Northborough, both of MA (US);
Kourosh Gharachorloo, Stanford, CA
(US)
(73) Assignee: Compaq Computer Corporation,
Houston, TX (US)
( * ) Notice: This patent issued on a continued prosecution application filed under 37 CFR 1.53(d), and is subject to the twenty year patent term provisions of 35 U.S.C. 154(a)(2).
Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 09/084,621
(22) Filed: May 26, 1998
(51) Int. C I. G06F 12/00
(52) U.S. CI 711/207; 711/206; 711/152;
711/208; 711/154
(58) Field of Search 711/206, 203,
711/207, 211, 151, 152, 208, 154, 143,
147
(56) References Cited
U.S. PATENT DOCUMENTS
5,182,808 * 1/1993 Bagnoli et al 710/119
A technique selectively imposes inter-reference ordering between memory reference operations issued by a processor of a multiprocessor system to addresses within a page pertaining to a page table entry (PTE) that is affected by a translation buffer (TB) miss flow routine. The TB miss flow is used to retrieve information contained in the PTE for mapping a virtual address to a physical address and, subsequently, to allow retrieval of data at the mapped physical address. The PTE that is retrieved in response to a memory reference (read) operation is not loaded into the TB until a commit-signal associated with that read operation is returned to the processor. Once the PTE and associated commit-signal are returned, the processor loads the PTE into the TB so that it can be used for a subsequent read operation directed to the data at the physical address.
10 Claims, 11 Drawing Sheets
