Retrograde well structure for a CMOS imager

(54) RETROGRADE WELL STRUCTURE FOR A CMOS IMAGER

(75) Inventors: Howard E. Rhodes, Boise, ID (US);

Mark Durcan, Boise, ID (US)

(73) Assignee: Micron Technology, Inc., Boise, ID (US)

( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

This patent is subject to a terminal disclaimer.

(21) Appl. No.: 10/295,952

(22) Filed: Nov. 18, 2002

(65) Prior Publication Data

US 2003/0173572 Al Sep. 18, 2003

Related U.S. Application Data

(60) Continuation ol application No. 09/918,450, filed on Aug. 1, 2001, now Pat. No. 6,483,129, which is a division ol application No. 09/334,261, filed on Jun. 16,1999, now Pat. No. 6,310,366.

(51) Int. CI.7 H01L 31/109

(52) U.S. CI 257/185; 257/431; 257/655

(58) Field of Search 257/185, 431,

257/655, 917

A retrograde well structure for a CMOS imager that improves the quantum efficiency and signal-to-noise ratio ol the imager. The retrograde well comprises a doped region with a vertically graded dopant concentration that is lowest at the substrate surface, and highest at the bottom ol the well. A single retrograde well may have a single pixel sensor cell, multiple pixel sensor cells, or even an entire array ol pixel sensor cells formed therein. The highly concentrated region at the bottom ol the retrograde well repels signal carriers from the photosensor so that they are not lost to the substrate, and prevents noise carriers from the substrate from diffusing up into the photosensor. Also disclosed are methods for forming the retrograde well.

33 Claims, 8 Drawing Sheets

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