(12) United States Patent ao) Patent No.: us 6,680,991 Bi
Gutierrez (45) Date of Patent: Jan. 20,2004
(58) Field of Search 375/324, 326,
375/327, 344, 354, 357, 371, 373, 374, 375, 376; 331/1 A, 1 R, 18, 25, 34, 37, 40; 327/212, 159, 156; 370/395.62, 503, 516; 455/182.2, 192.2, 255
(56) References Cited
U.S. PATENT DOCUMENTS
5,629,651 A * 5/1997 Mizuno 331/34
6,081,572 A * 6/2000 Filip 375/376
6,242,956 Bl * 6/2001 McCollough et al 327/159
6,314,150 Bl * 11/2001 Vowe 375/374
OTHER PUBLICATIONS
Gutierrez, G. et al; 2.488 Gb/s Silicon Bipolar Clock and Data Recovery ICfor SONET OC-48), IEEE 1998 Custom Integrated Circuits Conference, pp. 575-578. Gutierrez, G. et al.; Unaided 2.5 Gv/s Silicon Bipolar Clock and Data Recovery IC, 1998 IEEE Radio Frequency Integrated Circuits Symposium, pp. 173-176.
Kim, D. et al: A l.OGbps Clock and Data Recovery Circuit with Two—XOR Phase-Frequency Detector, Dept. of Electrical and Computer Engineering, Inha University, Inchon 402-751, Korea.
Miiller, E.;A 20 Gbit/s Parallel Phase Detector and Demultiplexer Circuit in a Production Silicon bipolar Technology with fT=25 GHz, IEEE BCTM 2.2, pp. 43-45. Noguchi, H. et al; A 9.9G-10.8Gb/s Rate-Adaptive Clock and Data—Recovery with No External Reference Clock for WDM Optical Fiber Transmission, ISSCC 2002 Session 15 Gigabit Communications, Paper 15.3. Pottbacker, A. et al.; A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s, IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec. 1992. Savoj, J. et al.; Design of Half—Rate Clock and Data Recovery Circuits for Optical Communications Systems, DAC 2001, Jun. 18-22, 2001, Las Vegas, Nevada, Copyright 2001.
Wang, H. et al.; AlGb/s CMOS Clock and Data Recovery Circuit, 1999 IEEE International Solid-State Circuits Conference, ISSCC99, Feb. 17, 1999, Session 20, Paper 20.5. Wurzer, M. et al.; 40 Gb/S Inegrated Clock and Data Recovery Circuit in a Silicon Bipolar Technology, IEEE BCTM 8.1. pp. 136-139.
* cited by examiner
Primary Examiner—Chieh M. Fan
(74) Attorney, Agent, or Firm—Fenwick & West LLP
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A lock detector is described for detecting a difference between the frequencies of a first and a second input signal. The lock detector includes first and second beat generators configured to generate corresponding beat signals based on the first and second input signals. The second beat signal is phase shifted relative to the first beat signal. A chatter elimination module combines the two chattery beat signals to produce a third corresponding beat signal that is substantially free of chatter. Using this clean beat signal and either of the input signals, a lock detection module produces a lock detection signal, which indicates whether the difference between the frequencies of the first and second input signals is within a prescribed tolerance.
21 Claims, 4 Drawing Sheets
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