5,787,490 A * 7/1998 Ozawa 709/103
5,802,338 A 9/1998 Rechtschaffen et al.
5,809,528 A 9/1998 Miller et al.
5.809.531 A 9/1998 Brabandt
5,875,465 A 2/1999 Kilpatrick et al.
5,913,224 A 6/1999 MacDonald
5,974,507 A 10/1999 Arimilli et al.
5,983,321 A 11/1999 Tran et al.
6,115,792 A * 9/2000 Tran 711/128
6,148,370 A * 11/2000 Kobayashi 711/118
6,161,167 A 12/2000 Witt
6,185,657 Bl 2/2001 Moyer 711/128
6,185,703 Bl * 2/2001 Guddat et al 714/718
6,237,083 Bl 5/2001 Favor
6,240,432 Bl 5/2001 Chuang et al.
6.240.532 Bl * 5/2001 Cho 714/42
6,263,082 Bl 7/2001 Ishimoto et al.
6,269,427 Bl 7/2001 Kuttanna et al.
6,295,608 Bl 9/2001 Parkes et al.
6,351,789 Bl 2/2002 Green
6,405,287 Bl 6/2002 Lesartre 711/128
6,606,686 Bl * 8/2003 Agarwala et al 711/129
OTHER PUBLICATIONS
Intel® StrongARM® SA-1100 Microprocessor, Developer's Manual, Aug. 1999, © Intel Corporation, Ch. 1, p. 6; Ch. 2, p. 2; Ch. 6, pp. 2-5; Ch. 7, p. 3.
"Memory Arbitration with Out ol Order Execution in Conjunction with a RISC System," IBM Technical Disclosure Bulletin, Sep. 1992, pp. 62-64.
"Handling Reservations in Multiple-Level Cache," IBM
Technical Disclosure Bulletin, Dec. 1993, pp. 441-446.
Stepanian, SiByte, SiByte SB-1 MIPS64 CPU Core,
Embedded Processor Forum 2000, Jun. 13,2 000, 15 pages.
Dekker et al., "A Realistic Fault Model and Test Algorithms
for Static Random Access Memories," IEEE Transactions on
Computer-Aided Design, vol. 9, No. 6, Jun. 1990, pp.
567-572.
Halfhill, "SiByte Reveals 64-bit Core for NPUs," Micro-
processor Report, Jun. 2000, pp. 45-48.
Cyrix® 5x86 Microprocessor, Jul. 1995, 8 pgs.
Cyrix® 6=86 Mircoprocessor, Aug. 1995, 6 pgs.
* cited by examiner