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(12) United States Patent

Rowlands et al.

US006732234B1

(io) Patent No.: US 6,732,234 Bl (45) Date of Patent: May 4,2004

(54) DIRECT ACCESS MODE FOR A CACHE

(75) Inventors: Joseph B. Rowlands, Santa Clara, CA (US); Michael P. Dickman, San Jose, CA (US)

(73) Assignee: Broadcom Corporation, Irvine, CA (US)

( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 125 days.

(21) Appl. No.: 09/633,544

(22) Filed: Aug. 7, 2000

(51) Int. CI.7 G06F 12/00

(52) U.S. CI 711/117; 711/118; 711/128;

711/133; 711/136; 711/145; 711/702; 711/108;

711/119

(58) Field of Search 711/117, 118,

711/128, 133, 160, 136, 139, 145; 702/108,

119

(56) References Cited

U.S. PATENT DOCUMENTS

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A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons and hit determination used for memory transactions) and either read the data from the cache storage entry (for read transactions) or write data from the transaction to the cache storage entry (for write transactions). The direct access transactions may, for example, be used to perform testing ol the cache memory. As another example, direct access transactions may be used to perform a reset ol the cache (by writing known data to each cache entry). In embodiments employing error checking and correction (ECC) mechanisms, direct access write transactions could also be used to recover from uncorrectable ECC errors, by overwriting the lailing data to eliminate the errant data. In one embodiment, the cache may alter the state ol its replacement policy in response to a direct access transaction explicitly specilying a particular way ol the cache.

40 Claims, 13 Drawing Sheets

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5,787,490 A * 7/1998 Ozawa 709/103

5,802,338 A 9/1998 Rechtschaffen et al.

5,809,528 A 9/1998 Miller et al.

5.809.531 A 9/1998 Brabandt
5,875,465 A 2/1999 Kilpatrick et al.
5,913,224 A 6/1999 MacDonald
5,974,507 A 10/1999 Arimilli et al.
5,983,321 A 11/1999 Tran et al.

6,115,792 A * 9/2000 Tran 711/128

6,148,370 A * 11/2000 Kobayashi 711/118

6,161,167 A 12/2000 Witt

6,185,657 Bl 2/2001 Moyer 711/128

6,185,703 Bl * 2/2001 Guddat et al 714/718

6,237,083 Bl 5/2001 Favor

6,240,432 Bl 5/2001 Chuang et al.

6.240.532 Bl * 5/2001 Cho 714/42

6,263,082 Bl 7/2001 Ishimoto et al.

6,269,427 Bl 7/2001 Kuttanna et al.

6,295,608 Bl 9/2001 Parkes et al.

6,351,789 Bl 2/2002 Green

6,405,287 Bl 6/2002 Lesartre 711/128

6,606,686 Bl * 8/2003 Agarwala et al 711/129

OTHER PUBLICATIONS

Intel® StrongARM® SA-1100 Microprocessor, Developer's Manual, Aug. 1999, © Intel Corporation, Ch. 1, p. 6; Ch. 2, p. 2; Ch. 6, pp. 2-5; Ch. 7, p. 3.

"Memory Arbitration with Out ol Order Execution in Conjunction with a RISC System," IBM Technical Disclosure Bulletin, Sep. 1992, pp. 62-64.

"Handling Reservations in Multiple-Level Cache," IBM
Technical Disclosure Bulletin, Dec. 1993, pp. 441-446.
Stepanian, SiByte, SiByte SB-1 MIPS64 CPU Core,
Embedded Processor Forum 2000, Jun. 13,2 000, 15 pages.
Dekker et al., "A Realistic Fault Model and Test Algorithms
for Static Random Access Memories," IEEE Transactions on
Computer-Aided Design, vol. 9, No. 6, Jun. 1990, pp.
567-572.

Halfhill, "SiByte Reveals 64-bit Core for NPUs," Micro-
processor Report, Jun. 2000, pp. 45-48.
Cyrix® 5x86 Microprocessor, Jul. 1995, 8 pgs.
Cyrix® 6=86 Mircoprocessor, Aug. 1995, 6 pgs.

* cited by examiner

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