Area-efficient implication circuits for very dense lukasiewicz logic arrays ...

United States Patent

[19]

Mills

US005770966A [ii] Patent Number: 5,770,966 [45] Date of Patent: Jun. 23, 1998

[54] AREA-EFFICIENT IMPLICATION CIRCUITS FOR VERY DENSE LUKASIEWICZ LOGIC ARRAYS

[75] Inventor: Jonathan W. Mills, Bloomington, Ind.

[73] Assignee: Indiana University Foundation,

Bloomington, Ind.

[21] Appl. No.: 783,196

[22] Filed: Jan. 15, 1997

Related U.S. Application Data

[63] Continuation of Ser. No. 887,711, May 22, 1992, abandoned.

[51] Int. CI. H03K 3/02

[52] U.S. CI 327/355; 327/538; 327/543

[58] Field of Search 326/35, 36, 119,

326/127, 133; 327/215, 355, 350, 538, 543, 560, 568

[56] References Cited

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Primary Examiner—-Terry Cunningham

Attorney, Agent, or Firm—-Woodard, Emhardt, Naughton,

Moriarty & McNett

A one-diode circuit for negated implication (—») is derived from a 12-transistor Lukasiewicz implication circuit (-»). The derivation also yields an adjustable three-transistor implication circuit with maximum error less than 1% ol lull scale. Two Lukasiewicz logic arrays (£LAs) are proposed that use area-efficient implementations ol the one-diode and three-transistor implication circuits. The very dense diodetower £LA contains 36,000 implications in an area that previously held 92 implications; the three-transistor £LA contains 1,990 implications. Both £LAs double the number ol inputs per pin on the IC package. Very dense £LAs make £LA-based luzzy controllers and neural networks practical. As an example, an £LA retina that detects edges in 15 nanoseconds is described.