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IIIH

US007117316B2

(12) United States Patent ao) Patent No.: Us 7,117,316 B2

Jeddeloh (45) Date of Patent: Oct. 3,2006

[merged small][merged small][table][merged small][merged small]

(51) Int. CI. G06F 13/00

(52) U.S. CI

(2006.01)

711/154; 711/118; 711/105;

711/109; 345/557

(58) Field of Classification Search 711/154,

711/118, 105, 109; 709/214; 345/557 See application file for complete search history.

(56) References Cited

U.S. PATENT DOCUMENTS

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(Continued)

Intel, Intel 840 Chipset: 82840 Memory Controller Hub (MCH), Oct. 1999, 298020-001, entirity.* "Free On-Line Dictionary of Computing" entry Flash Erasable Programmable Read-Only Memory, online May 17, 2004 [http://foldoc. doc.ic.ac.uk/foldoc/foldoc. cgi?flash+ memory].

Intel, "Flash Memory PCI Add-In Card for Embedded Systems", Application Note AP-758, Sep., 1997, pp. i—13. Shanley, T. et al., "PCI System Architecture", Third Edition, Mindshare, Inc., 1995, pp. 24-25.

Intel, "Intel 840 Chipset: 82840 Memory Controller Hub (MCH)", Datasheet, www. intel. com/ design/chipsets/ datashts/298020.htm, Oct. 1999, pp. 1-178.

Primary Examiner—Hong Kim

(74) Attorney, Agent, or Firm—Dorsey & Whitney, LLP

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A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices. The memory hub includes a row cache memory that stores data as they are read from the memory devices. When the memory module is not being accessed by the controller, a sequencer in the memory module generates requests to read data from a row of memory cells. The data read responsive to the generated read requests are also stored in the row cache memory. As a result, read data in the row being accessed may be stored in the row cache memory even though the data was not previously read from the memory device responsive to a memory request from the controller.

18 Claims, 2 Drawing Sheets

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Page 2

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cited by examiner

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