[54] SAFESTORE FRAME IMPLEMENTATION IN A CENTRAL PROCESSOR
[75] Inventors: Lowell D. McCulley; Russell W.
Guenthner; Clinton B. Eckard, all of
Glendale; Leonard Rabins,
Scottsdale; William A. Shelly,
Phoenix; Ronald E. Lange, Glendale;
David S. Edwards, Phoenix, all of
Ariz.
[73] Assignee: Bull HN Information Systems Inc.,
Billerica, Mass.
[21] Appl. No.: 682,801
[22] Filed: Apr. 9,1991
[51] Int. a.' G06F 11/00
[52] U.S. Q 395/575; 364/285.2;
364/D1G. 1; 371/12; 371/16.5
[58] Field of Search 371/12, 16.1, 16.5;
395/575; 364/285.2
[56] References Cited
U.S. PATENT DOCUMENTS 3,783,256 1/1974 Caputo et a] 371/12
3,784,801 1/1974 Caputo et al 371/12
4,697,266 9/1987 Finley 371/12
4,703,481 10/1987 Fremont 371/12
4,819,154 4/1989 Stiffler 395/575
4,853,932 8/1989 Nitschke et al 371/12
4,930,128 8/1989 Suzuki et al 371/12
Primary Examiner—Charles E. Atkinson
Attorney, Agent, or Firm—}. H. Phillips; J. S. Solakian
[57] ABSTRACT
In order to gather, store temporarily and deliver (if needed) central processor safestore information, a multiphase clock is employed to capture (one full clock cycle behind) the safestore information which typically includes all software visible registers in all (or selected) data manipulation chips of the CPU by routing the safestore information through temporary storage (under the influence of the multiphase clock) in a cache data array and into a special purpose XRAM module. Thus, upon the sensing of a fault, valid safestore information is available in the XRAM for analysis and, if appropriate, resumption of operation at a sequential point just previous to that at which the fault occurred.
5 Claims, 3 Drawing Sheets
