(12) United States Patent ao) Patent No.: us 6,432,754 Bi
Assaderaghi et al. (45) Date of Patent: Aug. 13,2002
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* cited by examiner
Primary Examiner—Hoai Ho
Assistant Examiner—Quoc Hoang
(74) Attorney, Agent, or Firm—Scully, Scott, Murphy & Presser; H. Daniel Schnurmann
The present invention provides various methods for forming a ground-plane SOI device which comprises at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer; and an oxide region present beneath the field effect transistor, located in an area between source and drain regions which are formed in said SOI wafer, said oxide region is butted against shallow extensions formed in said SOI wafer, and is laterally adjacent to said source and drain regions.
24 Claims, 8 Drawing Sheets