United States Patent [19]
Johnson
...
US005136697A
[ii] Patent Number: 5,136,697 [45] Date of Patent: Aug. 4, 1992
[54] SYSTEM FOR REDUCING DELAY FOR
EXECUTION SUBSEQUENT TO
CORRECTLY PREDICTED BRANCH
INSTRUCTION USING FETCH
INFORMATION STORED WITH EACH
BLOCK OF INSTRUCTIONS IN CACHE
[75] Inventor: William M. Johnson, San Jose, Calif.
[73] Assignee: Advanced Micro Devices, Inc., Austin, Tex.
[21] Appl. No.: 361,870
[22] Filed: Jun. 6, 1989
[51] Int. CI.' G06F9/38
[52] U.S. CI 395/375; 364/230.6;
364/231.8; 364/243.3; 364/243.42; 364/261.5;
364/261.7; 364/255.7; 364/931.41; 364/228.9; 364/948; 364/938.1; 364/938.2; 395/800 [58] Field of Search ... 364/200 MS File, 900 MS File
[56] References Cited
U.S. PATENT DOCUMENTS
4,200,927 4/1980 Hughes et al 364/200
4,295,193 10/1981 Pomerene 364/200
4,430,706 2/1984 Sand 364/200
4,477,872 10/1984 Losq et al 364/200
4,604,691 8/1986 Akagi 364/200
4,755,966 7/1988 Lee et al 364/900
■4,764,861 8/1988 Shibuya 364/200
4,807,115 2/1989 Torng 364/200
4,858,i04 8/1989 Matsuo et al. 364/200
4,860,197 8/1989 Langendorf et al 364/200
4,894,772 1/1990 Langendorf 364/200
Primary Examiner—Thomas C. Lee
Assistant Examiner—Ken S. Kim
Attorney, Agent, or Firm—Foley & Lardner
[57] ABSTRACT
A super-sealer processor is disclosed wherein branchprediction information is provided within an instruction cache memory. Each instruction cache block stored in the instruction cache memory includes branch-prediction information fields in addition to instruction fields, which indicate the address of the instruction block's successor and information indicating the location of a branch instruction within the instruction block. Thus, the next cache block can be easily fetched without waiting on a decoder or execution unit to indicate the proper fetch action to be taken for correctly predicted branching.
12 Claims, 7 Drawing Sheets
