(54) LOW BITLINE CAPACITANCE STRUCTURE AND METHOD OF MAKING SAME
(75) Inventors: Ramachandra Divakaruni, Somers, NY (US); Jeffrey P. Gambino, Westford, VT (US); Jack A. Mandelman, Stormville; Rajesh Rengarajan, Poughkeepsie, both of NY (US)
(73) Assignees: International Business Machines Corporation, Armonk, NY (US); Infineon Technologies North American Corp., San Jose, CA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 8 days.
(21) Appl. No.: 09/764,824
(22) Filed: Jan. 17, 2001
(51) Int. CI.7 H01L 21/338; H01L 21/461;
(52) U.S. CI 438/185; 438/740; 438/761
(58) Field of Search 438/185, 761,
(56) References Cited
U.S. PATENT DOCUMENTS
5,518,961 A * 5/1996 Ishimara 438/586
6,058,065 A 5/2000 Lattimore et al 365/230.03
A method for forming a memory device having low bitline capacitance, comprising: providing a gate conductor stack structure on a silicon substrate, said gate stack structure having a gate oxide layer, a polysilicon layer, a silicide layer, and a top dielectric nitride layer; oxidizing sidewalls of said gate oxide stack; forming sidewall spacers on the sidewalls of said gate conductor stack, said sidewall spacers comprising a thin layer of nitride having a thickness ranging from about 50 to about 250 angstroms; overlaying the gate structure with a thin nitride liner having a thickness ranging from about 25 to about 150 angstroms; depositing an insulative oxide layer over the gate structure; polishing the insulative oxide layer down to the level of the nitride liner of the gate structure; patterning and etching the insulative oxide layer to expose said nitride liner; forming second sidewall spacers over said first sidewall spacers, said second sidewall spacers comprising an oxide layer having a thickness ranging from about 100 to about 400 angstroms; and, depositing and planarizing a layer of polysilicon covering said gate structure and the sidewall spacers.
10 Claims, 4 Drawing Sheets