Synchronous clock generator including delay-locked loop

United States Patent [w]

Harrison et al.

[54] SYNCHRONOUS CLOCK GENERATOR INCLUDING DELAY-LOCKED LOOP

[75] Inventors: Ronnie M. Harrison; Brent Keeth,

both of Boise, Id.

[73] Assignee: Micron Technology, Inc., Boise, Id.

[ * ] Notice: This patent issued on a continued prosecution application filed under 37 CFR 1.53(d), and is subject to the twenty year patent term provisions of 35 U.S.C. 154(a)(2).

[21] Appl. No.: 08/799,661 [22] Filed: Feb. 11, 1997

[51] Int. CI. G11C 7/10

[52] U.S. CI 365/233; 365/194; 327/155;

327/158

[58] Field of Search 365/233, 194,

365/189.05, 189.07; 327/155, 156, 158,

161

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Primary Examiner—Son T. Dinh

Attorney, Agent, or Firm—Seed and Berry LLP

[57] ABSTRACT

A data and command latching circuit includes a delaylocked loop driven by a continuous reference clock signal that generates a delayed output clock signal having a delay controlled by the delay-locked loop. The latching circuit also includes a variable delay circuit external to the delay-locked loop that is driven by a discontinuous reference clock signal. Delay of the external delay circuit is controlled by a control voltage output from the delay-locked loop, so that the delays of the external delay circuit are determined with reference to the continuous reference clock signal. The delayed clock signals from the delay-locked loop activate control data latches to latch control data arriving at the latch circuit. The delayed signals from the variable voltage circuit activate data latches to latch data arriving at the latch circuit.

10 Claims, 5 Drawing Sheets

CCL'REF j DCLKREF!

,CCLKD

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