(i9) United States
(12) Patent Application Publication
Hareland et al.
(54) NONPLANAR SEMICONDUCTOR DEVICE
WITH PARTIALLY OR FULLY WRAPPED
AROUND GATE ELECTRODE AND
METHODS OF FABRICATION
(75) Inventors: Scott A. Hareland, Tigard, OR
(US); Robert S. Chau, Beaverton,
OR (US); Brian S. Doyle, Portland,
OR (US); Rafael Rios, Portland,
OR (US); Tom Linton, San Jose,
CA (US); Suman Datta, Beaverton,
OR (US)
Correspondence Address:
INTEL/BSTZ
BLAKELY SOKOLOFF TAYLOR & ZAFMAN
LLP
1279 OAKMEAD PARKWAY
SUNNYVALE, CA 94085-4040 (US)
(73) Assignee: Intel Corporation, Santa Clara, CA (US)
(21) Appl.No.: 12/259,464
(22) Filed: Oct. 28, 2008
Related U.S. Application Data
(62) Division of application No. 10/607,769, filed on Jun. 27, 2003, now Pat. No. 7,456,476.
Publication Classification
(51) Int. CI.
H01L 21/336 (2006.01)
(52) U.S. CI 438/157; 257/E21.411
(57) ABSTRACT
A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
