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US006643181B2

(12) United States Patent ao) Patent No.: us 6,643,181 B2

Sofer et al. (45) Date of Patent: Nov. 4,2003

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U.S. PATENT DOCUMENTS

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U.S. patent application Ser. No. 09/211,981, Eitan, filed Dec. 14, 1998.

U.S. patent application Ser. No. 09/348,720, Eitan, filed Jul. 6, 1999.

U.S. patent application Ser. No. 09/413,408, Eitan, filed Oct.

6, 1999.

U.S. patent application Ser. No. 09/730,586, Bloom et al, filed Dec. 7, 2000.

U.S. patent application Ser. No. 09/536,125, Eitan et al., filed Mar. 28, 2000.

Chan et al., "ATrue Single-Transistor Oxide-Nitride-Oxide EEPROM Device," IEEE Electron Device Letters, vol. EDL-8, No. 3, Mar., 1987.

Chang, J., "Non Volatile Semiconductor Memory Devices," Proceedings of the IEEE, vol. 64 No. 7, pp. 1039-1059, Jul, 1976.

Eitan et al., "Hot-Electron Injection into the Oxide in
n-Channel MOS Devices," IEEE Transactions on Electron
Devices, vol. ED-28, No. 3, pp. 328-340, Mar. 1981.
Lee, H., "A New Approach For the Floating-Gate MOS
Nonvolatile Memory", Applied Physics Letters, vol. 31, No.

7, pp. 475-476, Oct. 1977.

Ma et al, "A dual-bit Split-Gate EEPROM (DSG) Cell in Contactless Array for Single-Vcc High Density Flash Memories," IEEE, pp. 3.5.1-3.5.4, 1994. Ohshima et al., "Process and Device Technologies for 16Mbit Eproms with Large—Tilt—Angle implanted P-Pocket Cell," IEEE, CH2865-4/90/0000-0095, pp. 5.2.1-5.2.4, Dec, 1990.

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Ricco, Bruno et al., "Nonvolatile Multilevel Memories for Digital Applications," IEEE, vol. 86, No. 12, pp. 2399-2421, Dec, 1998.

Roy, Anirban "Characterization and Modeling of Charge Trapping and Retention in Novel Multi-Dielectric Nonvolatile Semiconductor Memory Devices," Doctoral Dissertation, Sherman Fairchild Center, Department of Computer Science and Electrical Engineering, pp. 1-35, 1989. "2 Bit/Cell EEPROM Cell Using Band-To-Band Tunneling For Data Read-Out," IBM Technical Disclosure Bulletin, U.S. IBM Corp. NY vol. 35, No. 4B, ISSN:0018-8689, Sep., 1992.

Tseng, Hsing-Huang et al., "Thin CVD Stacked Gate Dielectric for ULSI Technology", IEEE, 0-7803-1450-6, 1993.

Pickar, K.A., "Ion Implantation in Silicon," Applied Solid State Science, vol. 5, R. Wolfe Edition, Academic Press, New York, 1975.

Bhattacharyya et al., "FET Gate Structure for Nonvolatile N-Channel Read-Mostly Memory Device," IBM Technical Disclosure Bulletin, U.S. IBM Corp. vol. 18, No. 6, p. 1768, Nov., 1975.

Bude et al, "EEPROM/Flash Sub 3.0 V Drain-Source Bias Hot carrier Writing", IEDM 95, pp. 989-992.

Bude et al., "Secondary Electron Flash—a High Performance, Low Power Flash Technology for 0.35 um and Below", IEDM 97, pp. 279-282.

Bude et al., "Modeling Nonequilibrium Hot Carrier Device Effects", Conference of Insulator Specialists of Europe, Sweden, Jun., 1997.

* cited by examiner

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