Method of adjusting the threshold voltage in an SOI CMOS

(54) METHOD OF ADJUSTING THE

THRESHOLD VOLTAGE IN AN SOI CMOS

(75) Inventor: Shunpei Yamazaki, Tokyo (JP)

(73) Assignee: Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)

( * ) Notice: This patent issued on a continued prosecution application filed under 37 CFR 1.53(d), and is subject to the twenty year patent term provisions ol 35 U.S.C. 154(a)(2).

Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

(21) Appl. No.: 09/141,778

(22) Filed: Aug. 27, 1998

(30) Foreign Application Priority Data

Aug. 29, 1997 (JP) 9-249817

Sep. 3, 1997 (JP) 9-254258

(51) Int. CI.7 H01L 21/00; H01L 21/84

(52) U.S. CI 438/158; 438/163

(58) Field of Search 257/66, 67, 69,

257/57, 347; 438/795, 151, 157, 158, 163,

153

(56) References Cited

U.S. PATENT DOCUMENTS

5,397,718 * 3/1995 Furata et al 438/158

5,536,950 * 7/1996 Liu et al 257/59

5,567,959 * 10/1996 Mineji 257/69

5,591,650 * 1/1997 Hsu et al 438/163

5,729,308 * 3/1998 Yamazaki et al 349/39

5,789,762 * 8/1998 Koyama et al 257/66

5,808,321 * 9/1998 Mitanaga et al 257/72

5,821,137 * 10/1998 Wakai et al 438/163

5,837,619 * 11/1998 Adachi et al 438/795

5,854,494 * 12/1998 Yamazaki et al 257/57

5,903,014 5/1999 Ino et al. .

5,923,963 * 7/1999 Yamanaka 438/157

6,031,249 * 2/2000 Yamazaki et al 257/66

6,091,115 * 7/2000 Ohtani et al 257/369

OTHER PUBLICATIONS

S. Woll and R.N. Tauber, Silicon Processing, vol. 1., Lattice
Press, pp. 225, Dec. 1986.*

Sze, "Semiconductor Devices Physics and Technology",
John Wiley & Sons, pp. 417-419, 1985.
Hayashi, et al., "Fabrication ol Low-Temperature Bottom-
Gate Poly-Si TFTs on Large-Area Substrate by Linear-
Beam Excimer Laser Crystallization and Ion Doping
Method", IEDM 95, pp. 829-832.

* cited by examiner

Primary Examiner—Olik Chaudhuri

Assistant Examiner—-William David Coleman

(74) Attorney, Agent, or Firm—Fish & Richardson PC.

(57) ABSTRACT

This invention is related to a method for controlling a threshold voltage ol a bottom gate type thin film transistor as follows. Gate electrodes and a gate insulating film are formed on a glass substrate. An amorphous silicon film is formed thereon and then crystallized into a crystalline silicon film. After a buffer layer is formed thereon, an impurity element (selected from Group 13 or Group 15 elements) for a threshold voltage control is added to the crystalline silicon film by ion implantation or ion doping.

62 Claims, 19 Drawing Sheets