United States Patent w
Vora
[ii] Patent Number: 4,764,480 [45] Date of Patent: Aug. 16, 1988
[54] PROCESS FOR MAKING HIGH
PERFORMANCE CMOS AND BIPOLAR
INTEGRATED DEVICES ON ONE
SUBSTRATE WITH REDUCED CELL SIZE
[75] Inventor: Madhukar B. Vora, Los Gatos, Calif.
[73] Assignee: National Semiconductor Corporation, Santa Clara, Calif.
[21] Appl. No.: 113,417
[22] Filed: Oct. 23, 1987
Related U.S. Application Data
[63] Continuation of Ser. No. 946,108, Dec. 22, 1986, abandoned, which is a continuation of Ser. No. 718,392, Apr. 1, 1985, abandoned.
[51] Int. a.* H01L 21/22; H01L 21/225
[52] U.S. CI 437/054; 357/42;
357/91; 437/56; 437/69; 437/162
[58] Field of Search 437/54, 56, 69, 162;
357/42, 91
[56] References Cited
U.S. PATENT DOCUMENTS
4,375,999 3/1983 Nawata !148/187
4,384,301 5/1983 Tasch, Jr. et al 29/591
4,445,268 5/1984 Hirao 29/577 C
4,450,620 5/1984 Fuls et al 29/571
4,462,149 7/1984 Schwabe 29/571
4,484,388 11/1984 Iwasaki 29/571
4,507,847 4/1985 Sullivan 29/576 B
4,519,126 5/1985 Hsu 29/571
4,536,945 8/1985 Gray et al 29/571
4,569,123 2/1986 Ishii 29/578
OTHER PUBLICATIONS
Momose et al., IEEE-Trans. Electron Devices, vol.
ED-32 (1985), 217.
Vora et al, Reprint of a Seminar Talk, Sep. 1984.
Basic I.C. Engineering, ed. Hamilton, D. J.,
McGraw-Hill, NY, 1975, pp. 198-207.
Microelectronics, ed. Millman, McGraw-Hill, N.Y.,
1979, p. 104.
Primary Examiner—Upendra Roy
Attorney, Agent, or Firm—Lee Patch; Robert C. Colwell
[57] ABSTRACT
There is disclosed a high performance MOS transistor structure of either the N channel or P channel variety and a high performance bipolar transistor structure. A process is disclosed which can make high performance CMOS and high performance bipolar devices on the same die.
9 Claims, 8 Drawing Sheets
