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US006233724B1
(12) United States Patent ao) Patent No.: us 6,233,724 Bi
LaBerge (45) Date of Patent: May 15,2001
(54) CIRCUIT SYNTHESIS TIME BUDGETING BASED UPON WIRELOAD INFORMATION
(75) Inventor: Paul A. LaBerge, Shoreview, MN (US)
(73) Assignee: Micron Technology, Inc., Boise, ID (US)
( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 09/183,782
(22) Filed: Oct. 30, 1998
(51) Int. C I. G06F 17 50
(52) U.S. CI 716/18; 716/6; 716/3
(58) Field of Search 716/1-21
(56) References Cited
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OTHER PUBLICATIONS
Alessi et al. ("Integrating logic synthesis into a full chip ASIC design system", Proceedings of Second Annual IEEE ASIC Seminar and Exhibit, 1989, Sep. 25, 1989, pp. P2-2/ 1-4).*