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US006233724B1

(12) United States Patent ao) Patent No.: us 6,233,724 Bi

LaBerge (45) Date of Patent: May 15,2001

(54) CIRCUIT SYNTHESIS TIME BUDGETING BASED UPON WIRELOAD INFORMATION

(75) Inventor: Paul A. LaBerge, Shoreview, MN (US)

(73) Assignee: Micron Technology, Inc., Boise, ID (US)

( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

(21) Appl. No.: 09/183,782

(22) Filed: Oct. 30, 1998

(51) Int. C I. G06F 17 50

(52) U.S. CI 716/18; 716/6; 716/3

(58) Field of Search 716/1-21

(56) References Cited

U.S. PATENT DOCUMENTS

5,426,591 * 6/1995 Ginetti et al 716/6

5,586,046 * 12/1996 Feldbaumer et al 716/18

5,629,860 * 5/1997 Jones et al 716/6

5,650,937 * 7/1997 Bootehsaz et al 716/6

5,754,826 * 5/1998 Gamal et al 703/14

5,764,525 * 6/1998 Mahmood et al 716/18

5,812,416 * 9/1998 Gupte et al 716/2

5,831,868 * 11/1998 Beausang et al 716/18

5,867,396 * 2/1999 Parlour 716/18

5,903,466 * 5/1999 Beausang et al 716/18

5,910,897 * 6/1999 Dangelo et al 716/19

5,933,356 * 8/1999 Rostoker et al 703/15

6,026,228 * 2/2000 Imai et al 716/18

6,066,178 * 5/2000 Bair et al 716/2

OTHER PUBLICATIONS

Alessi et al. ("Integrating logic synthesis into a full chip ASIC design system", Proceedings of Second Annual IEEE ASIC Seminar and Exhibit, 1989, Sep. 25, 1989, pp. P2-2/ 1-4).*

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One embodiment of the present invention provides a system for synthesizing a circuit that allocates propagation delay between modules in the circuit based upon wireload information. The system receives a circuit divided into modules coupled together by a number of signal lines. The system defines a first set of timing constraints, and uses the first set of timing constraints to compile the circuit from a hardware description language specification into a first gate-level implementation. Next, the system performs a timing analysis on the first gate-level implementation to determine positive or negative slack values for the signal lines. These slack values specify amounts of extra propagation delay available on the signal lines. Next, the slack values are used to define a second set of timing constraints by allocating the slack values between the modules based upon wireload information. This wireload information may include such parameters as gate delays and drive strengths for gates coupled to the signal lines. The second set of timing constraints is used to compile the circuit into a second gate-level implementation. If necessary, the process of compilation, timing analysis and allocation of slack values may be repeated until the circuit meets all timing constraints.

25 Claims, 5 Drawing Sheets

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