Folding circuit

United States Patent [19]

Colleran et al.

[li] Patent Number: [45] Date of Patent:

5,376,937 Dec. 27,1994

[54] FOLDING CIRCUIT

[75] Inventors: William T. Colleran, Manhattan Beach; Asad A. Abidi, Pacific Palisades, both of Calif.

[73] Assignee: The Regents of the University of California, Oakland, Calif.

[21] Appl. No.: 20,477

[22] Filed: Feb. 22, 1993

[51] Int. CI.* H03M 1/36

[52] U.S. CI 341/159; 341/155

[58] Field of Search 341/155, 158, 159

[56] References Cited

U.S. PATENT DOCUMENTS

2,922,151 1/1960 Reiling 340/347

3,573,798 4/1971 Reiling 340/347

4,270,118 5/1981 Brokaw 340/347

4,297,679 10/1981 Arbel et al 340/347

4,325,054 4/1982 van de Plassche 340/347

4,386,339 5/1983 Henry et al 340/347

4,456,904 6/1984 van de Grift 340/347

4,617,523 10/1986 Taylor: 330/261

4,816,831 3/1989 Mizoguchi et al 341/156

4,839,653 6/1989 Devito 341/157

4,924,227 5/1990 Mangelsdorf 341/159

5,157,397 10/1992 Vernon 341/157

5,231,399 7/1993 Gorman et al 341/159

FOREIGN PATENT DOCUMENTS

1497806 1/1978 United Kingdom . WO9208288 5/1992 WIPO .

OTHER PUBLICATIONS

W. T. Colleran et al., "Compact high speed A/D converters", Final Report 1990-91, Micro Project No. 90-002.

W. T. Colleran et al., "Highly integrated gigahertz A/D converters", Final Report 1989-90, Micro Project No. 89-164.

W. T. Colleran et al., "Compact high frequency A/D converters", Micro Program, 1988-89.

R. Petschacher, et al., "A 10-b 75-MSPS subranging A/D converter with integrated sample and hold", IEEE Journal of Solid-State Circuits, vol. 25, No. 6, pp. 1339-1346, Dec. 1990.

R. E. J. van de Grift et al., "An 8 bit video ADC incorporating folding and interpolation techniques", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 6, pp. 944-953, Dec. 1987.

J. J. Corcoran, et al., "A 400MHz 6b ADC", in International Solid State Circuits Conference, pp. 294—295, IEEE. Feb. 1984.

A. Arbel et al., "Fast ADC", IEEE Transactions on Nuclear Science, vol. NS-22, Feb. 1975. U. Fiedler et al., "A high-speed 8 bit A/D converter based on a gray-code multiple folding circuit", IEEE Journal of Solid-State Circuits, vol. SC-14, No. 3, pp. 547-551, Jun. 1979.

(List continued on next page.)

Primary Examiner—Brian K. Young

Attorney, Agent, or Firm—Spensley Horn Jubas &

Lubitz

A folding circuit includes a differential resistance ladder and a plurality of comparators coupled to the differential resistance ladder in a manner which substantially reduces capacitive loading on the differential ladder. In addition, the folding circuit has a minimum number of output resistors to facilitate resistor matching for precision outputs. In another aspect of the invention, the folding circuit has a replica gain matching circuit which includes a replica comparator of predetermined size, which is coupled to a replica differential ladder at a predetermined location so as to replicate the currents drawn by the comparators coupled to the main differential resistance ladder for precise gain matching.

17 Claims, 8 Drawing Sheets

OTHER PUBLICATIONS

D. Daniel et al., "A silicon bipolar 4-bit 1-Gsample/s full nyquist A/D converter", IEEE Journal of Solid State Circuits, vol. SC-23, No. 3, pp. 742-749, Jun. 1988. R. J. van de Plassche et al., "An 8-bit 100-MHz full-nyquist analog-to-digital converter", IEEE Journal of Solid State Circuits, vol. 23, No. 6, pp. 1334-1344, Dec. 1988.

R. J. van de Plassche et al., "An 8b 100MHz folding

ADC", in International Solid State Circuits Conference, pp. 222-223, IEEE, Feb. 1988.

R. E. J. van de Grift et al., "An 8b 50MHz video ADC with folding and interpolation techniques", in International Solid State Circuits Conference, pp. 94-95, IEEE, Feb. 1987.

B. Gilbert, "Monolithic analog READ-ONLY memory for character generation", IEEE Journal of Solid State Circuits, vol. SC-6, pp. 45-55, Feb. 1971. J. V. Woods et al., "Fast synthesized cyclic-parallel analogue-digital converter", IEEE Proceedings, vol. 127, pp. 45, 51, Apr. 1980.