TECHNIQUE FOR INCORPORATING A
BUTLT-IN SELF-TEST (BIST) OF A DRAM
BLOCK WITH EXISTING FUNCTIONAL
TEST VECTORS FOR A MICROPROCESSOR
FIELD OF THE INVENTION
The present invention relates to testing of dynamic random access memories (DRAM), and particularly to a builtin self-test (BIST) for a DRAM array incorporated into a microprocessor such that the built-in self-test can operate in a background mode while functional tests are being run on the microprocessor core.
DESCRIPTION OF THE RELATED ART
Ml: WO IM2: RO,W1 IMS: R1,WO DM1: RO,W1 DM2: R1,WO
In some RAMs the read/write logic includes a data latch. In such RAMs, detection of stuck open faults is not guaranteed by the 9N test algorithm set forth above because the last read data of the memory is stored in the data latch. If a stuck-open cell is read, the contents of the data latch will be passed to the output pin. If this is the expected data to be read
from the memory, the stock open fault will not be detected. Consequently, for RAMs employing a data latch, a 13N test algorithm is used (the data latch is used to broaden the read window of the RAM during normal operation). The 13N test 5 algorithm is set forth in Table 2 below:
TABLE 2
13NTest
10 Ml: WO
M2: RO,W1,R1
M3: R1,WO,RO
DM1: RO,W1,R1
DM2: R1,WO,RO
DRAM arrays are susceptible to process related failures such as those resulting from dust particles on the chips or the masks, scratches and gate oxide pinholes, which may result in shorts or opens in the circuit. DRAM faults may be classified as stuck-at faults, stuck-open faults, transition 20 faults, state coupled faults, multiple access faults and data retention faults. Amemory cell is said to be stuck-at if aread from the cell is always at a certain logic value regardless of the action on the cell or influence from other cells. It can be caused by memory array faults or read/write logic faults. A 25 memory cell is said to be stuck-open if it can never be accessed. It can be caused by address decoder faults or read/write logic faults. A memory cell with a transition fault will fail to undergo at least one of the transitions 0 to 1, or 1 to 0. Transition faults are caused by memory array faults. 30 A memory cell is said to be state coupled to another cell if the first cell is fixed at a certain value only if the second cell is in one defined state. The testing of state coupled faults requires demonstrating that any arbitrary pair of cells in the memory is able to be in 0—0, 0-1, 1-0, and 1—1 states. 35 State coupled faults may be caused by memory array faults or read/write logic faults. A memory cell is said to have a multiple access fault if a read/write action accesses multiple cells. Multiple access faults can be caused by memory array faults or address decoder faults. Finally, a memory cell with 40 data retention fault is unable to retain the charge stored for a minimum required period.
A 9N test algorithm (where N is the number of addresses) may be used to test all of the faults outlined above. The 9N built-in self-test appears in Table 1 below. In what follows, 45 IMs denotes sweeping from address 0 to n-1; DMx denotes sweeping from address n-1 to 0; WO denotes writing a data background; RO denotes reading and comparing with data background; Wl denotes writing an inverted data background; and Rl denotes reading and comparing with an 50 inverted data background.
Further details regarding the 9N and 13N test algorithms may be found in Rob Dekker, Frans Beenker, LoekThussen, "A Realistic Fault Model & Test Algorithms for Static Random Access Memories," IEEE Log Number 9034766 (Jul. 10, 1989), which is hereby incorporated by reference.
As can be readily appreciated, performing a built in self test on even a relatively small RAM can take a relatively large amount of time. When the RAM is on a chip that also includes a processor core, the built-in self-test must generally be run after the processor core functional tests, because completion of any functional core tests will reset the entire chip. However, the built-in self-test is to be run upon every reset. Thus, the built-in self-test must be run after the core functional testing.
While adequate testing may be done in such a fashion, it takes a relatively long period of time. Increasingly, there is a desire for faster completion of various self tests. It would be advantageous to be able to perform the built-in self-test of an on-chip RAM at the same time as the processor core functional tests were being run. Moreover, it would be desirable to divide a built-in self test into several smaller patterns, individually selectable via an internal register accessible by the core functional test vectors and to allow the overlapping of the DRAM built-in self-test and existing core functional vectors to minimize test time without forcing a complete chip wide built-in self-test implementation.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, there is provided a processing unit having a CPU core and an integrated RAM and a test unit, which may be implemented in any of several ways, including as one or more state machines, or as microcode. A built-in self-test of a DRAM array is designed to run concurrently with the functional vectors used to test the microprocessor core. More particularly, once the core tests have been activated, a control register may be written to by the core tests, which will initiate the BIST. The BIST is divided into small patterns which are individually selectable via an internal register accessible by the functional test vectors. This allows the overlapping of the DRAM BIST and existing core functional vector testing to minimize test time without forcing a complete chip wide BIST implementation.
A first built-in self-test tests for all of the stuck-open, stuck-at, and transition faults. In addition, by running a plurality of patterns, the first test tests for state coupling faults in each word and half of the multiple access faults and state-coupling faults between words. A second built-in selftest tests for the remaining multiple access faults and the state-coupling faults between words. A data retention test tests whether the RAM can retain either a 1 or a 0 for a
