MOSFET STRUCTURE WITH MULTIPLE
SELF-ALIGNED SILICIDE CONTACTS
FIELD OF THE INVENTION
[0001] The present invention relates to a semiconductor structure, and more particularly to a metal oxide semiconductor field effect transistor (MOSFET) structure that contains multiple self-aligned silicide contacts. The present invention also provides methods for fabricating such a MOSFET structure.
BACKGROUND OF THE INVENTION
[0002] As metal oxide semiconductor field effect transistors (MOSFETs) scale down in size, higher performance can be achieved by bringing metal silicide contacts closer to the gate conductor. There are difficulties however in forming self-aligned metal silicide contacts close to the gate conductor edge. For example, relatively thick silicides (on the order of about 20 nm or greater), which are required to meet sheet resistivity in the diffusion and polycide, will consume silicon and can interfere with the integrity of an ultra shallow junction that is typically present near the gate edge under the spacer.
[0003] For ultra-thin body MOSFETs in which the device channel has a thickness of about 20 nm or less, the thickness of the silicon available to form a silicide contact is limited. So-called raised source/drain regions (RSD, or also called elevated source/drain regions) can mitigate this problem. However, RSD regions that are positioned close to the gate conductor edge will increase the capacitance between the gate and the source/drain regions.
[0004] In view of the above, there is a need for providing a MOSFET structure having self-aligned metal silicide contacts that are close to the gate conductor edge that do not consume sufficient silicon such that the integrity of the ultra shallow junction is not effected. Moreover, a MOSFET structure is needed in which the silicide located in proximity to the gate conductor edge does not increase the capacitance between the gate and the source/drain regions.
SUMMARY OF THE INVENTION
[0005] The present invention provides a solution to the problems mentioned in the background section of this application by utilizing two or more distinct regions of silicide. Specifically, the present invention provides a MOSFET structure that includes a silicide that is located outside of a gate spacer that is thick and of low resistivity, as is required for low resistivity local interconnects. Near the gate conductor edge and typically under the gate spacer, another silicide is provided that has a thickness that is less than the outer silicide. The thinner silicide has a higher resistivity than the thick outer silicide. The thinner silicide does not consume too much silicon during the processing thus avoiding the problems mentioned above.
[0006] Specifically, and in broad terms, the present invention provides a MOSFET structure that comprises:
[0007] at least one metal oxide semiconductor field effect transistor located on a surface of a Si-containing substrate, said at least one metal oxide semiconductor field effect transistor comprises at least a gate conductor having a gate edge;
[0008] a first inner silicide contact having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor, said first inner silicide contact having a first thickness and a first resistivity; and
[0009] a second outer silicide contact located adjacent to, i.e., self-aligned with, said first inner silicide contact, said second outer silicide contact having a second thickness and a second resistivity, wherein said second thickness is greater than the first thickness and second resistivity is lower than the first resistivity.
[0010] In addition to the MOSFET structure described above that includes multiple and distinct self-aligned silicide contacts, i.e., first inner silicide contact and second outer silicide contact, the present invention also provides methods of fabricating such a structure. A first method that is provided by the present invention comprises the steps of:
[0011] providing at least one metal oxide semiconductor field effect transistor comprising at least a gate conductor having a gate edge on a surface of a Sicontaining substrate, said gate edge including at least a wide spacer;
[0012] forming an outer silicide contact aligned to an outer edge of said wide spacer;
[0013] removing said wide spacer to expose a portion of said Si-containing substrate adjacent to said at least one metal oxide semiconductor field effect transistor; and
[0014] forming an inner silicide contact in said exposed portion of said semiconductor substrate, said inner silicide contact has an edge aligned to the gate edge, wherein said outer silicide contact has a thickness that is greater than the inner silicide contact and said outer silicide contact has a resistivity that is lower than the resistivity of the inner silicide contact.
[0015] A second method that is provided by the present invention differs from the first in that the inner silicide contact is formed prior to the outer silicide contact. Specifically, the second method of the present invention comprises the steps of:
[0016] providing at least one metal oxide semiconductor field effect transistor comprising at least a gate conductor having a gate edge on a surface of a Sicontaining substrate;
[0017] forming an inner silicide contact that is aligned to said gate edge;
[0018] forming a wide spacer atop a portion of said inner silicide contact that is located close to said gate edge; and
[0019] forming an outer silicide contact on a portion of said inner silicide contact that is not protected by said wide spacer, wherein said outer silicide contact has a thickness that is greater than the inner silicide contact and said outer silicide contact has a resistivity that is lower than the resistivity of the inner silicide contact.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIGS. 1A-1D are pictorial representations (through cross sectional views) illustrating the basic processing steps employed in a first embodiment of the present invention.
