Method of operating a semiconductor memory device

1 2

the DRAM section DM, a cell selector gate voltage METHOD OF OPERATING A SEMICONDUCTOR Vsg is applied to the gate terminal 6 to turn on the MEMORY DEVICE transistor Tl, and the power source voltage Vcc or zero

bias is applied to the drain 1, as shown in the top row of BACKGROUND OF THE INVENTION 5 FIG. 6A. In response to the above, the potential of the

1. Field of the Invention: accumulation node 3 becomes Vcc or 0. That is, the This invention relates to a method of operating a data in the DRAM section DM becomes "1" or "0".

semiconductor memory device, and more particularly The source 2 of the transistor MT is zero biased,

to a method of operating a semiconductor memory (2) When data is written into the EEPROM section

device having a volatile memory means and a non- 10 EM, as shown in the middle row of FIG. 6A, first the

volatile memory means. gate terminal 6 and drain 1 of the transistor Tl are zero

2. Description of the Prior Knowledge: biased to disable the DRAM section DM, and the Semiconductor memory devices of the prior art in- source 2 of the transistor MT is zero biased while the

elude a mask ROM (Read-Only Memory), an EE- program voltage Vpp which is greater than the power

PROM (Electrically Erasable Programmable Read- 15 source voltage Vcc is applied to the other electrode

Only Memory) and other types of non-volatile memory (piate electrode) terminal 8 of the capacitor C. Then,

devices which can retain their storage contents even electrons accumulate in the floating gate 4 through the

when the power is off, and a DRAM (Dynamic Ran- tunnel oxide fllm ^ regardless 0f whether the data in

dom-Acces^Memory) and other volatile memory de- the DRAM section DM is "0" or "1", and the threshold

vices which lose their storage contents when the power 20 ^ Qf ^ ... T2 Wgh (erase state) as

IS°! ... . . , „_w , _„ shown in the column "step 1" of FIG. 5. At this time,

Non-volatile memory devices, * mask ROM and EE- ^ ch ^ accumulation node 3 of the capacitor

PROM are capable of retaining stored date for a long * £

period of time after the power is cut off. However, in . . / , . ^, _.w .'

{he case of a mask ROM.^ata cannot be rewritten after 25 *e data stored £ the DRAM section DM does not

it has been written in a wafer process. In the case of an chan8e wh«n the EEPROM section EM goes to the

EEPROM, data can be rewritten after it has been ar- crase state- However, the capacitance of the capacitor C

ranged in an apparatus, but the period for data write/e- must designed sufficiently large compared to the gate

rase is as long as 10 ms and there is a limit to the number capacitances C52 (capacitance between the control gate

of possible write/erase cycles, so these devices are not 30 5 and the source 2) and C5 (capacitance between the

suitable to applications in which data is repeatedly re- control gate 5 and the substrate) of the transistor MT.

written. In the case of RAM, however, which is volatile Then, as shown in the bottom row of FIG. 6A, the

memory, data rewrite time is less than 10 ns and there is potential of the source 2 of the transistor MT is made to

no limit to the number of times data can be rewritten, the program voltage Vpp while the plate electrode 8 of

but when the power source is cut off, all stored data is 35 the capacitor C is zero biased. The storage contents of

lost. the EEPROM section EM change corresponding to the

Recently, the inventor invented a multiple-use semi- data state "0" or "1" of the DRAM section DM. For

conductor memory device in which data can be rewrit- the sake of explanation, the coupling ratio Rc of the

ten rapidly, and stored data can be retained for a long transistor MT is defined by the following expression: period of time in the absence of power supply (U.S. Ser. 40 No. 549,293 filed Jul. 6, 1990).

FIG. 3 shows such an improved semiconductor mem- Rc = c + C4; + C4 ory device. The semiconductor memory device of FIG.

3 has a DRAM section DM comprising one MOS tran- . _ . .. , .

■ . . .. K »• „ where C45 is the capacitance between the floating gate

sistor Tl and one capacitor C, and an EEPROM section 45 . ... . , . , „ . „. . r

EM comprising a floating gate transistor MT. The * ^the control fte SJ C*15 th,e capacitance between

source 10 of the transistor Tl is connected to the accu- the floatm« 8ate 4 'he substrate and C42 is the

mulation node 3 of the capacitor C, and the drain 9 of capacitance between the floating gate 4 and the source

the transistor MT is connected to the accumulation 2 Thtn< *»» volta«e aPP1,ed t0 the tunnel 0Mde mTM *"

node 3 via a mode selector transistor T2 which func- 50 ls:

tions as a switch means. The control gate 5 of the tran- (a) when the DRAM data is "0", V0 (=Rc.Vpp); or

sistor MT is also connected to the accumulation node 3. 0>) when the DRAM data is "1",

The transistor T2 is switched on or off by applying a V](=Rc(Vpp-Vcc)).

positive bias voltage V7 or a zero bias on the gate termi- That is, when the DRAM data is "0", a voltage

nal (mode selector gate) 7. 55 which is higher by

FIG. 8 shows a cross sectional view of the device of

FIG. 3 which is formed on a semiconductor substrate V*=Vo-V\=RcVcc 20. As shown in FIG. 8, the source 2 and drain 9 of the

transistor MT are diffused areas which are formed than in the casc when the DRAM data is "1" is applied

below the floating gate 4. Between the source 2 and the 60 t0 the tunnel oxide film 4a.

floating gate 4, a tunnel oxide film 4a is disposed. The ^ the case of (a) (when the DRAM data is "0"), the

gate electrode 6 of the transistor Tl is connected to a electrons accumulated in the floating gate 4 are pulled

word line, and the drain 1 is connected to a bit line BL. toward the source 2 because the voltage applied to the

This semiconductor device operates as follows when tunnel oxide film 4a is high. As a result, even if the

the transistor T2 is off, i.e., when the mode selector gate 65 potential of the floating gate 4 becomes high and the

7 is zero biased. transistor MT turns to the on state, the electrons do not

(1) First, as shown in FIG. 4, the DRAM section DM flow to the drain 9 since the transistor T2 is in the off

is electrically isolated. When data is to be written into state. In this way, many electrons are pulled away and 3 4

the threshold value of the transistor MT becomes low In such a semiconductor memory device, however, it

(write state). has been found that, when the DRAM section DM is

In the case of (b) (when the DRAM data is "1"), operated for a long period of time while retaining the

electrons remain accumulated in the floating gate 4 data initially stored in the transistor MT (i.e., without

since the voltage applied to the tunnel oxide film 4a is 5 rewriting the storage contents of the transistor MT),

low. Therefore, the threshold value of the transistor charges move through the tunnel oxide film 4a due to

MT remains high (erase state). Fowler-Nordheim tunneling, to be gradually accumu

In this way, the storage contents of the EEPROM lated over a long span of time, resulting in that the

section EM can be set to a write state (low threshold storage contents initially stored in the transistor MT

value) or erase state (high threshold value) in accor- 10 nay be changed. In this way, the above-described

dance with "0" or "1" of the data contents of the method of operating the improved semiconductor

DRAM section DM, while the data contents of the memory device involves a problem in that the charac

DRAM section DM are retained. teristics of retaining storage contents (read retention) is

Next, the on state of the transistor T2, i.e., the state impaired,

wherein a positive bias V7 is applied to the mode selec- 15 SUMMARY OF THE INVENTION

tion gate 7 will be described. m ...... ...

(3) As shown in the top row of FIG. 6B, the DRAM Tte method of this invention, which overcomes the section DM operates in the same way as in the off state above-discussed and numerous other disadvantages and described above, by setting the source 2 of the transistor deficiencies of the prior art. In this method, a semiconMT to the open state and zero biasing the plate terminal 20 ductor ^J00** device composing a volatile memory 8 of the capacitor C means and a non-volatile memory means is operated,

(4) When data is to be written into the EEPROM vo!atile memory means ^Prising a MOS transissection EM, the drain 1 and cell selection gate terminal or'and a c£Pacltor means one electrode of said: capaci

. . j. tor means being connected to the source of said MOS

6 of the transistor Tl are zero biased to disable the ....... •. ,

T-vt>aw nit r. »u i. ... .25 transistor, said non-volatile memory means comprises a

DRAM section DM, as shown in the bottom row in • , • . . _ _

,n . _ .. ... r , c .. . . .. floating gate transistor, said semiconductor memory

FIGS. 6B and 7 a bias VTfor transfer is applied to the deviceBfl^her comprising a switch means connected source 2 of the transistor MT while the plate terminal 8 ^ ^ of ^ MQS ... and Qne

of the capacitor Cis zero biased. source/drain of said floating gate transistor, the control

As m the case where the transistor T2 is m the off 3Q q{ ^ floati transistor being connected to

state the storage contents of the EEPROM section EM ^ source of sajd MQS transistor. ^ method com. can be set to the write state or the erase state in accor- rises the of> when ^ swhch means is off and said dance with the DRAM data '0 or 1 . As shown m volati,e memory means are t0 ^ operated) applying a the equivalent circuit of FIG. 7, the dram 9 of the tran- voltage to the other source/drain of floating gate sistor MT is connected to the accumulation node 3 of 35 transistor) the levei 0f said voltage being substantially the capacitor C, so that the charge of the accumulation one half of that of a source voltage with respect node 3 is lost during the write operation through the t0 tjje gr0und level.

drain 9 of the transistor MT. That is, the DRAM data is xhus> the invention described herein makes possible not retained, and transferred to the EEPROM section t],e objectives of:

EM- 40 (i) providing a method of operating a semiconductor

In this way, the improved semiconductor memory memory device comprising a volatile memory means device operates as a DRAM capable of continually and a non-volatile memory means, which can operate rewriting data at high speed, and is able to transfer data the volatile memory means with a longer period of time from a DRAM section DM to an EEPROM section of retaining contents of the non-volatile memory means; EM, and also to rewrite EEPROM data while retaining 45 (2) providing a method of operating a semiconductor DRAM data. Furthermore, even when the power is off, memory device comprising a volatile memory means this device can store data as an EEPROM over a long and a non-volatile memory means, which can operate period of time, thus giving it a wide range of applicabil- the volatile memory means without lowering the retenIly- tion characteristic of the non-volatile memory means;

The improved semiconductor memory device in the 50 and state in which data is written in the DRAM section DM (3) providing a method of operating a semiconductor while the transistor T2 is off has the equivalent circuit memory device comprising a volatile memory means shown in FIG. 2. When data is to be written into the and a non-volatile memory means, in which the amount DRAM section DM, the voltage Vsg is applied to the of current leak is reduced, gate terminal 6 to turn on the transistor Tl. In this 55

condition, the power source voltage Vcc or zero bias is BRIEF DESCRIPTION OF THE DRAWINGS applied to the drain 1 through the transistor Tl, and the This invention may be better understood and its nusource 2 of the transistor MT is zero biased (the poten- merous objects and advantages will become apparent to tial is 0 V). During the operation of the DRAM section those skilled in the art by reference to the accompanyDM, therefore, the potential difference between the 60 ing drawings as follows:

control gate 5 and the source 2 of the transistor MT is FIG. 1 is a circuit diagram of an improved semiconthe power source voltage Vcc at the maximum. The ductor memory device illustrating an embodiment of storage contents of the transistor MT is rewritten by the the invention.

application of the program voltage Vpp which is FIG. 2 is a circuit diagram of the semiconductor greater than the power source voltage Vcc. Hence, the 65 memory device illustrating another operating method application of the power source voltage Vcc is not which was proposed by the inventor, directly led to the rewriting of the storage contents of FIG. 3 is a circuit diagram illustrating the semiconthe transistor MT. ductor memory device.