An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing...http://www.google.de/patents/US6784677?utm_source=gb-gplus-sharePatent US6784677 - Closed-grid bus architecture for wafer interconnect structure
Closed-grid bus architecture for wafer interconnect structure
