entire array of cells, or a significant group of cells, is FLASH EEPROM MEMORY SYSTEMS HAVING erased simultaneously (i.e., in a flash).
MULTISTATE STORAGE CELLS EEPROM's have been found to have a limited effec
tive life. The number of cycles of programming and CROSS-REFERENCE TO RELATED 5 erasing that such a device can endure before becoming
APPLICATION degraded is finite. After a number of such cycles in
This is a division of copending application Ser. No. excess of 10,000 depending upon its specific structure, 07/204,175, filed June 8, 1988. lts P^grammabihty can be reduced. Often, by the time
the device has been put through such a cycle for over BACKGROUND OF THE INVENTION 10 100,000 times, it can no longer be programmed or
This invention relates generally to semiconductor e'ased ... This * ^edjo be .the re*ult. °f
electrically programmable read only memories e!ectrons beinf trafPed ln *e dielectric each time
(EPROM) and electrically erasable programmable read ?harSe 1S transferred to or away from the floating gate
only memories (EEPROM), and specifically to tech- 15 by programming or erasing respectively.
. , \, r 13 It is a primary object of the present invention to pro
niques for using them. ., Aw »i. • J .
\ , . • , , , , vide an EEPROM array with increased storage capac
An electrically programmable read only memory . ^ ^ J e r
(EPROM) utilizes a floating (unconnected) conductive y„ it_ ' . ,. „ - it_
v . '. ., „ „ ^ .\ „ j Further, it is an object of the present invention to
gate, m a field effect transistor structure, positioned ., _' . . . r., ,
. , , r ■ , . . r provide techniques for increasing the number of proover but insulated from a channel region in a semicon- 20 / , .u * ccr,„nu _i
, , I j ■ ■ A gram/erase cycles that an EEPROM can endure,
ductor substrate, between source and drain regions. A D . ., ,. . .. t. . .,
, . , ... , „ . ° , Another object of the present invention is to provide
control gate is then provided over the floating gate, but . , . , . . ., *<•■<•.•
, . / , ... , , techniques for increasing the amount of information
also insulated therefrom. The threshold voltage charac- . \ ( ,. . cncAU rrDDm«
... 6 r that can be stored m a given size EPROM or EEPROM tenstic of the transistor is controlled by the amount of
charge that is retained on the floating gate. That is, the 25 arr» h ... Qf ^ t ... tQ
minimum amount of voltage (threshold) that must be jde EEPROM semiCOnductor chips that are useful
applied to the control gate before the transistor is for sqm statg m tQ ^ tic disk e
turned on to permit conduction between its source devices and drain regions is controlled by the level of charge on
the floating gate. A transistor is programmed to one of 30 SUMMARY OF THE INVENTION
two states by accelerating electrons from the substrate These and additional objects are accomplished by the
channel regIon, through a thin gate dielectric and onto various asp£Cts of the present invention> wherein,
the floating gate. briefly and generaliy> each EPROM or EEPROM
The memory cell transistor's state is read by placing memory cell is caused to store more than one bit of data
an operatmg voltage across its source and drain and on by partitioning its programmed charge into three or
its control gate, and then detecting the level of current more ranges £ach cdl is then pr0grammed into one of
flowing between the source and drain as to whether the these ranges If four ranges are used> two bits of data
device is programmed to be "on" or "off at the control can be stored in a single cell If eight ranges are desig.
gate voltage selected. A specific, single cell in a two-di- ^ nated; three bits can be stored) and so on.
mensional array of EPROM cells is addressed for read- An intelligent programming and sensing technique is
ing by application of a source-drain voltage to source provided which permits the practical implementation of
and drain lines in a column containing the cell being such multiple state storage. Further, an intelligent erase
addressed, and application of a control gate voltage to algorithm is provided which results in a significant
the control gates in a row containing the cell being 4J reduction in the electrical stress experienced by the
addressed. erase tunnel dielectric and results in much higher endur
One example of such a memory cell is a triple polysili- ance t0 program/erase cycling and a resulting increased
con, split channel electrically erasable and programma- jjfe 0f the memory.
ble read only memory EEPROM. It is termed a "split Additional objects, features and advantages of the
channel" device since the floating and control gates 50 present invention will be understood from the following
extend over adjacent portions of the channel. This re- description of its preferred embodiments, which de
sults in a transistor structure that operates as two tran- scription should be taken in conjunction with the ac
sistors in series, one having a varying threshold in re- companying drawings, sponse to the charge level on the floating gate, and
another that is unaffected by the floating gate charge 55 BRIEF DESCRIPTION OF THE DRAWINGS
but rather which operates in response to the voltage on FIG. 1 is a cross section of an example split channel
the control gate as in any normal field effect transistor. EPROM or EEPROM.
Such a memory cell is termed a "triple polysilicon" FIG. la is a cross-sectional view of a Flash EEcell because it contains three conductive layers of PROM cell. FIG. la is a schematic representation of the polysilicon materials. In addition to the floating and 60 composite transistor forming a split channel EPROM control gates, an erase gate is included. The erase gate device.
passes through each memory cell transistor closely FIG. 2b shows the programming and erase characteradjacent to a surface of the floating gate but insulated istics of a split channel Flash EEPROM device, therefrom by a thin tunnel dielectric. Charge is then FIG. 2c shows the four conduction states of a split removed from the floating gate of a cell to the erase 65 channel Flash EEPROM device in accordance with gate, when appropriate voltages are applied to all the this invention.
transistor elements. An array of EEPROM cells are FIG. 2d shows the program/erase cycling endurance
generally referred to as a Flash EEPROM array if an characteristics of prior art Flash EEPROM devices.