Flash EEPROM memory systems having multistate storage cells

FIG. 2e and 2f show a circuit schematic and programming/read voltage pulses required to implement multistate storage.

FIG. 3 outlines the key steps in the new algorithm used to erase with a minimum stress. 5

FIG. 4 shows the program/erase cycling endurance characteristics of the split channel Flash EEPROM device using intelligent algorithms for multistate programming and for reduced stress during erasing.

DESCRIPTION OF THE PREFERRED 10
EMBODIMENTS

Referring initially to FIG. 1, the structure of a splitchannel EPROM or EEPROM cell is described that is suitable for use in the improved memory array and 15 operation of the present invention. A semiconductor substrate 11 includes source region 13 and drain region 15, usually formed by ion implantation. Between the source and drain is a channel region 17. Over a portion of the channel region designated as LI is a floating gate 20 19, separated from the substrate by a thin layer of gate oxide 21. Over a portion of the channel region designated as L2 is formed a control gate 23, separated from the substrate 11 by a thin gate oxide layer 25. The control gate 23 is also electrically isolated from the floating 25 gate 19 by an oxide layer 27.

It is the amount of electrical charge on the floating gate 19 that is programmed in accordance with the state desired to be stored in the cell. If the charge level is above some set threshold, the cell is considered to be in 30 one state. If below that threshold, it is designated to be in its other state. The desired charge level is programmed by applying an appropriate combination of voltages to the source, drain, substrate and control gate, for a designated period of time, in order to cause elec- 35 trons to move from the substrate 11 to the floating gate 19.

The floating gate is confined to its one memory cell and is electrically isolated from all other parts of the structure. The control gate 23, on the other hand, ex- 40 tends across a large number of cells sharing a common word line. As described hereinafter, the split-channel has the effect of providing two field-effect-transistors in series, one with the floating gate 19 and the control gate 23 controlling conduction of its channel and the other 45 with the control gate 23 along controlling conduction of its channel.

The generic split-channel EPROM or EEPROM structure of FIG. 1 becomes a Flash EEPROM device when an erase gate 31 (FIG. la) is added. The erase gate 50 is a separate electrode positioned near a portion of the floating gate 27 and separated from it by a tunnel dielectric 33. When the proper voltages are applied to the source, drain, substrate, control gate and erase gate, the amount of charge on the floating gate is reduced. A 55 single erase gate extends to a large number of memory cells, if not the entire array, so that they may be erased all at once. In some prior art Flash EEPROM cells the source or drain diffusions underneath the floating gate are used also as the erase electrode, while in other cells 60 the erase electrode is implemented either in the same conductive layer as the control gate or in a separate conductive layer.

LI and having a variable threshold voltage Vn- Transistor T2 has a fixed (enhancement) threshold voltage Vn and an effective channel length L2. The EPROM programming characteristics of the composite transistor are shown in curve (a) of FIG. 2b. The programmed threshold voltage V,x is plotted as a function of the time t during which the programming conditions are applied. These programming conditions typically are Vcg= 12V, VD=9V, VS=VBB=QW, where V^is the substrate voltage. No programming can occur if either one of Vcc or Vd is at 0V. A virgin (unprogrammed, unerased) device has Vn = + 1-5V and Vn= + 1-0V. After programming for approximately 100 microseconds, the device reaches a threshold voltage V«g +6.0 volts. This represents the off ("0") state because the composite device does not conduct at Vcg=+ 5.0V. Prior art devices employ a so called "intelligent programming" algorithm whereby programming pulses are applied, each of typically 100 microseconds to 1 millisecond duration, followed by a sensing (read) operation. Pulses are applied until the device is sensed to be fully in the off state, and then one to three more programming pulses are applied to ensure solid programmability.

Prior art split channel Flash EEPROM devices erase with a single pulse of sufficient voltage VErase and sufficient duration to ensure that Vn is erased to a voltage below Vn (curve (b) in FIG. 2 b). Although the floating gate transistor may continue to erase into depletion mode operation (line (c) in FIG. 2b), the presence of the series T2 transistor obscures this depletion threshold voltage. Therefore the erased on ("1") state is represented by the threshold voltage V!x—Vn— + 1.0V. The memory storage "window" is given by A V = V«("0") - Vtt(" 1") = 6.0 - 1.0=5.0V. However, the true memory storage window should be represented by the full swing of Vtx for transistor Tl. For example, if Tl is erased into depletion threshold voltage Vn=-3.0V, then the true window should be given by—AV = 6.0-(-3.0) = 9.0V. None of the prior art EEPROM devices take advantage of the true memory window. In fact they ignore altogether the region of device operation (hatched region D in FIG. 2b) where Vn is more negative than V72.

This invention proposes for the first time a scheme to take advantage of the full memory window. This is done by using the wider memory window to store more than two binary states and therefore more than a single bit per cell. For example, it is possible to store 4, rather than 2 states per cell, with these states having the following threshold voltage:

State "3": Vn = -3.0V, Vn= + 1.0V (highest conduction)^, 1. •

State "2": Vn = -0.5V, Vn= + 1-0V (intermediate conduction) = 1, 0.

State "1": Vn = +2.0V, Vr2= + 1.0V (lower conduction) =0, 1.

State "0": Vn=+4.5V, Vn= + 1.0V (no conduction) =0, 0.

To sense any one of these four states, the control gate is raised to Vcg=+ 5.0V and the source-drain current Ids is sensed through the composite device. Since Vn= + 1.0V for all four threshold states transistor T2 behaves simply as a series resistor The conduction current Ids of the composite transistor for all 4 states is shown as a function of Vcg in FIG. 2c. A current sensing amplifier is capable of easily distinguishing between these four conduction states. The maximum number of 5

states which is realistically feasible is influenced by the noise sensitivity of the sense amplifier as well as by any charge loss which can be expected over time at elevated temperatures. Eight distinct conduction states are necessary for 3 bit storage per cell, and 16 distinct conduc- 5 tion states are required for 4 bit storage per cell.

Multistate memory cells have previously been proposed in conjunction with ROM (Read Only Memory) devices and DRAM (Dynamic Random Access Memory). In ROM, each storage transistor can have one of 10 several fixed conduction states by having different channel ion implant doses to establish more than two permanent threshold voltage states. Prior art multistate DRAM cells have also been proposed where each cell in the array is physically identical to all other cells. 15 However, the charge stored at the capacitor of each cell may be quantized, resulting in several distinct read signal levels. An example of such prior art multistate DRAM storage is described in IEEE Journal of SolidState Circuits, Feb. 1988, p. 27 in an article by M. 20 Horiguchi et al. entitled "An Experimental LargeCapacity Semiconductor File Memory Using 16Levels/Cell Storage". A second example of prior art multistate DRAM is provided in IEEE Custom Integrated Circuits Conference, May 1988, p. 4.4.1 in an 25 article entitled "An Experimental 2-Bit/Cell Storage DRAM for Macrocell or Memory-on-Logic Applications" by T. Furuyama et al.

To take full advantage of multistate storage in EPROM it is necessary that the programming algo- 30 rithm allow programming of the device into any one of several conduction states. First it is required that the device be erased to a voltage Vn more negative than the "3" state (—3.0V in this example). Then the device is programmed in a short programming pulse typically 35 one to ten microseconds in duration. Programming conditions are selected such that no single pulse can shift the device threshold by more than one half of the threshold voltage difference between two successive states. The device is then sensed by comparing its con- 40 duction current Ids with that of a reference current source Iref, i (i=0,1,2,3) corresponding to the desired conduction state (four distinct reference levels must be provided corresponding to the four states). Programming pulses are continued until the sensed current (solid 45 lines in FIG. 2c) drops slightly below the reference current corresponding to the desired one of four states (dashed lines in FIG. 2c). To better illustrate this point, assume that each programming pulse raises V!x linearly by 200 millivolts, and assume further that the device 50

6

ligent programming algorithms" of prior art devices In fact, with the new programming algorithm/ only carefully metered packets of electrons are injected during programming. A further benefit of this approach is that the sensing during reading is the same sensing as that during programming/sensing, and the same reference current sources are used in both programming and reading operations. That means that each and every memory cell in the array is read relative to the same reference level as used during program/sense. This provides excellent tracking even in very large memory arrays.

Large memory systems typically incorporate error detection and correction schemes which can tolerate a small number of hard failures i.e. bad Flash EEPROM cells. For this reason the programming/sensing cycling algorithm can be automatically halted after a certain maximum number of programming cycles has been applied even if the cell being programmed has not reached the desired threshold voltage state, indicating a faulty memory cell.

There are several ways to implement the multistate storage concept in conjunction n array of Flash EEPROM transistors. An example of one such circuit is shown in FIG. 2e. In this circuit an array of memory cells has decoded word lines and decoded bit lines connected to the control gates and drains respectively of rows and columns of cells. FIG. 2f shows voltages VpfVL and Vpbl during operation of the circuit of FIG 2e. Each bit line is normally precharged to a voltage of between 1.0 V and 2.0 V during the time between read, program or erase. For a four state storage, four sense amplifiers, each with its own distinct current reference levels IREF,0, IREF,1, IREF,2, and IREF,3 are attached to each decoded output of the bit line. During read, the current through the Flash EEPROM transistor is compared simultaneously (i.e., in parallel) with these four reference levels (this operation can also be performed in four consecutive read cycles using a single sense amplifier with a different reference applied at each cycle, if the attendant additional time required for reading is not a concern). The data output is provided from the four sense amplifiers through four Di buffers (DO, Dl, D2 and D3).

During programming, the four data inputs li (10, II, 12 and 13) are presented to a comparator circuit which also has presented to it the four sense amp outputs for the accessed cell. If Di match Ii, then the cell is in the correct state and no programming is required. If however all four Di do not match all four Ii, then the comparator output activates a programming control circuit. This circuit in turn controls the bit line (VPBL) and word line (VPWL) programming pulse generators. A single short programming pulse is applied to both the selected word line and the selected bit line. This is followed by a second read cycle to determine if a match between Di and Ii has been established. This sequence is repeated through multiple programming/reading pulses and is stopped only when a match is established (or earlier if no match has been established but after a preset maximum number of pulses has been reached).

The resulJ_of such multistate programming algorithm is that each cell is programmed into any one of the four conduction states in direct correlation with the reference conduction states Iref, i- In fact, the same sense amplifiers used during programming/reading pulsing are also used during sensing (i.e., during normal reading). This allows excellent tracking between the reference levels (dashed lines in FIG. 2c) and the pro