An EEPROM formed of three-layer polysilicon is provided. A floating gate is at a second level and a portion thereof is at a first level. A first control gate and a select gate are formed spaced against from each other at the first level and a portion of the second floating gate extends between them for...http://www.google.de/patents/US5049516?utm_source=gb-gplus-sharePatent US5049516 - Method of manufacturing semiconductor memory device
Method of manufacturing semiconductor memory device
