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METHOD OF MAKING AN LDC OR X-RAY IMAGING DEVICE WITH FIRST AND SECOND INSULATING LAYERS
BACKGROUND OF THE INVENTION
 Electronic matrix arrays find considerable application in X-ray imagers and active matrix liquid crystal displays (AMLCDs). Such AMLCDs and X-ray imagers generally include X and Y (or row and column) address lines which are horizontally and vertically spaced apart and cross at an angle to one another thereby forming a plurality of crossover points. Associated with each crossover point is an element (e.g. pixel) to be selectively addressed. These elements in many instances are liquid crystal display pixels or alternatively the memory cells of an electronically adjustable memory array or X-ray imaging array.
 Typically, a switching or isolation device such as a diode or thin film transistor (TFT) is associated with each array element or pixel. The isolation devices permit the individual pixels to be selectively addressed by the application of suitable potentials between respective pairs of the X and Y address lines. Thus, the TFTs act as switching elements for energizing or otherwise addressing corresponding pixel electrodes.
 Amorphous silicon (a-Si) TFTs have found wide usage for isolation devices in liquid crystal display (LCD) arrays and X-ray imagers. Structurally, TFTs generally include substantially co-planar source and drain electrodes, a thin film semiconductor material (e.g. a-Si) disposed between the source and drain electrodes, and a gate electrode in proximity to the semiconductor but electrically insulated therefrom by a gate insulator. In LCDs, current flow through a TFT between the source and drain is controlled by the application of voltage to the gate electrode. The voltage to the gate electrode produces an electric field which accumulates a charged region near the semiconductor-gate insulator interface. This charged region forms a current conducting channel in the semiconductor through which current is conducted. Thus, by controlling the voltage to the gate and drain electrodes, pixels may be switched on and off in a known manner.
 Herein, "drain" electrodes are those which are in communication with a drain address line and "source" electrodes are those that are in communication with the pixel electrodes through vias in the insulating layers.
 It is old and well-known to make TFT arrays wherein address lines and overlapping pixel electrodes are insulated from one another by an insulating layer. For example, see U.S. Pat. Nos. 5,641,974; 5,055,899; 5,182, 620; 5,414,547; 5,426,523; 5,446,562; 5,453,857; and 5,457,553, the disclosures of which are incorporated herein by reference.
 Unfortunately, when certain prior art pixel electrodes are arranged so as to overlap the address lines (e.g. U.S. Pat. No. 5,003,356), an undesirably high parasitic capacitance results in the overlap areas between the pixel electrodes and the address lines. In overlap areas, the pixel electrode forms a capacitor in combination with the overlapped address lines. The resulting parasitic capacitance
CPL between the pixel electrode and the address line in the area of overlap is defined as follows:
 where "e" is the dielectric constant of the insulating^ layer, "co" is a constant value of about 8.85x10 F/cm, "A" is the area of the resulting capacitor in the area of overlap, and "d" is the thickness of the insulating layer in the area of overlap.
 When a thin profile silicon nitride insulator is used as in U.S. Pat. No. 5,003,356, the resulting parasitic capacitance created by the overlap is undesirably high thereby resulting in capacitive crosstalk in the LCD. The dielectric constant of silicon nitride is well over 5.0 (typically from about 6.4 to 7.2). Such crosstalk results when the signal voltage intended to be on a particular pixel is not there. Thus, when CPL is too high, the voltage on the pixel is either higher or lower than intended depending upon how much voltage the other pixels on the signal address line receive. In other words, the pixel is no longer satisfactorily isolated when CPL is too high. In view of the above, there exists a need in the art for an LCD (and/or X-ray imager) having both an increased aperture ratio as well as reduced capacitive crosstalk in overlap areas so as to simultaneously and properly isolate each pixel and increase the pixel opening sizes.
 Further with respect to the '356 patent, for example, its disclosure does not appreciate the importance of the dielectric constant e of the insulating layer. While referencing numerous materials including silicon nitride and Si02, which may be used for the insulating layer, the '356 patent does not discuss either the dielectric constant values of these materials or their importance in helping reduce CPL in overlap areas. When e of the insulating layer is too high, capacitive crosstalk results.
 Recently, organic polymer films have been applied to TFT-LCDs as an insulating layer between address lines and pixel electrodes in high aperture applications. For example, see commonly owned U.S. Pat. No. 5,641,974. There has been increasing concern as to how such polymers affect back-channel-etch TFT performance and reliability. It has been found that both threshold voltage and sub-threshold swing can be degraded by acrylic or black resin insulating layers, as compared to silicon nitride, for example. In addition, a high off-current shoulder in sub-threshold regions has been found after negative gate voltage stress on acrylic passivated TFTs. The mechanism behind such degradation is believed to be that fixed charge and defect states are created at the interface between the organic insulating layer and the a-Si TFT layer.
 As the performance of LCDs and X-ray imagers is dependent upon TFT characteristics in both the off-state and sub-threshold regions, the below-referenced invention is an improvement over the disclosure of the commonly owned '974 patent in an effort to improve TFT characteristics and performance.
 It is apparent from the above that there exists a need in the art for an improved TFT array and/or resulting LCD (or X-ray imager) having an increased pixel aperture ratio, good TFT performance in all regions, and little capacitive crosstalk. Such an LCD or X-ray imager should be made with as few steps as possible.
 It is a purpose of this invention to fulfill the above-described needs in the art, as well as other needs which will become apparent to the skilled artisan from the following detailed description of this invention.
SUMMARY OF THE INVENTION
 Generally speaking, this invention fulfills the above-described needs in the art by providing an X-ray imager comprising:
 a substrate;
 an array of thin film transistors (TFTs) disposed on the substrate, the array of TFTs including a plurality of address lines connected to the TFTs;
 an array of substantially transparent electrodes disposed on the first substrate, a plurality of the electrodes in the array of electrodes overlapping at least one of the address lines;
 an organic photo-imageable insulating layer having a dielectric constant less than about 4.0 disposed on the substrate between the address lines and the electrodes at least in areas of overlap and areas adjacent source electrodes of the TFTs;
 an intermediate protective insulating layer disposed between the TFTs and the photo-imageable insulating layer so as to prevent the organic photoimageable insulating layer from directly contacting semiconductor material in channels of the TFTs thereby reducing potential shifts of threshold voltage and subthreshold swings in the TFTs; and
 the photo-imageable insulating layer and the intermediate protective layer each having a plurality of contact vias defined therein, wherein the electrodes are in electrical communication with corresponding TFT source electrodes through the contact vias defined in the insulating layers.
 In certain preferred embodiments, the organic photo-imageable insulating layer is a negative resist which includes BCB.
 In certain preferred embodiments, the organic photo-imageable insulating layer has a dielectric constant of less than about 3.0.
 In certain preferred embodiments, the organic photo-imageable insulating layer has a thickness of from about 0.9 fim to 2.75 fim, with the thickness in the areas of overlap, of course, being smaller than the above-recited thickness.
 In certain preferred embodiments, the intermediate insulating layer has a thickness of from about 100 A-1,000 A.
 This invention further fulfills the above-described needs in the art by providing a liquid crystal display comprising:
 a first substrate;
 a liquid crystal layer;
 an array of substantially transparent pixel electrodes on the first substrate for permitting image data to be displayed to a viewer;
 a plurality of gatelines and TFT gate electrodes on the first substrate;
 a semiconductor layer patterned so as to remain in an array of TFT areas;
 a source and drain electrode in each TFT area on the first substrate, a TFT channel being defined between a corresponding source and drain electrodes of each TFT, thereby forming an array of TFTs on the first substrate;
 drain lines connected to the drain electrodes;
 wherein a plurality of the pixel electrodes overlap at least one of a gateline and a drain line thereby increasing the pixel aperture ratio of the display;
 a substantially transparent photo-imageable insulating layer having a dielectric constant less than about 4.0, the photo-imageable insulating layer being disposed on the first substrate between (i) the pixel electrodes and (ii) the TFTs and the overlapped lines so as to insulate the pixel electrodes from the overlapped lines and the TFTs; and
 an intermediate insulating layer disposed between the photo-imageable insulating layer and the TFTs so as to prevent the photo-imageable insulating layer from directly contacting TFT portions which the photo-imageable insulating layer overlap.
 This invention further fulfills the above-described needs in the art by providing a TFT array structure comprising:
 an array of TFTs on a substrate, the TFTs being connected to a corresponding array of electrodes;
 row and column address lines on the substrate for addressing the TFTs;
 organic photo-imageable insulating means having a dielectric constant less than about 4.0 disposed between the electrodes and the address lines so as to reduce crosstalk and permit the insulating means to be photoimaged; and
 an intermediate protective insulating layer disposed between the photo-imageable insulating means and the TFTs so as to prevent the insulating means from contacting semiconductor material of the TFTs.
 This invention further fulfills the above-described needs in the art by providing a method of making a TFT structure, including first and second insulating layers over the TFTs.
 This invention still further fulfills the above-described needs in the art by providing a method of making an X-ray imager, the method including the steps of providing a substrate, forming an array of TFTs on the substrate, forming a first inorganic (e.g. silicon nitride) insulating layer over the TFTs, forming a second organic insulating layer over the
first layer so that the first insulating layer prevents the second insulating layer from directly contacting the semiconductor material of the TFTs, and forming an array of electrode members over the second insulating layer with each of the electrode members in communication with one of the TFTs through a contact hole defined in the first and second insulating layers.
 This invention further fulfills the above-described needs in the art by providing a method of making a liquid crystal display, the method comprising the steps of providing a substrate, forming an array of TFTs or other switching elements on the substrate, forming first and second insulating layers over the TFTs or other switching elements, forming contact holes in the first and second insulating layers proximate TFTs, and forming a plurality of pixel electrodes over the second insulating layer so that each of the pixel electrodes is in communication with one of the TFTs through a corresponding one of the contact holes.
 This invention will now be described with reference to certain embodiments thereof as illustrated in the following drawings.
IN THE DRAWINGS
 FIG. 1 is a top view of an AMLCD according to this invention, this figure illustrating pixel electrodes overlapping surrounding row and column address lines along their respective lengths throughout the display's pixel area so as to increase the pixel aperture ratio of the display.
 FIG. 2 is a top view of the column (or drain) address lines and corresponding drain electrodes of FIG. 1 (or of an X-ray imager), this figure also illustrating the TFT source electrodes disposed adjacent the drain electrodes so as to define the TFT channels having length "L."
 FIG. 3 is a top view of the pixel electrodes of FIG. 1 (or of an X-ray imager) except for their extensions.
 FIG. 4 is a side elevational cross-sectional view of the linear-shaped thin film transistors (TFTs) of FIGS. 1-2, this structure being utilized in either an LCD or an X-ray imager according to this invention.
 FIGS. 5-7 are side elevational cross-sectional views illustrating how a TFT in an array according to this invention is manufactured.
DETAILED DESCRIPTION OF CERTAIN
EMBODIMENTS OF THIS INVENTION
 Referring now more particularly to the accompanying drawings in which like reference numerals indicate like parts throughout the several views.
 The structure and function of AMLCDs are disclosed in U.S. Pat. No. 5,641,974, and the structure and function of X-ray imagers are disclosed in U.S. Pat. Nos. 5,525,527; 5,498,880; 5,396,072; and 5,619,033, the disclosure of which are incorporated herein by reference. Familiarity with such structures and functions is assumed herein.
 FIG. 1 is a top view of four pixels in an array of an active matrix liquid crystal display (AMLCD) 2 according to an embodiment of this invention. This portion of the display includes substantially transparent pixel electrodes 3, drain address lines 5, gate address lines 7, an array of four
thin film transistors (TFTs) 9, and auxiliary storage capacitors 11 associated with each pixel. Each storage capacitor 11 is defined on one side by a gate line 7 and on the other side by an independent storage capacitor electrode 12. Storage capacitor electrodes 12 are formed along with drain electrodes 13. As shown, the longitudinally extending edges of each pixel electrode 3 overlap drain lines 5 and gate lines 7 respectively along the edges thereof so as to increase the pixel aperture ratio (or pixel opening size) of the LCD.
 In the areas of overlap 18 between substantially transparent pixel electrodes 3 and address or bus lines 5, 7, a pixel-line (PL) capacitor is defined by an electrode 3 on one side and the overlapped address line on the other. The dielectric disposed between the electrodes of these PL capacitors is insulation layer 33 (see FIGS. 4 and 7). The parasitic capacitance CPL of these capacitors is defined by the equation:
 where "d" is the thickness of layer 33, e is the dielectric constant of layer 33, e0 is the constant 8.85xl0~14 F/cm (permitivity in vacuum), and "A" is the area of the PL capacitor in overlap areas 8. The fringing capacitance may also be taken into consideration in a known manner. According to certain other embodiments, CPL is less than or equal to about 0.01 pF for a display with a pixel pitch of about 150 fim. When the pixel pitch is smaller, CPL should be scaled to a lower value as well because overlap areas 18 are smaller. Additionally, the pixel aperture ratio of an LCD decreases as the pixel pitch decreases as is known in the art. The pixel pitch of AMLCD 2 may be from about 40 to 5,000 pan according to certain embodiments of this invention. The pixel pitch as known in the art is the distance between centers of adjacent pixels in the array.
 According to alternative embodiments of FIG. 1, the TFTs may be swung 90° so that the gates are formed by perpendicular extensions from the gate lines and the drains are formed by the drain lines themselves. This may be used in both LCD and X-ray imager embodiments of this invention.
 FIG. 2 is a top view of drain address lines 5 of AMLCD 2 (or of an X-ray imager) showing how extensions of address lines 5 may form drain electrodes 13 of TFTs 9 in the FIG. 1 illustrated embodiment. Each TFT 9 in the array includes source electrode 15, 31. drain electrode 13, 29, and gate electrode 17. Gate electrode 17 of each TFT 9 is formed by the corresponding gate address line 7 in the FIG. 1 illustrated embodiment. According to other embodiments discussed above, the gate electrode 17 may be formed by a branch extending substantially perpendicular to the gate line, while drain electrodes 13 are formed by the drain lines 5 themselves.
 FIG. 3 is a top view illustrating pixel electrodes 3 (absent their extension portions 38) of AMLCD 2 or an X-ray imager arranged in array form.
 FIG. 4 is a side elevational cross-sectional view of a single thin film transistor (TFT) 9 in the TFT array of either an X-ray imager or AMLCD 2, with each TFT 9 in the array