Method and apparatus for modulating the perceptible intensity of a light ...

U.S. Patent Apr. 10, 1979 Sheet 5 of 5 4,149,111 Modulating the perceptible intensity of light can be 40 light emitting display. The apparatus proposed by this

invention employs the inherent information retention of the display information over relatively long periods of time of the light emitting display and the persistence of vision of the human eye to modulate the perceived light 45 intensity. For example, the maximum intensity of the light emitting display identified above is achieved for a light sustaining signal having a nominal frequency of about 50 KHZ for which two light pulses are emitted for every cycle of the light emitting display so that light

filter or by an electrically controlled colloidal light 50 pulses are generated at a rate of about 100 KHz. Simple 3 4

from a minimum light intensity achieved with a repeti- FIG. 3 is a graphical representation showing the

tion rate or interruption frequency of about 10 Hz with relationships between the clock pulse train, the repeti

a duty cycle, or the length of time of the interruption, tion pulse train, the gating signal, the retention signal,

that allows a single cycle of the light sustaining signal or the system clock signal, a representative light sustaining

two light pulses, to substantially maximum intensity (the 5 signal, and the light pulses.

maximum intensity being derived from an uninterrupted FIG. 4 (comprised of a and b) is a schematic represen

50 KHz light sustaining signal) achieved with a repeti- tation showing an apparatus used to modulate the per

tion signal of at least 40 Hz having a duty cycle that ceptible intensity of the presentation of a light emitting

interrupts the light emitting display for a single cycle of display.

the light sustaining signal or two light pulses. 10 nFSPRTPTTON OF THF PRFFFRRFO The correlation between that frequency of a light 1JHSCR1F1 ION OF mtl^EhERRED source and the amount of light received by the eye EMBODIMENT which causes a perceptible flicker is presented in the As discussed above, FIG. 1 is a rough graphical repgraphical representation, Critical Frequency of Flicker resentation of the relationship between the repetition by John W. T. Walsh in his book "Photometry," 1958, 15 frequency and the duty cycle whereby Representation I Third Edition, Dover at page 70. This correlation indicates the minimum perameters for the undesirable shows a generally linear relationship between the fre- perceptible flicker. Combinations of frequency and duty quency of the light source and the logarithm of the cycle above Representation I would not create a perquantity of received light. FIG. 1 of the drawings, pres- ceptible flicker while combinations below would. The ents a rough relationship, Representation I, between the 20 maximum range of light intensities is achieved by dyrepetition frequency along the vertical axis and the duty namically varying the repetition frequency and duty cycle (a simplified approximation of the amount of cycle in the manner indicated by Representation I. light) along the horizontal axis. While there is no pre- FIG. 2 shows a functional block diagram of an appacise algorithm relating the John W. T. Walsh graphical ratus used to modulate the perceptible intensity of the representation to FIG. 1, FIG. 1 does show the general 25 presentation of a light emitting display. The modulation relationship between repetition frequency, duty cycle, apparatus is shown generally at 10 and the light emitting and flicker perception. A flicker in the light emitting display is shown at 110. The modulation apparatus 10 display is perceived for combinations of repetition fre- includes a clock pulse train generator 20 (clock means) quency and duty cycle which fall below Representation which generates a clock pulse train signal; a repetition I. 30 pulse train generator 50 (the repetition means) which Optimum results can be achieved by reducing the generates a repetition pulse train signal, having an adduty cycle from 100% to a minumum level that permits justable frequency and duty cycle; a synchronizer 40 a single cycle of the light sustaining signal to be trans- (the synchronization means) which generates a gating mitted, then by reducing the repetition rate from 40 H* signal, the logically true or active state of which is in to approximately 10 Hz. Alternatively, it is possible to 35 synchronization with the logically true or active state of reduce both the repetition rate and the duty cycle in the the repetition pulse train signal and the logically false or manner indicated by Representation I of FIG. 1. These inactive state of which is in synchronization with the adjustments provide the maximum range of intensity of logically false or inactive state of the repetition pulse the light emitting display. The ability to independently train signal and the active state of a retention signal; adjust both the repetition rate and the duty cycle pro- 40 stopping generator 30 (stopping means) which genervides a substantially wider range of light intensities ates a control system clock signal by interrupting the without flicker, particularly for the lower intensities. In clock pulse train signal in synchronization with the practice, the apparatus of this invention interrupts the gating signal; and indication generator 60 (indication light emitting display in synchronization with the repe- means) which generates the retention signal by decodtition signal having an adjustable duty cycle and a reten- 45 ing the system clock signal to provide an active retention signal; the retention signal indicating the retention tion pulse at the point in time that the light emitting state of the light emitting display. display is capable of retaining display information upon It is an object of this invention to provide an appara- the interruption of either the light sustaining signal or tus for adjustably modulating the perceptible intensity the electrical power. The indication generator 60 also of the presentation of a light emitting display over a 50 provides clock phase control to the light emitting diswide range of light intensities. A further object of this play 110.

invention is to provide an apparatus for interrupting the The clock pulse train signal which is generated by the

system clock of a light emitting display. A further ob- clock pulse generator 20 is fed over line 21 to the stop

ject of this invention is to provide an apparatus enabling ping generator 30 and over line 22 to the synchronizer

the light sustaining signal or electrical power of a light 55 40. The repetition pulse train signal which is generated

emitting display to be interrupted while providing maxi- by the repetition pulse train generator 50 if fed over line

mum retention of the display information. 51 to the synchronizer 40. The gating signal which is

Urtff nFSPRTPTTON OF THF DR AWTNOS provided by the synchronizer 40 is fed over line 41 to

BRIEF DESCRIPTION OF THE DRAWINGS the stopping ge„erator 30 which then generates the

The following is a brief description of the accompa- 60 control system clock signal that is fed over line 31 to the

nying drawings. indication generator 60 and over line 32 to the light

FIG. 1 is a graphical representation showing the emitting display 110. The indication generator 60 prominimum flicker conditions as a function of the flicker vides the retention signal which is fed over line 62 to the frequency and duty cycle of the repetition signal. synchronizer 40, and the phase control signals which

FIG. 2 is a block diagram showing the functional 65 are fed over line 64 to the light emitting display 110.

embodiment of an apparatus that modulates the percep- The clock pulse train generator 20 is a conventional

tible intensity of a presentation of a light emitting dis- frequency generator such as a voltage controlled fre

play. quency oscillator a back-to-back monostable multivi5 6

brator or a conventional RC timing circuit. The clock FIG. 3 is an example of a timing diagram of the modpulse train generator 20 produces a clock pulse train ulation apparatus showing the relationships between its signal which has a characteristic frequency of about, for various electronic signals. In referring to FIG. 3, Repreexample, 3.2 MHZ which is 64 times the characteristic sentation A shows the continuous clock pulse train frequency of the light sustaining signal. In a similar 5 signal generated by the free running sustaining clock manner, the repetition pulse train generator 50 gener- pulse train generator 20 at a representative 3.2 MHz. ates an adjustable repetition pulse train signal having a Representation B shows the repetition pulse train signal characteristic frequency of about 0 to 100 Hz. The repe- generated by the repetition pulse train generator 50 at a tition pulse train generator 50 also includes a duty cycle representative 40 Hz. Representation C shows the regenerator (see FIG. 4) which adjustably controls the 10 tention signal developed by the indication generator 60 length of the logically true or active state of the repeti- indicating the point in time within a major light sustaintion pulse train signal; that is the ratio of time the repeti- ing signal cycle that the light emitting display 110 is tion pulse train signal is true or active relative to the capable of retaining display information. The retention time of a complete cycle of the repetition pulse train pulse typically is true for one full minor cycle of the signal. 15 characteristic 3.2 MHz system clock signal for every

The repetition pulse train signal is connected by line major cycle of the light sustaining cycle.

51, and the clock pulse train signal is connected by line The specific minor cycle, of the 64 cycles of the 3.2

22, and a retention signal is connected by line 62 to the MHz system clock signal which constitutes a major

synchronizer 40. The gating signal is generated by the cycle of a light sustaining signal, is determined empiri

synchronizer 40 such that the gating signal goes active 20 cally and is decoded by the indication generator 60 to

or logically true in synchronization with the positive identify the time of maximum data retention capability

transition of the repetition pulse train signal. The gating of the light emitting display.

signal is set active or logically true until both the reten- Representation D shows the gating signal produced

tion signal is logically true or active and the repetition 2J by the display synchronizer 40. Representation I shows

pulse train signal is logically false or inactive whereby the gating signal going true or active at the first positive

the gating signal is reset inactive or logically false. Both transition of the clock pulse train signal after the repeti

the positive and negative transitions of the gating signal tion pulse train signal has gone true or active. Represen

may be triggered by the clock pulse train signal for tation II shows the gating signal going false or inactive

internal timing purposes. 30 at the positive transition of the clock pulse train signal

The gating signal is connected over line 41 and the after the repetition pulse train signal has gone false or

clock pulse train signal is connected over line 21 to the inactive and the retention signal has gone true or active,

stopping generator 30. The stopping generator 30 effec- Representation E shows the control system clock

tively interrupts the clock pulse train signal in synchro- signal as generated by the stopping generator 30. Repre

nization with the gating signal by logically disabling the 35 sentation F is a representative indication of the timing

clock pulse train signal during periods when the gating for the light sustaining signal which is used by the light

signal is logically false or inactive and enables the clock emitting display 110. The light sustaining signal has a

pulse train signal when the gating signal is logically true characteristic frequency of 50 KHz. Representation G

or active thus generating the control system clock sig- indicates the light pulses generated by the light emitting

nal. The control system clock signal is fed over line 32 40 display as a result of the light sustaining signal,

to the light emitting display 110 where it is used by the FIG. 4 shows a schematical representation of a spe

light emitting display 110 in lieu of its internal system cific embodiment for an electrical circuit 10 which

clock. The control clock signal also connects over line produces a control system clock signal used to modu

31 to the indication generator 60. late the perceptible intensity of the presentation of a

The indication generator 60 includes circuitry to 45 light emitting display. With reference to FIG. 4(a) the generate the retention signal, such as a conventional clock pulse train generator shown generally at 20 infrequency divider circuit and a counter decoding cir- eludes three invertors U14-C, U16-D, and U16-E, concuit. The frequency divider circuit divides the charac- nected to form a ring having a conventional RC timing teristic frequency of the control system clock signal by circuit connected across U16-E such that a square wave a specific ratio to generate a frequency representative of 50 clock pulse train signal having a characteristic frethe light sustaining signal, which has a characteristic quency of 3.2 MHz is generated at the output of U16-D. frequency of about 50 KHz and other intermediate The output of U16-D is coupled to a final inverting frequencies, such as 100 KHz, 200 KHz 400 KHz, and element U3-D. Inverting elements U14-C and U3-D 800 KHz. All frequencies are provided over line 64 to may be conventional NAND gates (such as SN7400N the light emitting display 110 to maintain clock phase 55 available from Texas Instruments) connected as logical control therewith. The counter decoding circuitry logi- signal invertors and elements U16-D and U-16E may be cally compares a numerical value set in a bank of conventional Schmitt triggors (such as SN7414N availswitches which represents the cycle count of the system able from Texas Instruments).

clock signal in which the light emitting display is capa- The repetition pulse train generator 50 includes a ble of retaining display information, with the changing 60 rep-rate clock circuit 54, a duty cycle circuit 55, a Turnstate of the various intermediate frequencies provided Off circuit 56 and a system override circuit 57. Rep-rate by the frequency divider circuit and generates an active clock circuit 54 includes a pulse generator U13 (such as retention pulse when a comparision is made. The nu- SN555 available from Texas Instruments) with resistors, merical value used to indicate the display's capability to capacitors and diodes connected to provide a rep-rate retain display information and the active retention pulse 65 pulse train having positive pulse of about 10 microcorrespondes to a point in time after the gas discharge seconds at a frequency of about 50 Hz. The frequency of the display medium and before the next transition, of the rep-rate circuit 54 is adjustable between about 0 either positive or negitive, of the light sustaining signal. and 100 Hz by adjusting variable resistor R3. The out