1 INCREASING READOUT SPEED IN CMOS APS SENSORS THROUGH BLOCK READOUT
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a continuation of application Ser. No. 10/983,083, filed Nov. 8, 2004, now U.S. Pat. No. 7,671,914, Which is a continuation of application Ser. No. 09/274,739, filed Mar. 23, 1999 (now U.S. Pat. No. 6,847,399), Which claims the benefit of U.S. Provisional Application No. 60/079,046, filed on Mar. 23, 1998. Each ofthese disclosures are incorporated herein by reference.
The present invention relates to CMOS image sensors, and more particularly to methods and associated architectures for reading out data, from such a sensor.
The advent of HDTV and other high-end digital imaging systems is increasing demand for large format high speed sensors. CMOS active pixel image sensors Which have loW poWer dissipation, are loW cost and highly reliable, and Which can typically be configured in a single chip solution, are increasingly being developed for large format high speed imaging applications. Large format sensors usually require an image pixel array of at least 1024x1024 pixels in size. Unfortunately, as the image array is made larger, it becomes diflicult to increase pixel readout rate Without also increasing frame rate because of parasitic capacitance limitations in current architectures.
The present disclosure describes a method and associated architecture for dividing column readout circuitry in an image sensor in a manner Which reduces the parasitic capacitance on the readout line. In a preferred implementation, column readout circuits are grouped in blocks and provided With block signaling. Accordingly, only column readout circuits in a selected block significantly impart a parasitic capacitance effect on shared column readout lines at any point in time. Block signaling Was found to increase pixel readout rate While maintaining a constant frame rate for utility in large format high-speed imaging applications.
In accordance With a preferred embodiment, by mathematically modeling the load capacitance and the effective RC constant seen by any column output stage at a particular time and by using a differentiated derived equation, a desirable optimum number of connections per block as Well as a desired number of blocks for a given size of column readout circuits can be easily determined.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shoWs a pixel and corresponding column readout circuit in an active pixel sensor.
FIG. 2 shoWs the timing for a photodiode pixel readout operation.
FIG. 3 shoWs a block diagram of a CMOS active pixel sensor including an array of pixels and corresponding column readout circuits, all coupled to a pair of shared readout lines.
FIG. 4 shoWs a simplified schematic diagram of a portion of an output stage for each of plural column readout circuits and the parasitic capacitance effects contributed thereby.
FIG. 5 shoWs a tree-style column decoder and multiplexer.
FIG. 6 shoWs the grouping of column readout circuits in blocks of k across an m-pixel linear array.
FIG. 7 shoWs the timing for column readout and column group selection in accordance With a preferred implementation of the present disclosure.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
A schematic diagram of a conventional CMOS active pixel 100 and associated column readout circuit 101 is shoWn in FIG. 1. Incident photons on the pixel 101 generate electrons that are collected in the floating diffusion area 102. The charge is buffered by an in-pixel source follover 105. A number of pixels are typically arranged horizontally to form a roW of pixels and also vertically to define a column of pixels. RoW selection transistor 103 is enabled to alloW charge from a given roW of pixels to be selectable for readout.
A more detailed discussion of the general principles of pixel readout is provided in U.S. Pat. No. 5,841,126.
While the illustrative implementation shoWs a photodiode pixel, it should be understood that a photogate, phototransistor or the like could be used instead.
During imaging, the photodiode floating diffusion area 1 02 is first reset. This is achieved by pulsing a gate of reset transistor 104 to a high voltage, for example VDD. After a period of time, the voltage of the floating diffusion area 102 drops to reflect the number of electrons accumulated in the Floating diffusion area 102. The voltage VS of the floating diffusion area is then read out from the pixel 100 into the column readout circuit 101 using source folloWer 105 Within pixel 100. Voltage V5 is then sampled onto storage capacitor CS 106 by enabling the sample-hold signal (SHS) transistor 107.
After the signal charge VS is read out, the pixel 100 is then reset and the gate of reset transistor 104 is again pulsed to a high voltage. The resultant voltage VR of Floating diffusion area 102 is then read out to the column readout circuit 101 as before. This time the voltage VR is sampled onto storage capacitor CR 108 by enabling the sample-hold reset (SHR) transistor 109. FIG. 2 shoWs the timing for the above photodiode operation.
The voltage difference betWeen the voltages stored in the tWo capacitors, C S 106 and C R 108 is indicative of the charge collected in the floating diffusion area 102. Typically, all the pixels 100 in a same roW are processed simultaneously. The signals are sampled onto capacitors C S and C R in their respective column readout circuits collectively arranged beneath the roW (or multiple roWs: array 10) of pixels. After a roW sampling process is complete, voltage signal Vout_S, Vout_R in each column is read out successively by successively enabling the associated n-channel column selection transistors 110, 111. A high level block diagram ofan array ofpixels 10 and associated linear array 10' of corresponding column readout circuits 101, arranged in parallel fashion, is shoWn in FIG. 3. The outputs of Vout_R and Vout_S of column readout circuits 101 each share a common readout line.
FIG. 4 is a simplified partial schematic diagram of the respective output stages of the column readout circuits 101 in a linear array of pixels 10'. Each column output stage contributes a parasitic capacitance resulting in an effective load capacitance of Cp, represented by capacitor 401. Assuming Ci to be the parasitic capacitance contributed by each column
