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* cited by examiner
1
SEMICONDUCTORS BONDED ON GLASS
SUBSTRATES
CROSS-REFERENCE TO RELATED
APPLICATIONS 5
This application is a divisional of U.S. application Ser. No. 10/443,340, filed May 21,2003, now U.S. Pat. No. 7,273,788, which is herein incorporated by reference in its entirety.
This application is related to the following commonly 10 assigned U.S. patent application, U.S. application Ser. No. 10/443,355, entitled: "Silicon Oxycarbide Substrates for Bonded Silicon on Insulator," filed May 21,2003, now issued as U.S. Pat. No. 7,008,854, which is herein incorporated by reference in its entirety. 15
TECHNICAL FIELD
This application relates generally to electronic devices and device fabrication and, in particular, semiconductor on insu- 20 lator devices and their fabrication.
BACKGROUND
Almost half the energy expended by a silicon microchip 25 during its manufacture and lifetime is spent in producing the silicon wafer material, and another quarter is spent during the operating lifetime of the microchip. A technique that reduces the energy associated with fabrication of the silicon material and power consumption during operation will reduce the 30 overall cost of the silicon microchip integrated circuit.
Power consumption during operation can be reduced using silicon on insulator (SOI) technology. The use of SOI technology not only results in a lower power consumption but also increased speed of operation of integrated circuits due to a 35 reduction in stray capacitance. For SOI structures, thin layers of silicon on insulator can be fabricated using several well known techniques such as separation by implantation of oxygen (SIMOX), separation by plasma implantation of oxygen (SPIMOX), silicon on sapphire (SOS), bonded wafer pro- 40 cesses on silicon, and silicon bonded on sapphire.
Bonded wafer processes on silicon involve technologies to bond monocrystalline silicon materials onto semiconductor wafers and oxidation processes to form the semiconductor on insulator. In these technologies, a portion of one or both of the 45 bonded wafers is removed, typically, by polishing methods. Another process to remove large portions of a bonded wafer uses a "Smart cut" technology. "Smart cut" technology generally refers to a process in which a material is implanted into a silicon substrate to a particular depth and ultimately utilized 50 to crack the substrate.
There continues to be a need to provide fabrication processes and structures to reduce the overall cost for a silicon microchip integrated circuit.
55
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates an embodiment of a semiconductor on insulator, according to the present invention.
FIG. 2 illustrates a relationship between silicon layer thick- 60 ness and strain.
FIG. 3 depicts an embodiment of an electronic device using a semiconductor on insulator structure, according to the present invention.
FIG. 4 is a simplified block diagram of a memory device 65 using an embodiment of a semiconductor on insulator structure, according to the present invention.
2
FIG. 5 illustrates a block diagram for an electronic system having devices that use an embodiment of a semiconductor on insulator structure, according to the present invention.
FIG. 6 illustrates the relationship of elements in an embodiment for a method to form a semiconductor on insulator structure, according to the present invention.
DETAILED DESCRIPTION
The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.
The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form an integrated circuit (IC) structure. The term substrate is understood to include semiconductor wafers. Both wafer and substrate can include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art.
The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
FIG. 1 illustrates an embodiment of a semiconductor on insulator structure 100. Semiconductor on insulator structure 100 includes a glass substrate 105, and an ultra-thin semiconductor layer 110 bonded to the glass substrate 105. Semiconductor on insulator structure 100 is configured with semiconductor layer 110 having a thickness such that semiconductor layer 110 does not yield due to temperature-induced strain at device processing temperatures. Temperature-induced strain includes strain that is produced in a material combined with another material as a result of mismatches in the coefficients of thermal expansion of the two materials.
In an embodiment, an insulator layer 112 is disposed between semiconductor layer 110 and glass substrate 105. Insulator layer 112 can be an oxide of a semiconductor material contained in semiconductor layer 110. In an embodiment, semiconductor layer 110 includes a silicon layer. In an embodiment where semiconductor layer 110 includes a silicon layer having insulator layer 112, insulator layer 112 is a silicon oxide, which can include a native silicon oxide. However, insulator layer 112 is not limited to an oxide and can include other insulator materials. Insulator layer 112 can provide further reduction of stray capacitances and/or be used in processing device circuitry in the semiconductor on insulator structure. Additionally, semiconductor layer 110 can include and is not limited to a semiconductor layer containing germanium, gallium arsenide, a silicon-germanium compound, and other semiconductor materials as are known to those skilled in the art.
In an embodiment, glass substrate 105 can be a fused quartz substrate or a fused silica substrate. Alternately, glass substrate 105 includes a borosilicate glass substrate. An embodiment includes a thin silicon layer 110 on a glass substrate 105, where the glass substrate 105 can include a fused
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