APPARATUS AND METHOD FOR
SHADOWING PROCESSOR INFORMATION
BACKGROUND OF THE INVENTION 5
1. Field of the Invention
The invention relates generally to debugging processors, and more specifically, to shadowing processor information for debugging purposes. 10
2. Related Art
System-on-chip devices (SOCs) are well-known. These devices generally include a processor, one or more modules, bus interfaces, memory devices, and one or more system busses for communicating information. Because multiple :5 modules and their communications occur internally to the chip, access to this information is generally difficult when problems occur in software or hardware. Thus, debugging on these systems is not straightforward. As a result of development of these SOCs, specialized debugging systems 20 have been developed to monitor performance and trace information on the chip. Such systems typically include dedicated hardware or software such as a debug tool and debug software which accesses a processor through serial communications. 25
However, debugging an SOC generally involves intrusively monitoring one or more processor registers or memory locations. Accesses to memory locations are sometimes destructive, and a data access to a location being read
from a debugging tool may impede processor performance. Similarly, accesses are generally performed over a system bus to the processor, memory, or other module, and may reduce available bandwidth over the system bus for performing general operations. Some debugging systems do not perform at the same clock speed as that of the processor, and 35 it may be necessary to slow the performance of the processor to enable use of debugging features such as obtaining trace information. By slowing or pausing the processor, some types of errors may not be reproduced, and thus cannot be detected or corrected. Further, accurate information may not 40 be available altogether due to a high speed of the processor; information may be skewed or missing.
Some systems include one or more dedicated functional units within the SOC that are dedicated to debugging the 4J processor, sometimes referred to as a debug unit or module. However, these units affect the operation of the processor when obtaining information such as trace information. These devices typically function at a lower speed than the processor, and thus affect processor operations when they 5Q access processor data. The debug system relies upon running debug code on the target processor itself, and this code is usually built into the debugee. Thus, the presence of the debug code is intrusive in terms of memory layout, and instruction stream disruption. 55
Other debugging systems referred to as in-circuit emulators (ICEs) match on-chip hardware and are connected to it. Thus, on-chip connections are mapped onto the emulator and are accessible on the emulator. However, emulators are prohibitively expensive for some applications, and do not 60 successfully match all on-chip speeds or communications. Thus, emulator systems are inadequate. Further, these systems generally transfer information over the system bus, and therefore necessarily impact processor performance.
Another technique for troubleshooting includes using a 65 Logic State Analyzer (LSA) which is a device connected to pins of the integrated circuit that monitors the state of all
off-chip communications. LSA devices are generally expensive devices, and do not allow access to pin information inside the chip. In sum, there are many systems which are inadequate for monitoring the internal states of a processor and for providing features such as real-time state and real-time trace in a non-intrusive manner.
SUMMARY OF THE INVENTION
These and other drawbacks of conventional debug systems are overcome by providing a dedicated link which operatively couples a processor and a debug circuit which transfers information between them to support debugging operations. In one aspect, the processor provides information that a debug trace tool would need to be performed non-intrusively, that is, without disturbing memory accesses or the execution pipeline of the processor. Also, in one aspect, information is transmitted from the processor at a rate that matches the processor internal clock speed.
In one aspect, the processor communicates over this link to a debug circuit. Further, this link coupling the processor and the debug circuit is utilized in a manner which minimizes a number of physical lines required to communicate the information. Further, information needed to perform trace operations is transferred in a non-intrusive manner over the link. In one aspect, the processor and debug circuit may be located on a single integrated circuit.
According to another aspect, the processor provides program counter information to the debug circuit. In another aspect, program counter information is stored in a register of the debug unit. The register may be memory-mapped such that systems on-chip and/or external systems may access program counter information without affecting processor performance. By shadowing program counter information in debug circuit and because the debug circuit is capable of serving information independently of the processor, processor performance is unaffected when program counter information is accessed by other systems. By providing program counter information, the debug circuit is capable of creating trace messages for debugging purposes.
According to one aspect of the invention, a signal indicating the program counter has incremented is sent program counter signals to the debug circuit to allow the circuit to track the program counter in the processor. Thus, transmission of the entire program counter is not necessary and the number of communication lines between the processor and debug circuit is minimized.
In yet another aspect, the system provides watchpoint circuits for determining one or more states of the processor and locates signals related to triggering the processor. The processor may be configured to transfer values of the processor states to the debug circuit over the dedicated link. In one aspect of the invention, the internal states of the processor are mapped to registers in the debug circuit whereas conventional systems generally need intrusive software to determine state of processor.
According to one aspect of the invention, the location of watchpoints are balanced between being located in processor and debug circuit; the interface is configured to minimize the number of lines to access the information. In one aspect, watchpoint circuits that relate to triggering in the processor are located in the processor. For example, watchpoint circuitry related to operand addresses, instruction values, and instruction addresses are located in the processor.
In another aspect of the invention, the processor provides process identification information to debug circuit which then can base/optimize filtering based on process identifier