A PC bus architecture that is compatible with an industry standard bus architecture and allows devices to transfer data at higher data rates that the bus clock speed. By transferring data more than once per clock cycle, the data transfer rate is multiplied. Another feature of the present invention...http://www.google.de/patents/US5689660?utm_source=gb-gplus-sharePatent US5689660 - Enhanced peripheral component interconnect bus protocol
Enhanced peripheral component interconnect bus protocol
