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Zheng et al.
Vashchenko et al.
Yamada
Maayan et al.
Avni et al.
Eshel

Quader et al.

Miyatake et al 257/296

Kuono

Petti etal 365/230.06

Shappir et al.

Takashima 365/145

Banks
Norman
Muranaka et al.
Eitan

Johnson etal 257/314

Eliyahu et al.
Keshavarzi et al.
Shor et al.

Kobayashi et al 365/200

Maayan et al.
Subramoney et al.
Lai

Yachareni et al.
Bloom et al.
Sofer et al.
Yamashita
Buhr

Roizin et al.
Maayan et al.
Dvir et al.
Cohen et al.
Verma et al.

Ooishi 365/185.21

Ramsbey et al.

Tsukikawa et al 365/149

Shinozaki et al.

Yamada

Takahashi

Van Buskirk et al.

Takahashi et al.

Iijima

Hashimoto et al.
Le et al.
Fukuda et al.
Miki et al.
Chou et al.
Kurihara
Torii

Wilier et al.
Yang et al.
Zheng et al.
Takahashi et al.
Shor et al.
Polansky et al.
Hwang
Avni et al.
Maayan et al.
Anderson et al.
Do et al.
Anderson et al.
Atir et al.
Lusky et al.
Maayan et al.
Shappir et al.
Lusky et al.

Ichigeetal 365/185.28

Sekiguchi et al 365/207 Page 6

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WO WO 03/100790 12/2003

OTHER PUBLICATIONS

U.S. Appl. No. 11/489,327, filed Jul. 18, 2006, Eitan et al. Bude et al., EEPROM/Flash Sub 3.0V drain—Source Bias Hot Carrier Writing, IEDM, 1995, pp. 989-992.

Bude et al., Secondary Electron Flash—a High Performance, Low Power Flash Lechnology for 0.35 um and below, IEDM, 1997, 279282.

Bude et al., Modeling Nonequilibrium Hot Carrier Device Effects, Conference of Insulator Specialists of Europe, Jun. 1997, Sweden. Jung et al., IEEE Journal of Solid-State Circuits, Nov. 1996, 15751583, vol. 31, No. 11.

Campardo et al., IEEE Journal of Solid-State Circuits, Nov. 2000, 1655-1667, vol.35, No. 11.

Lin et al., Novel Source-Controlled Self-Verified Programming for Multilevel EEPROM's, IEEE Transactions on Electron Devices, Jun. 2000, 1166-1174, vol. 47, No. 6.

Chan et al., A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device, IEEE Electron Device Letters, Mar. 1987, vol. EDL-8, No. 3. Eitan et al., "Hot-Electron Injection into the Oxide in n-Channel MOS Devices", IEEE Transactions on Electron Devices, vol. ED-28, No. 3, pp. 328-370, Mar. 1981.

Roy Anirban, "Characterization and Modeling of Charge Trapping and Retention in Novel Multi-Dielectric Nonvolatile Semiconductor Memory Devices", Microelectronics Laboratory, Sherman Fairchild Center, Department of Computer Science and Electrical Engineering, Bethlehem, Pennsylvania, p. 1-35, 1989.

Tanaka et al., "A Quick Intelligent Page-Programming Architecture and a Shielded Bitline Sensing Method for 3 V-Only NAND Flash Memory", IEEE Journal of Solid-State Circuits, vol. 29, No. 11, Nov. 1994, pp. 1366-1373.

Ma et al., A Dual-bit Split-Gate EEPROM (DSG) Cell in Contactless Array for Single-Vcc High Density Flash Memories, IEEE, 1994, 57-60.

Oshima et al., Process and Device Technologies for 16Mbit EPROMs with Large-Tilt-Angle Implanted P-Pocket Cell, IEEE, Dec. 1990, Ch. 2865-4/90/0000-0095, pp. 521-524, San Francisco, California. Lee, A new approach for the floating-gate MOS nonvolatile memory, Applied Physics Letters, Oct. 1977, 475-476, vol. 31, No. 7, American Institute of Physics.

Glasser et al., MOS Device Electronics, The Design and Analysis of VLSI Circuits, Chapter 2, 67-163,1998, Addison-Wesley Publishing Company.

Bhattacharyya et al., FET Gate Structure for Nonvolatile N-Channel Read-Mostly Memory Device, IBM Technical Disclosure Bulletin, Nov. 1975, 1768, vol. 18, No. 6.

Ricco et al., Nonvolatile Multilevel Memories for Digital Applications, Dec. 1998, 2399-2421, vol. 86, No. 12, Institute of Electrical and Electronics Engineers, Inc.

Martin, Improved Circuits for the Realization of Switched-Capacitor Filters, IEEE Transactions on Circuits and Systems, Apr. 1980, 237244, vol. CAS-27.

Tseng et al., "Thin CVD Stacked Gate Dielectric for ULSI Technology", IEEE, pp. 321-214; 1993, 13.1.1-13.1.4. Pickar, Ion Implementation is Silicon—Physics, Processing, and Microelectronic Devices, Applied Solid State Science, 1975, 151241, vol. 5, Academic Press.

2 Bit/Cell EEPROM Cell Using Band-To-Band Tunneling for Data Read-Out, IBM Technical Disclosure Bulletin, 1992, 136-140, vol. 35 No. 4B.

Umezawa, et al., A 5-V-Only Operation 0.6um Flash EEPROM with Row Decoder Scheme in Triple-Well Structure, IEEE Journal of Solid-State Circuits, 1992, 1540, vol. 27.

Mitchell, et al., A new self-aligned planar array cell for ultra high density EPROMS, 1987.

Esquivel, et al, High Density Contactless, Self Aligned EPROM Cell Array Technology, 1986.

Johns, Martin, Analog Integrated Circuit Designl, Jun. 1,1997, Chapter 10, John Wiley and Sons Inc.

Allen, et al., CMOS Analog Circuit Design, 2002, 259pages, Oxford University Press.

Page 7

Klinke, et al., A very-high-slew-rate CMOS operational amplifier,
IEEE Journal of Solid-State Circuits, 1989, 744-746, 24 vol.
Shor, et al, paper WA2.04.01—Self regulated Four phased charge
pump with boosted wells, ISCAS 2002.

Fotouhi, An efficient CMOS line driver for 1.544-Mb/s T1 and 2.048Mb/s El applications, IEEE Journal of Solid-State Circuits, 2003, 226-236pages, 38vol.

P-N Junction Diode, Physics of semiconductor devices, 1981, ch. 2,
"A Wiley-Interscience Publication", John Wiley & Sons Publishers.
Chang, Non Volatile Semiconductor Memory Devices, Proceedings
of the IEEE, 64 vol., No. 7, pp. 1039-1059; Jul. 1976.
Yoon, Sukyoon, et al., A Novel Substrate Hot Electron and Hole
Injection Structure with a double-implanted buried-channel
MOSFET, IEEE Transactions on Electron Devices, Dec. 1991, p.
2722, vol. 38, No. 12.

4 Bits of Digital Data Fit in a Single Cell, Technology Newsletter, Electronic Design, Apr. 1, 1996.

M. Specht et al, Novel Dual Bit Tri- Gate Charge Trapping Memory Devices, IEEE Electron Device Letters, vol. 25, No. 12, Dec. 2004, pp. 810-812.

"Design Considerations in Scaled SONOS Nonvolatile Memory Devices" Bu, Jiankang et al. , Lehigh University, Bethlehem, PA, Power Point Presentation, pp. 1-24, 2000; http://klabs.org/ richcontent/MemoryContent/nvmt_symp/nvmts_2000/presentations/bu white sonos lehigh_univ.pdf.

"SONOS Nonvolatile Semiconductor Memories for Space and Military Applications", Adams et al., Symposium, 2000. http://klabs.org/ richcontent/MemoryContent/nvmt_symp/nvmts_2000/papers/ adams_d.pdf.

"Philips Research—Technologies—Embedded Nonvolatile Memories" http://research.philips.com/technologies/ics/nvmemories/index.html.

"Semiconductor Memory: Non-Volatile Memory (NVM)", National University of Singapore, Department of Electrical and Computer Engineering: http://ece.nus.edu.sg/stfpage/elezhucx/myweb/NVM. pdf.

"Salfun Non-Volatile Memory Technology", 1 st Edition, 2005, published and written by Saifun Semiconductors Ltd. 1110 pgs.

* cited by examiner

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