Dietmar Gogl et al: "A 1-Kbit EEPROM in SIMOX Technology for High-Temperature Applications up to 250° C," IEEE Journal of Solid-State Circuits, Oct. 2000, vol. 35, No.
10, IEEE.
"3D Chip-On-Chip Stacking", Semiconductor International, Dec. 1991.
Lay, Richard, "TRW Develops Wireless Multiboard Interconnect System", Electronic Engineering Times, Nov. 5, 1994.
Wada Y. et al, "Active-Body-Bias SOI-CMOS Driver Circuits", Jun. 1997 Symposium on VLSI Circuits Digest of Technical Papers, pp. 29-30.
Abou-Samra S.J.: "3D CMOS SOI for High Performance Computing", Low Power Electronics and Design Proceedings, 1998.
Yamazaki K.: "4—Layer 3-D IC Technologies for Parallel Signal Processing", International Electron Devices Meeting Technical Digest, Dec. 9-12, 1990, pp. 25.51-25.5.4. Schlaeppi H.P: "nd Core Memories using Multiple Coincidence", IRE Transactions on Electronic Computers, Jun. 1960, pp. 192-196.
Schlaeppppi H.P: "Session V: Information Storage Techniques", International Solid-State Circuits Conference, Feb.
11, 1960, pp. 54-55.
De Graaf C. et al.: "A Novel High-Density, Low-Cost Diode Programmable Read Only Memory," IEDM, beginning at p. 189.
Peter K. Naji et al: "A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM," 2001 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, ISSCC 2001/Session 7/Technology Directions: Advanced Technologies/7.6, Feb. 6, 2001, pp. 122-123 (including enlargement of figures, totaling 9 pages), and associated Visual Supplement, pp. 94-95,4040-405 (enlargements of slides submitted, totaling 25 pages).
Kim C. Hardee et al.: "A Fault-Tolerant 30 ns/375 mW 16Kxl NMOS Static RAM," IEEE Journal of Solid-State Circuits, Oct. 1981, vol. SC-16, No. 5, pp. 435^143. Toshio Wada et al; "A 15-ns 1024-Bit Fully Static MOS RAM," IEEE Journal of Solid-State Circuits, Oct. 1978, vol. SC-13, No. 5, pp. 635-639.
Camperi-Ginestet C: "Vertical Electrical Interconnection of Compound Semiconductor Thin-Film Devices to Underlying Silicon Circuitry", IEEE Photonics Technology Letters, vol. 4, No. 9, Sep. 1992, pp. 1003-1006. Akasaka Yoichi: Three-dimensional Integrated Circuit: Technology and Application Prospect, Microelectronics Journal, vol. 20, No.s 1-2, 1989, pp. 105-112. Sakamoto Koji: "Architecture des Circuits a Trois Dimension (Architecture of Three Dimensional Devices)", Bulletin of the Electrotechnical Laboratory, ISSN 0366-9092, vol. 51, No. 1, 1987, pp. 16-29.
Akasaka Yoichi: "Three-dimensional IC Trends", Proceedings of the IEEE, vol. 74, No. 12, 1986, pp. 1703-1714. Carter William H.: "National Science Foundation (NSF) Forum on Optical Science and Engineering", Proceedings SPIE—The International Society for Optical Engineering, vol. 2524, Jul. 11-12 1995, (Article by N. Joverst titled "Manufacturable Multi-Materilas Integraton Compound Semi-conductor Devices Bonded to Silicon Circuity". Hayashi, Y: "A New Three Dimensional IC Fabrication Technology, Stacking Thin Film Dual-CMOS Layers", IEDM, 1991, pp. 25.6.2-25.6.4.
Reber M.: "Benefits of Vertically Stacked Integrated Circuits for Sequential Logic", IEEE, 1996, pp. 121-124. Stern Jon M.: Design and Evaluation of an Epoxy Three-dimensional Multichip Module, IEEE Transactions on Components, Packaging, and Manufacturing Technology—Part B, vol. 19, No. 1, Feb. 1996, pp. 188-194. Bertin Claude L.: "Evaluation of a Three-dimensional Memory Cube System", IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 16, No. 8, Dec. 1993, pp. 1006-1011.
Watanabe Hidehiro: "Stacked Capacitor Cells for High-den- sity Dynamic RAMs", IEDM, 1988, pp. 600-603. Web Page: "Stacked Memory Modules", IBM Technical Disclosure Bulletin, vol. 38, No. 5, 1995. Thakur Shashidhar: "An Optimal Layer Assignment Algo- rithm for Minimizing Crosstalk for Three VHV Channel Routing", IEDM, 1995, pp. 207-210. Terril Rob: "3D Packaging Technology Overview and Mass Memory Applications", IEDM, 1996, pp. 347-355. Inoue Y: "A Three-Dimensional Static RAM", IEEE Elec- tron Device Letters, vol. 7, No. 5, May 1986, pp. 327-329. Reber M.: "Benefits of Vertically Stacked Integrated Cir- cuits for Sequential Logic", IEDM, 1996, pp. 121-124. Kurokawa Takakazu: "3-D VLSI Technology in Japan and an Example: A Syndrome Decoder for Double Error Corec- tion", FGCS—Future, Generation, Computer, Systems, vol. 4, No. 2, 1988, pp. 145-155, Amsterdam, The Netherlands. Makiniak David: "Vertical Ingegration of Silicon Allows Packaging of Extremely Dense System Memory In Tiny Volumes: Memory-chip Stacks Send Density Skyward", Electronic Design, No. 17, Aug. 22, 1994, pp. 69-75, Cleveland Ohio.
Yamazaki K.: "Fabrication Technologies for Dual 4-KBIT Stacked SRAM", IEDM 16.8., 1986, pp. 435-438. Pein Howard: "Performance of the 3-D PENCIL Flash EPROM Cell an Memory Array", IEEE Transactions on Electron Devices, vol. 42, No. 11, Nov. 1995, pp. 1982-1991.
Abstract Lomatch S.: "Multilayered Josephson Junction Logic and Memory Devices", Proceedings of the SPIE-The International Society for Optical Engineering vol. 2157, pp. 332-343.
Abstract Lu N.C.C.: "Advanced Cell Structures for Dynamic RAMs", IEEE Circuits and Devices Magazine, vol. 5, No. 1, Jan. 1989, pp. 27-36.
Abstract Sakamato K.: "Architecture of Three Dimensional Devices", Journal: Bulletin of the Electrotechnical Laboratory, vol. 51, No. 1, 1987, pp. 16-29. Abstract "Wide Application of Low-Cost Associative Processing Associative Processing Seen", Electronic Engineering Times, Aug. 26, 1996, p. 43.
Abstract "Interconnects & Packaging", Electronic Engineering Times, Nov. 27, 1995, p. 43.
Abstract "Closing in on Gigabit DRAMs", Electronic Engi- neering Times, Nov. 27, 1995, p. 35. Abstract "Module Pact Pairs Cubic Memory with Vision- Tek", Semiconductor Industry & Business Survey, vol. 17, No. 15, Oct. 23, 1995.
Abstract "Layers of BST Materials Push Toward 1Gbit DRAM", Electronics Times, Oct. 19, 1995. Abstract "Technologies Will Pursue Higher DRAM Densi- ties", Electronic News (1991), Dec. 4, 1994, p. 12. Abstract "Looking Diverse Storage", Electronic Engineer- ing Times, Oct. 31, 1994, p. 44.
Abstract "Special Report: Memory Market Startups Cubic Memory: 3D Space Savers", Semiconductor Industry & Business Survey, vol. 16, No. 13, Sep. 12, 1994. Abstract "Technique Boosts 3D Memory Density", Electronic Engineering Times, Aug. 29, 1994, p. 16. Abstract "Memory Packs Poised 3D Use", Electronic Engineering Times, Dec. 7, 1992, p. 82.
Astract "MCMs Hit the Road", Electronic Engineering Times, Jun. 15, 1992, p. 45.
Abstract "IEDM Ponders the 'Gigachip' Era", Electronic Engineering Times, Jan. 20, 1992, p. 33.
Abstract "Tech Watch: 1-Gbit DRAM in Sight", Electronic World News, Dec. 16, 1991, p. 20.
Abstract "MCMs Meld into Systems", Electronic Engineering Times, Jul. 22, 1991, p. 35.
Abstract "Systems EEs See Future in 3D", Electronic Engineering Times, Sep. 24, 1990, p. 37. Chan et al. "Three Dimensional CMOS integrated Circuits on Large Grain Polysilicon Films" IEEE, Hong Kong University of Science and Technology 2000 IEEE.
* cited by examiner
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