Double density NROM with nitride strips (DDNS)

OTHER PUBLICATIONS

U.S. Appl. No. 08/902,890, filed Jul. 30, 1997, Eitan.
U.S. Appl. No. 11/489,327, filed Jul. 18, 2006, Eitan et al.
U.S. Appl. No. 11/440,624, filed May 24, 2006, Lusky et al.
U.S. Appl. No. 11/489,747, filed Jul. 18, 2006, Bloom et al.
U.S. Appl. No. 11/336,093, filed Jan. 20, 2006, Eitan et al.
Bude et al., EEPROM/Flash Sub 3.0V drain—Source Bias Hot Car-
rier Writing, IEDM, 1995, pp. 989-992.

Bude et al., Secondary Electron Flash—a High Performance, Low Power Flash Technology for 0.35 um and below, IEDM, 1997, 279282.

Bude et al., Modeling Nonequilibrium Hot Carrier Device Effects, Conference of Insulator Specialists of Europe, Jun. 1997, Sweden. Jung et al., IEEE Journal of Solid-State Circuits, Nov. 1996, 15751583, vol. 31, No. 11.

Campardo et al., IEEE Journal of Solid-State Circuits, Nov. 2000, 1655-1667, vol.35, No. 11.

Lin et al., Novel Source-Controlled Self-Verified Programming for Multilevel EEPROM's, IEEE Transactions on Electron Devices, Jun. 2000, 1166-1174, vol. 47, No. 6.

Chan et al., A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device, IEEE Electron Device Letters, Mar. 1987, vol. EDL-8, No. 3. Eitan et al., "Hot-Electron Injection into the Oxide in n-Channel MOS Devices", IEEE Transactions on Electron Devices, vol. ED-28, No. 3, pp. 328-370, Mar. 1981.

Roy Anirban, "Characterization and Modeling of Charge Trapping and Retention in Novel Multi-Dielectric Nonvolatile Semiconductor Memory Devices", Microelectronics Laboratory, Sherman Fairchild Center, Department of Computer Science and Electrical Engineering, Bethlehem, Pennsylvania, p. 1-35, 1989.

Tanaka et al., "A Quick Intelligent Page-Programming Architecture and a Shielded Bitline Sensing Method for 3 V-Only NAND Flash Memory", IEEE Journal of Solid-State Circuits, vol. 29, No. 11, Nov. 1994, pp. 1366-1373.

Ma et al., A Dual-bit Split-Gate EEPROM (DSG) Cell in Contactless Array for Single-Vcc High Density Flash Memories, IEEE, 1994, 57-60.

Oshima et al., Process and Device Technologies for 16Mbit EPROMs with Large-Tilt-Angle Implanted P-Pocket Cell, IEEE, Dec. 1990, Ch. 2865-4/90/0000-0095, pp. 5 2 1-5 2 4, San Francisco, California. Lee, A new approach for the floating-gate MOS nonvolatile memory, Applied Physics Letters, Oct. 1977, 475-476, vol. 31, No. 7, AmeriGlasser et al., MOS Device Electronics, The Design and Analysis of VLSI Circuits, Chapter 2,67-163,1998, Addison-Wesley Publishing Company.

Bhattacharyya et al., FET Gate Structure for Nonvolatile N-Channel Read-Mostly Memory Device, IBM Technical Disclosure Bulletin, Nov. 1975, 1768, vol. 18, No. 6.

Ricco et al., Nonvolatile Multilevel Memories for Digital Applications, Dec. 1998, 2399-2421, vol. 86, No. 12, Institute of Electrical and Electronics Engineers, Inc.

Martin, Improved Circuits for the Realization of Switched-Capacitor Filters, IEEE Transactions on Circuits and Systems, Apr. 1980, 237244, vol. CAS-27.

Tseng et al., "Thin CVD Stacked Gate Dielectric for ULSI Technology", IEEE, pp. 321-214; 1993, 13.1.1-13.1.4. Pickar, Ion Implantation in Silicon—Physics, Processing, and Microelectronic Devices, Applied Solid State Science, 1975, 151-241, vol. 5, Academic Press.

2 Bit/Cell EEPROM Cell Using Band-To-Band Tunneling for Data Read-Out, IBM Technical Disclosure Bulletin, 1992, 136-140, vol. 35 No. 4B.

Umezawa, et al., A 5-V-Only Operation 0.6-um Flash EEPROM with Row Decoder Scheme in Triple-Well Structure, IEEE Journal of Solid-State Circuits, 1992, 1540, vol. 27.

Mitchell, et al., A new self-aligned planar array cell for ultra high density EPROMS, 1987.

Esquivel, etal., High Density Contactless, Self Aligned EPROM Cell Array Technology, 1986.

Johns, Martin, Analog Integrated Circuit Design, Jun. 1,1997, Chapter 10, John Wiley and Sons Inc.

Allen, et al., CMOS Analog Circuit Design, 2002, 259pages, Oxford
University Press.

Klinke, et al., A very-high-slew-rate CMOS operational amplifier,
IEEE Journal of Solid-State Circuits, 1989, 744-746, 24 vol.
Shor, et al, paper WA2.04.01—Self regulated Four phased charge
pump with boosted wells, ISCAS 2002.

Fotouhi, An efficient CMOS line driver for 1.544-Mb/s T1 and 2.048Mb/s El applications, IEEE Journal of Solid-State Circuits, 2003, 226-236pages, 38vol.

P-N Junction Diode, Physics of semiconductor devices, 1981, ch. 2, "A Wiley-Interscience Publication", John Wiley & Sons Publishers. Chang, Non Volatile Semiconductor Memory Devices, Proceedings of the IEEE, 64 vol., No. 7 , pp. 1039-1059; Jul. 1976.

Yoon, Sukyoon, et al., A Novel Substrate Hot Electron and Hole Injection Structure with a double-implanted buried-channel MOSFET, IEEE Transactions on Electron Devices, Dec. 1991, p. 2722, vol. 38, No. 12.

4 Bits of Digital Data Fit in a Single Cell, Technology Newsletter, Electronic Design, Apr. 1, 1996.

M. Specht et al, Novel Dual Bit Tri- Gate Charge Trapping Memory Devices, IEEE Electron Device Letters, vol. 25, No. 12, Dec. 2004, pp. 810-812.

"Design Considerations in Scaled SONOS Nonvolatile Memory Devices" Bu, Jiankang et al. , Lehigh University, Bethlehem, PA, Power Point Presentation, pp. 1-24, 2000; http://klabs.org/ richcontent/MemoryContent/nvmt_symp/nvmts_2000/presentations/bu_white_sonos_lehigh_univ.pdf.

"SONOS Nonvolatile Semiconductor Memories for Space and Military Applications", Adams et al., Symposium, 2000. http://klabs.org/ richcontent/MemoryContent/nvmt symp/nvmts 2000/papers/ adams_d.pdf.

"Philips Research—Technologies—Embedded Nonvolatile Memories" http://research.philips.com/technologies/ics/nvmemories/index.html.

"Semiconductor Memory: Non-Volatile Memory (NVM)", National University of Singapore, Department of Electrical and Computer Engineering: http://ece.nus.edu.sg/stfpage/elezhucx/myweb/NVM. pdf.

"Saifun Non-Volatile Memory Technology", 1 st Edition, 2005, published and written by Saifun Semiconductors Ltd. 1110 pgs. European Search Report 06100524.5, May 16, 2006. European Search Report 06100507.0, Mar. 28, 2007. European Search Report 04791843.8, Feb. 13, 2007. Lee et al., Scalable 2-bit silicon-oxide-nitride-oxide-silicon (SONOS) memory with physically separated local nitrides under a merged gate, Solid State Electronics 48 (2004), pp. 1771-1775. Mahapatra et al. , CHISEL Flash EEPROM—Part I: Performance and Scaling; IEEE Transactions on Electron Devices, vol. 49. No. 7, Jul. 2002.

Mohapatra et al., CHISEL Programming Operation of Scaled NOR Flash EEPROMs—Effect of Voltage Scaling, Device Scaling and Technological Parameters IEEE Transactions on Electron Devices, vol. 50. No. 10, Oct. 2003.

* cited by examiner