CA1063205A - Direct input photoelectric pulse initiator for meter telemetry and recording systems - Google Patents
Direct input photoelectric pulse initiator for meter telemetry and recording systemsInfo
- Publication number
- CA1063205A CA1063205A CA236,442A CA236442A CA1063205A CA 1063205 A CA1063205 A CA 1063205A CA 236442 A CA236442 A CA 236442A CA 1063205 A CA1063205 A CA 1063205A
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- Prior art keywords
- circuit
- pulse
- outputs
- flip
- output
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R11/00—Electromechanical arrangements for measuring time integral of electric power or current, e.g. of consumption
- G01R11/36—Induction meters, e.g. Ferraris meters
Abstract
ABSTRACT OF THE DISCLOSURE
A completely solid state photoelectric pulse ini-tiator for electric utility meter telemetry and recording systems includes a low power CMOS digital integrated circuit (I.C.) flip-flop output circuit for directly generating output pulses in response to the rate of rotation of a meter movement.
A pulse rate dividing circuit is provided by a presettable divide-by-N CMOS digital I.C. in one preferred form for elec-tronically varying the ratio of the output pulses relative to the input pulses. A simplified data magnetic recording re-ceiver circuit is capable of being supplied recorder drive current directly from the Q and ? logic outputs of the output flip-flop to produce non-return-to-zero (NRZ) data pulse recording.
A completely solid state photoelectric pulse ini-tiator for electric utility meter telemetry and recording systems includes a low power CMOS digital integrated circuit (I.C.) flip-flop output circuit for directly generating output pulses in response to the rate of rotation of a meter movement.
A pulse rate dividing circuit is provided by a presettable divide-by-N CMOS digital I.C. in one preferred form for elec-tronically varying the ratio of the output pulses relative to the input pulses. A simplified data magnetic recording re-ceiver circuit is capable of being supplied recorder drive current directly from the Q and ? logic outputs of the output flip-flop to produce non-return-to-zero (NRZ) data pulse recording.
Description
BACKGROUND OF THE INVENTION
The invention relates to photoelectric pulse ini-tiators for pulse operated meter telemetry and recording sys-tems and more particularly to such pulse initiators including a low power digital I.C. arrangement for simplifying and con-trolling the transmitted pulses generated by the pulse ini-tiator and to afford a simplified recording apparatus receiving the transmitted pulses.
In U.S. Patent No. 5,733,493 issued May 15, 1973 to T. M. McClelland III and in U.S. Patent No. 3,878,391 issued April 15, 1975 to T. M. McClelland III et al, both assigned to the assignee of this invention, radiation or photoelectric pulse initiators are disclosed for use in the ,.~
. 45,336 electric power meterlng fleld for lnitlatlng meter data pulses in response to the rate of rotation of a utlllty meter Or the watthour type. In these prlor systems varlou~ technlques are descrlbed for generatlng pulses in respanse to the meter ro-tatlon with an output pulse generator rormed by a latchlng type three-wlre contact device such as a mercury wetted relay.
Large current values are sometlmes requlred to adequately operate the relay ln e~tremely cold enviranments and~are typlcally inefrlclent~ Slnce the rela~ effectlvely lsolates the pulse lnltlator output and a data recelving recarding.clr-cult, 3eparate power supply sources are required to supply both the pulse lnltlator clrcuits and the data recordlng circuits. Mechanical control for varying.the pulse rate.in response to the speed Or the meter shart movement., referred to as the constant Mp in the above-identifled appllcatlon, i8 not always satlsractory for all appllcatio~s. Gear train ratios used ln drivlng-a patterned dlsk or drum ln.the pulse lnltiator mechanlsm or the number of refle~ctlve ~egments form-` lng the indlcla of the pulse lnltlator pattern o~ten requlre substant~al lnterchanglng or:parts and have llmitatlons due to undeslred loadlng a~ the meter shart and space avallable wlthin the meter houslngO RatlQs of less than one.pulse per meter shart rotatlon are often only posslble by.changlng a.gear train ratlo whlle high output.pulse numbers per.sha~t rotatlon a~e often only obtalnable by increaslng the number Or rerlectlve segments ln the shaft drlven pattern.
In the data.magnetlc recordlng ~ystems u~ed ln u~ility meter recordlng.telemetry sDstems lt.has..been noted that watt-hour meter shaft speeds may reach as hlgh.as 6,670 revolut~ons per hour 80 that wlth two reflectlve segment~ over 13~000
The invention relates to photoelectric pulse ini-tiators for pulse operated meter telemetry and recording sys-tems and more particularly to such pulse initiators including a low power digital I.C. arrangement for simplifying and con-trolling the transmitted pulses generated by the pulse ini-tiator and to afford a simplified recording apparatus receiving the transmitted pulses.
In U.S. Patent No. 5,733,493 issued May 15, 1973 to T. M. McClelland III and in U.S. Patent No. 3,878,391 issued April 15, 1975 to T. M. McClelland III et al, both assigned to the assignee of this invention, radiation or photoelectric pulse initiators are disclosed for use in the ,.~
. 45,336 electric power meterlng fleld for lnitlatlng meter data pulses in response to the rate of rotation of a utlllty meter Or the watthour type. In these prlor systems varlou~ technlques are descrlbed for generatlng pulses in respanse to the meter ro-tatlon with an output pulse generator rormed by a latchlng type three-wlre contact device such as a mercury wetted relay.
Large current values are sometlmes requlred to adequately operate the relay ln e~tremely cold enviranments and~are typlcally inefrlclent~ Slnce the rela~ effectlvely lsolates the pulse lnltlator output and a data recelving recarding.clr-cult, 3eparate power supply sources are required to supply both the pulse lnltlator clrcuits and the data recordlng circuits. Mechanical control for varying.the pulse rate.in response to the speed Or the meter shart movement., referred to as the constant Mp in the above-identifled appllcatlon, i8 not always satlsractory for all appllcatio~s. Gear train ratios used ln drivlng-a patterned dlsk or drum ln.the pulse lnltiator mechanlsm or the number of refle~ctlve ~egments form-` lng the indlcla of the pulse lnltlator pattern o~ten requlre substant~al lnterchanglng or:parts and have llmitatlons due to undeslred loadlng a~ the meter shart and space avallable wlthin the meter houslngO RatlQs of less than one.pulse per meter shart rotatlon are often only posslble by.changlng a.gear train ratlo whlle high output.pulse numbers per.sha~t rotatlon a~e often only obtalnable by increaslng the number Or rerlectlve segments ln the shaft drlven pattern.
In the data.magnetlc recordlng ~ystems u~ed ln u~ility meter recordlng.telemetry sDstems lt.has..been noted that watt-hour meter shaft speeds may reach as hlgh.as 6,670 revolut~ons per hour 80 that wlth two reflectlve segment~ over 13~000
-2-45,336 ~063205 pulses per hour mlght be produced rrom a pulse lnltlator whlle the data-pu-lse recelver lncludlng-.a magnetlc.recorder may be capable Or handllng only 7,000 pulses per hour. Thls requlres that the number o~ pulses developed at the radlatlon .. plckup sensors be dlvided to a lower rate proportlonal to the meter sha~t speed.
Accordlngly, it 18 deslrable to slmpllry the com-ponents and numbers Or components requlred t~ lnltlate and record meter data pulses ln puise lnltlators used ln meterlng telemetry systems, to lmprove:the rellablllty and adverse operatlng characterlstics due to:mechanlcal parts, to de-crease power requlred ln such telemetry systems, and.to add greater ~lexlbillty ln controlllng.the output pulse rates.or pulse inltlators to provlde dlrferent dealred.pulse rates relatlve to a.glven watthour meter shart r~tation~ In con-slderatlon Or the arorementloned:de n clencles.and undesirable aspects ln prlor art devlces the present lnventlon is made as brlerly summarlzed herelnarter~ .
BRIEF SUMMARY OF THE IN~E~TION
In accordance wlth.the present~lnventlon a dlrect.
lnput photoelectrlc pulse-lnltlator ror;;meterlng telemetry and recordlng systems lncludes.a low power CMOS dlgital inte-grated clrcult rllp-flop output arrangement whlch 18 .toggled between hlgh and.low loglc states at the Q and.~ outputs~- The loglc states reverse.ln response to-.the alternate actlvatlons Or radlatlon responslve.source-plckup palrs.belng.activated .
at the rate Or rotatlon.of a rerlectlve pattern drlven by a meter movement. The rllp-rlop outp~t ls..er~ectl~.e to dlrectly supply output.current.ln.opposlte dlrectlons to a metering telemetry system recelver such as a magnetlc recorder 80 that each output current polarity transitions are responsive to the detection of segments of the reflective pattern. A pulse rate dividing circuit is included in the pulse initiator circuit by connecting a low power CMOS digital integrated circuit presettable divide-by-N counter to a dual flip-flop CMOS digital integrated output circuit. A pulse division selector device is positional to produce various desirable pulse rates which are equal to or are a submultiple of the rate at which the reflective segmehts are detected. The direct connection with the recorder telemetry receiver permits elimination of switch contact devices between the pulse ini-tiator circuit output and the elimination of separate recorder and pulse initiator power supply circuits to transfer pulse data information generated at the pulse initiator directly into the data recording circuit of a recorder data receiver.
Other advantages and features of this invention will be apparent from the detailed description of the preferred embodiments and the drawings which is briefly described hereinafter.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a schematic view of a meter data record-ing apparatus including a direct input photoelectric pulse initiator and made in accordance with this invention;
Fig. 2 is a front elevational view of a watthour meter included in the apparatus illustrated in Fig. l;
Fig. 3 is a top elevational view of a circuit board supporting the pulse initiator circuit and taken along the axis III-III in Fig. 2 looking in the direction of the arrows;
Fig. 4 is an electrical schematic diagram of the direct input photoelectric pulse initiator arrangement illu-strated in Fig. 2;
Fig. 5 is a fragmentary portion of the electrical schematic diagram of Fig. 4 illustrating CMOS integrated cir-cuit transistor devices provided at the circuit output of Fig. 4;
Fig. 6 is an electrical schematic diagram of an alternative embodiment of the diagram illustrated in Fig. 4;
Fig. 7 is an electrical schematic diagram of another alternative embodiment of the diagram illustrated in Fig. 4 and is found on the same sheet as figure 5; and Fig. 8 is an electrical schematic diagram of an alternative power supply portion for use in the electrical schematic diagrams illustrated in Figs. 4, 6 and 7.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to the drawings wherein like numerals designate like or similar parts in the several Figures, and more particularly to Fig. 1 wherein is shown a metering data recording device 10 of a type referred to as a Load Survey Recorder although this invention is not limited to such tele-metry receiver devices. The device 10 includes a housing 11 containing a watthour meter 12 forming one main unit thereof that has a direct input photoelectric pulse initiator 14.
A magnetic tape data recorder 16 forms a second main unit of the device 10 and the pulse initiator 14 and the recorder 16 are described in particular detail hereinbelow.
The watthour meter 12 is of the integrating type used by electric utility companies including an electro-responsive meter movement having a rotatable shaft 17 for carrying an electroconductive disk 18 and electromagnetic sections including a potential coil 19 and a current coil 20.
The coils 19 and 20 are appropriately connected to power line conductors 22 and 23 serving a utility customer's load 24 such that the disk 18 is electromagnetically driven at a predeter-mined rotational rate corresponding to the electrical energy supplied to the load 24. The meter 12 may, typically, include a dial register 25 for indicating the measured electrical en-ergy consumption quantity in kilowatt hours. ~The meter 12 is removably mounted in the housing 11 to facilitate use of variously rated watthour meters corresponding to the elec-trical power levels to be measured and recorded. Preferably the watthour meter 12 is provided wlth a housing including a plastic meter cover 26 as described and claimed in U.S. Patent
Accordlngly, it 18 deslrable to slmpllry the com-ponents and numbers Or components requlred t~ lnltlate and record meter data pulses ln puise lnltlators used ln meterlng telemetry systems, to lmprove:the rellablllty and adverse operatlng characterlstics due to:mechanlcal parts, to de-crease power requlred ln such telemetry systems, and.to add greater ~lexlbillty ln controlllng.the output pulse rates.or pulse inltlators to provlde dlrferent dealred.pulse rates relatlve to a.glven watthour meter shart r~tation~ In con-slderatlon Or the arorementloned:de n clencles.and undesirable aspects ln prlor art devlces the present lnventlon is made as brlerly summarlzed herelnarter~ .
BRIEF SUMMARY OF THE IN~E~TION
In accordance wlth.the present~lnventlon a dlrect.
lnput photoelectrlc pulse-lnltlator ror;;meterlng telemetry and recordlng systems lncludes.a low power CMOS dlgital inte-grated clrcult rllp-flop output arrangement whlch 18 .toggled between hlgh and.low loglc states at the Q and.~ outputs~- The loglc states reverse.ln response to-.the alternate actlvatlons Or radlatlon responslve.source-plckup palrs.belng.activated .
at the rate Or rotatlon.of a rerlectlve pattern drlven by a meter movement. The rllp-rlop outp~t ls..er~ectl~.e to dlrectly supply output.current.ln.opposlte dlrectlons to a metering telemetry system recelver such as a magnetlc recorder 80 that each output current polarity transitions are responsive to the detection of segments of the reflective pattern. A pulse rate dividing circuit is included in the pulse initiator circuit by connecting a low power CMOS digital integrated circuit presettable divide-by-N counter to a dual flip-flop CMOS digital integrated output circuit. A pulse division selector device is positional to produce various desirable pulse rates which are equal to or are a submultiple of the rate at which the reflective segmehts are detected. The direct connection with the recorder telemetry receiver permits elimination of switch contact devices between the pulse ini-tiator circuit output and the elimination of separate recorder and pulse initiator power supply circuits to transfer pulse data information generated at the pulse initiator directly into the data recording circuit of a recorder data receiver.
Other advantages and features of this invention will be apparent from the detailed description of the preferred embodiments and the drawings which is briefly described hereinafter.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a schematic view of a meter data record-ing apparatus including a direct input photoelectric pulse initiator and made in accordance with this invention;
Fig. 2 is a front elevational view of a watthour meter included in the apparatus illustrated in Fig. l;
Fig. 3 is a top elevational view of a circuit board supporting the pulse initiator circuit and taken along the axis III-III in Fig. 2 looking in the direction of the arrows;
Fig. 4 is an electrical schematic diagram of the direct input photoelectric pulse initiator arrangement illu-strated in Fig. 2;
Fig. 5 is a fragmentary portion of the electrical schematic diagram of Fig. 4 illustrating CMOS integrated cir-cuit transistor devices provided at the circuit output of Fig. 4;
Fig. 6 is an electrical schematic diagram of an alternative embodiment of the diagram illustrated in Fig. 4;
Fig. 7 is an electrical schematic diagram of another alternative embodiment of the diagram illustrated in Fig. 4 and is found on the same sheet as figure 5; and Fig. 8 is an electrical schematic diagram of an alternative power supply portion for use in the electrical schematic diagrams illustrated in Figs. 4, 6 and 7.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to the drawings wherein like numerals designate like or similar parts in the several Figures, and more particularly to Fig. 1 wherein is shown a metering data recording device 10 of a type referred to as a Load Survey Recorder although this invention is not limited to such tele-metry receiver devices. The device 10 includes a housing 11 containing a watthour meter 12 forming one main unit thereof that has a direct input photoelectric pulse initiator 14.
A magnetic tape data recorder 16 forms a second main unit of the device 10 and the pulse initiator 14 and the recorder 16 are described in particular detail hereinbelow.
The watthour meter 12 is of the integrating type used by electric utility companies including an electro-responsive meter movement having a rotatable shaft 17 for carrying an electroconductive disk 18 and electromagnetic sections including a potential coil 19 and a current coil 20.
The coils 19 and 20 are appropriately connected to power line conductors 22 and 23 serving a utility customer's load 24 such that the disk 18 is electromagnetically driven at a predeter-mined rotational rate corresponding to the electrical energy supplied to the load 24. The meter 12 may, typically, include a dial register 25 for indicating the measured electrical en-ergy consumption quantity in kilowatt hours. ~The meter 12 is removably mounted in the housing 11 to facilitate use of variously rated watthour meters corresponding to the elec-trical power levels to be measured and recorded. Preferably the watthour meter 12 is provided wlth a housing including a plastic meter cover 26 as described and claimed in U.S. Patent
3,846,677 issued November 5, 1974 to J.M. Keever et al and assigned to the assignee of this invention.
The pulse initiator 14 is mounted to the frame of the watthour meter 12 in accordance with the description of Fig. 2 and generally includes a sensing head 28 including first and second photoelectric source-pickup pairs including solid state radiation emitter sources and a solid state radiation responsive transistor pairs. The source-pickup pairs are oriented to be alternately operated in response to a pattern of reflective indicia markings or segments 30A, 30B, 30C
and 30D disposed on the bottom of the disk 18. The segments 30A and 30C are oriented on one common circumference of the disk to activate a first source-pickup pair and the segments 30B and 30D are oriented on a second common circumference of the disk 18 to activate a second source-pickup pair in a man-ner corresponding to that described in U.S. Patent No.
30 3,733,493 issued May 15, 1973 to McClelland III and assigned 45,336 ~063Z~
~o the assignee of this inventionO The two source-plckup pairs are connected in the pulse inltlator low power inte-grated clrcult (IlCO) clrcuit 31 mounted along with the sen-slng head 28 on a printed circult board 32 shown ln Figs, 2 and 3O
A pa~r of wire conductors 33A and 34A are connected within the meter 12 to the electrlcal source provlded by the power line canductors 22 and 23O Two further pairs o~ wlre conductors 35A and 36A and 37A and 38A are connected to the clrcult 31 Or the photoelectric ptllse lnitiator 14~ These wire conductors 33A, 34A, 35A, 36A, 37A.and 38A extend through an opening 40 in the plastlc meter cover 26 and ter-minate at a connector 41D A connector 42.mates wlth the connector end 41 and ls connected to wlre conductors 33B, 34B, 35B3 36BJ 37B and 38B which are connected through con-nectors 41 and 42 to the wire conductors 33A, 34A, 35A, 36A, 37A and 38A, respectlveiy. The conductora 33A-33B and 34A-34B supply the pulse initlator circuit 31 ~rom the power 8Up~
ply 43 in the recorder 16 as descr~bed ~urther hereinbelow and the conductors 37A-37B and 38A-37B provide a dlrect input to the data recQrding circuit in the recorder 16 as descrlbed further hereinbelow~
The recorder 16 generally provldes non-return-to-zero (NRZ) recording of data.pul~es.and time lnterval pulses on a magnetic tape 45 carried ln.an inser~able cartridge 46 as described and claimed in U~S~.Pa.tent NoO. 3,678,484 issued July 18, 1972 to A_ Ho Maxwell, JrO and as~lgned to the assignee of this inventlon.~ The tape i8 recorded for extended periods lncludi.ng a one-month period for later data tran~la~
tion by computer processlngO The power supply 43 includes a trans~ormer having a primary winding 43A with outer and cen-ter tapped terminals 44A, 44B and 44C. m ese permit connec-tlon to power line conductor sources, from conductors 33A-33B
and 34A-34~ connected at two of the terminals 44A, 44B and 44C, being measured ~aving eit!ler 120 or 240 volts, Two secondary windings 43B and 43C supply the recorder circuits as well as the pulse initiator circuit 31. The winding 43B
supplies the timing motor 46. The center tapped secondary winding 43C has the outer terminals supplying 24 volts to the time interval recording circuit and 12 volts at the center terminal and one outer terminal to the recorder terminals 47A and 47~. These latter designated terminals are connected through the conductors 35A-35B and 36A-36B to apply the 12 volts to the voltage supply input of the pulse initiator cir-cuit 31.
The time interval recording circuit of the recorder 16 is connected to the power supply winding 43c and includes a full wave recti~ier circuit 49, a resistor 50, a capacitor 51 and a cam operated switch 52 which is actuated in response to the motor 46. The switch 5~ periodically discharges the capacitor 51 through resistor 53 and time interval magnetic record head 54 including a coil 54A. The tape drive (not shown) and ti~e interval recording circuit is provided sub-stantially in accordance with disclosures in the Canadian Application Serial No. 232,001 filed on July 22, 1975, and U. S. Patent 3,913,129 issued October 21, 1975 and are assigned to the assignee of this invention. Accordingly, the discharge of capacitor 51 produces return-to-bias time pulses typically at fifteen, thirty or sixty minute intervals or at such other time intervals as may be desired, as described in the afore-45,336 mentioned patent applicatlons.
In accordance with an lmpo~ta~t advantage.o~ thls inventlon, a slmpler data recordlng clrcuit 18 provlded ln the recorder 16, by a data magnetlc record head ~6 havlng a-coll 56A connected in serles wlth.a reslator 57 and across the recorder termlnals 58A and 5.8B~ ~he wlre conductors 37A-37B and 38A-38B are connected:to the..terminals 58A and .
58B, respectiveiy, so as to provide a dlrect lnput o~ pulse initlator clrcult 31 to the recording oircult lncludlng the data record head 56 ln the recorder i6 a...
In.Flg. 2 there ls shown the meter.l2 separated from the meterlng data recordlng.devlce iO and the manner Or `mountlng the pulse lnitlator clrcult board 32. A pair Or screws 60 secure the circuit board 32 to the meter. rrame 61 -lo2~
below the dlsk 18. The meter:nameplate.~, shown broken away, i9 ~astened to:the ends Or ~orward proJectin~ bosses-63 and 6 Or the frame 61 by a palr~of screws 65 to substantlally co~er the ~ront of the clrcult-board 32... The sensing head 28 i8 rastened to the board 32 by the screws and.the.two radlatlon..
emltter.sources and two radiatlon-responslve transistors, shown ln Flg, 4 are connected to the clrcuit elements Or the-pulse lnltlator circuit 31 by the wlrlng a~rangement 6.7. The dlscrete clrcuit eiements shawn mounted.on the board 32 correspond to the elements ha~lng..llke nume~ical designation in clrcuit diagram.ln Fig. .4 described.herelnbelow. Three low power solld state~digltal lntegrat.ed circult chlp de-vlces 70, 71 and 72 or.the CMOS or COS/MOS (camplementary metal oxlde slll.con) transistor type.proulde important advan-tages ln the pulse initiator clrcult.310.
At lert-hand slde Or the clrcuit board 32 as viewed _g_ ~n Fig. 2 is a pulse division selector pin connector arrange-ment 74. A center pin 75 is circumscribed by eight pins 76, 77, 78, 79, 80, 81, 82 and 83. Although not shown, the pins designated 76 through 83 may be labelled "2", "4", "6", "8", ''lo'', "12", "16" and "20", respectively, on the board 32 shown in Fig. 2 because these pins correspond to the 2:1, 4:1, 6:1, 8:1, lo:l, 12:1, 16:1 and 20:1 pulse rate division ratio provided by the pulse initiator circuit 31.
To ef~ect the different pulse ratios, a ~umper connection 85 is made between center pin 75 and the selected one of the outer pins. For example, pin 76 is connected to pin 75, as shown in Fig. 2 to provide a two to one pulse rate ratio The ~umper connection 85 can be made by soldering a wire strip between the center pin 75 and a selected outer pin or the ~umper connection 85 can be a wire having socket ends for mating with the ends of pins. Alternatively, the pulse division selector pin connector arrangement 74 can be replaced by a eight position rotary selector switch, not shown, to provide the same preselective connections. The 2Q conductors 35A and 36A, shown in Figs. 1 and 4, are connected, at the left side of the circuit board 32, although not shown in Fig. 2, to apply the supply voltage to the pulse initiator circuit 31.
At the right-hand side of the circuit board 32 ;n --~ shown ~ fig. 2, there are two sets of three pins 87, 88 and 89 and 90, 91 and 92 which are also shown in Fig. 4. The pins 88 and 91 provide output pin terminals providing the pulse output of the pulse initiator circuit to the conductors 37A and 38A for direct connection to the data recording cir-cuit in the recorder 16. Jumper wires 94 and 95 are con-nectable between the pins 88 and 87 and 91 and 90, respec-tively, to provide a 1:1 pulse division ratio output of the ~ -10-A
~063Z05 o~ the circuit 31 and wires 94 and 95 are connectable between the pins 88 and 89 and 91 and 92, respectively, to provide the pulse division ratio selected at the selector pin connect~r 74. Thus, the rate at t~h~c~l the reflectlve se~ments 30A, 30R, 30C and 30D
-lOa-~., are detected by the devices in the sensing head 28 will be produced either at the same rate at the pins 88 and 91 or at the aforementioned pulse division ratios selected at the pin connector arrangement 74.
In Fig. 3 there is shown a top elevational view of the c~rcuit board 32 separated fro~ meter mounting shown in F~g. 2. The sensing head 28 includes two package assemblies 28A and 28B each includin~ angularly disposed pair o~ cavities 97A and 97B and 98A and 98B ~or direc ting the emitted and re~lected radiations. The cavities ald in the optical coupling between each o~ the source-pickup pair contained in separate ones of the assemblies 28A and 28B.
Re~erring now to Fig. 4 there is shown the electric circuit diagram o~ the direct input photoelectric pulse ini-tiator circuit 31 carried on the circuit board 32 described hereinabove. The recorder power supply 43 is shown supplying, from the 12 volt secondary winding 45C and conductors 35A
and 36A, the the power input circuit 100 provides recti~ying and voltage regulation ~or the pulse initiator circuit 31 on the circuit board 32. The resistor 101 is connected in one conductor line o~ a pair of lines connecting the power input conductors 35A and 36A across the input o~ a full wave rectifier bridge including conventional rectifier diodes 102, 103, 104 and 105. A ~iltering capacitor 107 and a Zener voltage regulating diode 108 are connected across the output of the rectifier bridge with a resistor 109 connected between the upper ends of the capacitor 107 and Zener diode 108 and in series ~rith positive supply conductor 110 of the pulse initiator circuit 31. A regulated direct current voltage in the order of positive 7.5 VDC is produced on the supply conductor 110 relative to the re~erence supply conductor 112 which is grounded. The VDD supply voltages for the CMOS I.C. components 70, 71 and 72 are applied from the conductor 110 and the VSS voltages are applied from the con-ductor 112.
A first source-pickup pair included in ~he sensing head package assembly 28A shown in Fig. 3 includes a radiation emitter formed by the light emitting diode (LED) 114 and a radiation responsive pickup formed by a phototransistor 115.
The LED 116 and phototransistor 117 are included in the second source-pickup pair contained in the sensing head package assem-bly 28B. ~The LED's 114 and 116 are connected in series with the resistor 118 and in series across the conductors 110 and 112 to be continuously lighted. The collector-emitter circuits of the phototransistor 115 and 117 have emitter connected re-sistors 119 and 120, respectively, connecting the collector-emitter circuits across the conductors 110 and 112. The bases of the phototransistors 115 and 117 have biasing resistors 122 and 123, respectively, connecting the bases to the ground reference conductor 112.
The output of the photoelectric pulse initiator cir-cuit 31 is provided by the CMOS digital integrated circuit 70 which is a dual D-type flip-flop with set-reset capability designated CD4013AE as described at pages 68 through 73 in the RCA Solid State '74 Databook Series SSD-203B; COS/MOS
Digital Integrated Circuits available from RCA Solid State Division, Somerville, New Jersey. Two identical data-type flip-flop circuits F/Fl and F/F2 have independent DATA, SET, RESET, and CLOCK inputs and Q and Q outputs as shown in Fig.
The pulse initiator 14 is mounted to the frame of the watthour meter 12 in accordance with the description of Fig. 2 and generally includes a sensing head 28 including first and second photoelectric source-pickup pairs including solid state radiation emitter sources and a solid state radiation responsive transistor pairs. The source-pickup pairs are oriented to be alternately operated in response to a pattern of reflective indicia markings or segments 30A, 30B, 30C
and 30D disposed on the bottom of the disk 18. The segments 30A and 30C are oriented on one common circumference of the disk to activate a first source-pickup pair and the segments 30B and 30D are oriented on a second common circumference of the disk 18 to activate a second source-pickup pair in a man-ner corresponding to that described in U.S. Patent No.
30 3,733,493 issued May 15, 1973 to McClelland III and assigned 45,336 ~063Z~
~o the assignee of this inventionO The two source-plckup pairs are connected in the pulse inltlator low power inte-grated clrcult (IlCO) clrcuit 31 mounted along with the sen-slng head 28 on a printed circult board 32 shown ln Figs, 2 and 3O
A pa~r of wire conductors 33A and 34A are connected within the meter 12 to the electrlcal source provlded by the power line canductors 22 and 23O Two further pairs o~ wlre conductors 35A and 36A and 37A and 38A are connected to the clrcult 31 Or the photoelectric ptllse lnitiator 14~ These wire conductors 33A, 34A, 35A, 36A, 37A.and 38A extend through an opening 40 in the plastlc meter cover 26 and ter-minate at a connector 41D A connector 42.mates wlth the connector end 41 and ls connected to wlre conductors 33B, 34B, 35B3 36BJ 37B and 38B which are connected through con-nectors 41 and 42 to the wire conductors 33A, 34A, 35A, 36A, 37A and 38A, respectlveiy. The conductora 33A-33B and 34A-34B supply the pulse initlator circuit 31 ~rom the power 8Up~
ply 43 in the recorder 16 as descr~bed ~urther hereinbelow and the conductors 37A-37B and 38A-37B provide a dlrect input to the data recQrding circuit in the recorder 16 as descrlbed further hereinbelow~
The recorder 16 generally provldes non-return-to-zero (NRZ) recording of data.pul~es.and time lnterval pulses on a magnetic tape 45 carried ln.an inser~able cartridge 46 as described and claimed in U~S~.Pa.tent NoO. 3,678,484 issued July 18, 1972 to A_ Ho Maxwell, JrO and as~lgned to the assignee of this inventlon.~ The tape i8 recorded for extended periods lncludi.ng a one-month period for later data tran~la~
tion by computer processlngO The power supply 43 includes a trans~ormer having a primary winding 43A with outer and cen-ter tapped terminals 44A, 44B and 44C. m ese permit connec-tlon to power line conductor sources, from conductors 33A-33B
and 34A-34~ connected at two of the terminals 44A, 44B and 44C, being measured ~aving eit!ler 120 or 240 volts, Two secondary windings 43B and 43C supply the recorder circuits as well as the pulse initiator circuit 31. The winding 43B
supplies the timing motor 46. The center tapped secondary winding 43C has the outer terminals supplying 24 volts to the time interval recording circuit and 12 volts at the center terminal and one outer terminal to the recorder terminals 47A and 47~. These latter designated terminals are connected through the conductors 35A-35B and 36A-36B to apply the 12 volts to the voltage supply input of the pulse initiator cir-cuit 31.
The time interval recording circuit of the recorder 16 is connected to the power supply winding 43c and includes a full wave recti~ier circuit 49, a resistor 50, a capacitor 51 and a cam operated switch 52 which is actuated in response to the motor 46. The switch 5~ periodically discharges the capacitor 51 through resistor 53 and time interval magnetic record head 54 including a coil 54A. The tape drive (not shown) and ti~e interval recording circuit is provided sub-stantially in accordance with disclosures in the Canadian Application Serial No. 232,001 filed on July 22, 1975, and U. S. Patent 3,913,129 issued October 21, 1975 and are assigned to the assignee of this invention. Accordingly, the discharge of capacitor 51 produces return-to-bias time pulses typically at fifteen, thirty or sixty minute intervals or at such other time intervals as may be desired, as described in the afore-45,336 mentioned patent applicatlons.
In accordance with an lmpo~ta~t advantage.o~ thls inventlon, a slmpler data recordlng clrcuit 18 provlded ln the recorder 16, by a data magnetlc record head ~6 havlng a-coll 56A connected in serles wlth.a reslator 57 and across the recorder termlnals 58A and 5.8B~ ~he wlre conductors 37A-37B and 38A-38B are connected:to the..terminals 58A and .
58B, respectiveiy, so as to provide a dlrect lnput o~ pulse initlator clrcult 31 to the recording oircult lncludlng the data record head 56 ln the recorder i6 a...
In.Flg. 2 there ls shown the meter.l2 separated from the meterlng data recordlng.devlce iO and the manner Or `mountlng the pulse lnitlator clrcult board 32. A pair Or screws 60 secure the circuit board 32 to the meter. rrame 61 -lo2~
below the dlsk 18. The meter:nameplate.~, shown broken away, i9 ~astened to:the ends Or ~orward proJectin~ bosses-63 and 6 Or the frame 61 by a palr~of screws 65 to substantlally co~er the ~ront of the clrcult-board 32... The sensing head 28 i8 rastened to the board 32 by the screws and.the.two radlatlon..
emltter.sources and two radiatlon-responslve transistors, shown ln Flg, 4 are connected to the clrcuit elements Or the-pulse lnltlator circuit 31 by the wlrlng a~rangement 6.7. The dlscrete clrcuit eiements shawn mounted.on the board 32 correspond to the elements ha~lng..llke nume~ical designation in clrcuit diagram.ln Fig. .4 described.herelnbelow. Three low power solld state~digltal lntegrat.ed circult chlp de-vlces 70, 71 and 72 or.the CMOS or COS/MOS (camplementary metal oxlde slll.con) transistor type.proulde important advan-tages ln the pulse initiator clrcult.310.
At lert-hand slde Or the clrcuit board 32 as viewed _g_ ~n Fig. 2 is a pulse division selector pin connector arrange-ment 74. A center pin 75 is circumscribed by eight pins 76, 77, 78, 79, 80, 81, 82 and 83. Although not shown, the pins designated 76 through 83 may be labelled "2", "4", "6", "8", ''lo'', "12", "16" and "20", respectively, on the board 32 shown in Fig. 2 because these pins correspond to the 2:1, 4:1, 6:1, 8:1, lo:l, 12:1, 16:1 and 20:1 pulse rate division ratio provided by the pulse initiator circuit 31.
To ef~ect the different pulse ratios, a ~umper connection 85 is made between center pin 75 and the selected one of the outer pins. For example, pin 76 is connected to pin 75, as shown in Fig. 2 to provide a two to one pulse rate ratio The ~umper connection 85 can be made by soldering a wire strip between the center pin 75 and a selected outer pin or the ~umper connection 85 can be a wire having socket ends for mating with the ends of pins. Alternatively, the pulse division selector pin connector arrangement 74 can be replaced by a eight position rotary selector switch, not shown, to provide the same preselective connections. The 2Q conductors 35A and 36A, shown in Figs. 1 and 4, are connected, at the left side of the circuit board 32, although not shown in Fig. 2, to apply the supply voltage to the pulse initiator circuit 31.
At the right-hand side of the circuit board 32 ;n --~ shown ~ fig. 2, there are two sets of three pins 87, 88 and 89 and 90, 91 and 92 which are also shown in Fig. 4. The pins 88 and 91 provide output pin terminals providing the pulse output of the pulse initiator circuit to the conductors 37A and 38A for direct connection to the data recording cir-cuit in the recorder 16. Jumper wires 94 and 95 are con-nectable between the pins 88 and 87 and 91 and 90, respec-tively, to provide a 1:1 pulse division ratio output of the ~ -10-A
~063Z05 o~ the circuit 31 and wires 94 and 95 are connectable between the pins 88 and 89 and 91 and 92, respectively, to provide the pulse division ratio selected at the selector pin connect~r 74. Thus, the rate at t~h~c~l the reflectlve se~ments 30A, 30R, 30C and 30D
-lOa-~., are detected by the devices in the sensing head 28 will be produced either at the same rate at the pins 88 and 91 or at the aforementioned pulse division ratios selected at the pin connector arrangement 74.
In Fig. 3 there is shown a top elevational view of the c~rcuit board 32 separated fro~ meter mounting shown in F~g. 2. The sensing head 28 includes two package assemblies 28A and 28B each includin~ angularly disposed pair o~ cavities 97A and 97B and 98A and 98B ~or direc ting the emitted and re~lected radiations. The cavities ald in the optical coupling between each o~ the source-pickup pair contained in separate ones of the assemblies 28A and 28B.
Re~erring now to Fig. 4 there is shown the electric circuit diagram o~ the direct input photoelectric pulse ini-tiator circuit 31 carried on the circuit board 32 described hereinabove. The recorder power supply 43 is shown supplying, from the 12 volt secondary winding 45C and conductors 35A
and 36A, the the power input circuit 100 provides recti~ying and voltage regulation ~or the pulse initiator circuit 31 on the circuit board 32. The resistor 101 is connected in one conductor line o~ a pair of lines connecting the power input conductors 35A and 36A across the input o~ a full wave rectifier bridge including conventional rectifier diodes 102, 103, 104 and 105. A ~iltering capacitor 107 and a Zener voltage regulating diode 108 are connected across the output of the rectifier bridge with a resistor 109 connected between the upper ends of the capacitor 107 and Zener diode 108 and in series ~rith positive supply conductor 110 of the pulse initiator circuit 31. A regulated direct current voltage in the order of positive 7.5 VDC is produced on the supply conductor 110 relative to the re~erence supply conductor 112 which is grounded. The VDD supply voltages for the CMOS I.C. components 70, 71 and 72 are applied from the conductor 110 and the VSS voltages are applied from the con-ductor 112.
A first source-pickup pair included in ~he sensing head package assembly 28A shown in Fig. 3 includes a radiation emitter formed by the light emitting diode (LED) 114 and a radiation responsive pickup formed by a phototransistor 115.
The LED 116 and phototransistor 117 are included in the second source-pickup pair contained in the sensing head package assem-bly 28B. ~The LED's 114 and 116 are connected in series with the resistor 118 and in series across the conductors 110 and 112 to be continuously lighted. The collector-emitter circuits of the phototransistor 115 and 117 have emitter connected re-sistors 119 and 120, respectively, connecting the collector-emitter circuits across the conductors 110 and 112. The bases of the phototransistors 115 and 117 have biasing resistors 122 and 123, respectively, connecting the bases to the ground reference conductor 112.
The output of the photoelectric pulse initiator cir-cuit 31 is provided by the CMOS digital integrated circuit 70 which is a dual D-type flip-flop with set-reset capability designated CD4013AE as described at pages 68 through 73 in the RCA Solid State '74 Databook Series SSD-203B; COS/MOS
Digital Integrated Circuits available from RCA Solid State Division, Somerville, New Jersey. Two identical data-type flip-flop circuits F/Fl and F/F2 have independent DATA, SET, RESET, and CLOCK inputs and Q and Q outputs as shown in Fig.
4. The logic level present at the DATA input of each flip-flop is transferred to the associated Q outpu~ during the posi -tive-going transition of a ~063205 pulse of the associated CLOCK input. The fllp-flops provide a latching operation by remaining in either the high or low state until a subse~uent trigger pulse is applied. High levels on the SET or RESET inputs accomplish setting and resetting of the fl~p-flops F~Fl and F/F2,.
The Ql and Ql outputs of the flip-flop F/Fl are connected to the circuit board pins 87 and 90 respectively and the Q2 and ~2 outputs of the ~lip-flop F~F2 are connected to t,he pins 89 and 92. Depending upon the position of the aforementioned ~umpers 94 and 95 the meter data pulse output conductors 37A and 38A directly connect the data magnetic record head 56 ~o the Q and ~ outputs of one of the flip-flops F/Fl or F/F2.
It is an important feature of the present invention that the integrated circuits 70, 71 and 72 are of the low power CMOS integrated circuit type to be distinguished from the medium or relative high power solid state integrated cir-cuit types including the common logic na~es of resistor-tran-sistor-logic (RTL), diode-transistor logic (DTL), transistor-transistor-logic (TTL) and emitter-coupled logic (ECL).
These logic families operate at high operating quiescent current requirements in the order of sixty milliamperes and quiescent power requirements in the order of 200 milli-watts. In contrast the substantially lower requirements of the CMOS integrated circuits include operating quiescent current levels in the order of only ten microamperes and quiescent power requirements of 100 microwatts.
Referring now in more detail to the circuit 31 shown in Fig. 4 and in particular to the dual ~lip~flop cir-cuit 70, the SET 1 input to the flip-flop F/FI is connected across the emitter resistor 120 of the phototransistor 117 so that when a reflective disk segment is detected by render-ing the phototransistor 117 conductive so that a high level logic is applied to the SET 1 input. m e RESET 1 input is similarly connected across the emitter resistor 119 so that when the phototransistor 115 is rendered conductive, upon detecting a reflective segment, a high logic state is applied to the RESET 1 input. m e CLOCK 1, S~T 2 and RESET 2 inputs are not used and are connected to the grounded supply conductor 112 along with the VSS terminal of the I.C. circuit 70. The DATA
2 input is connected to the ~2 output. me VDD terminal of the circuit 70 is connected to the supply conductor 110 as shown. With above connection, the Ql and ~1 outputs develop a transition between high and low logic states to reverse cur-rent through the record heat 56. When the jumpers 94 and 95 are connected in the broken line position to the pins 87 and 90 7 the circuit ~1 produces a 1:1 pulse ratio at the pulse initiator circuit output because the pulse dividing part of the circuit 72, described hereinafter, is bypassed.
To product the divide-by-"N" operation of the cir-cuit 31 the CMOS digital integrated circuit 72 is a presettable divide-by-N counter type CD4018 described at pages 95 through 99 of the above-identified RCA Solid State '74 Databook Series SSD-203B. The circuit provides a programmable divide by counter function when connected to the integrated circuits 70 and 71 as shown. m e CMOS digital integrated circuit 71 is a CMOS NAND gate (positive logic) Quad two input type CD4011AD also described in the aforementioned RCA Solid State '74 Databook Series SSD-203B at pages 61 through 67.
The divide-by-N-counter circuit 72 includes five JAM inputs PRESET ENABLE, VSS terminal and RESET
INPUTS connected to ground. The DATA input is connected through a resistor 125 to ground and is also connected to the center pin 75 of the pulse division selector arrangement 74 and further to the CLOCK 2 input of the flip-flop circuit F/F2. The CLOCK input to the circuit 72 is connected directly to the divide by "2" pin 76 and to the Ql output of the flip-flop F/Fl. Since the circuit 72 only advances counting with the low to high transitions at the CLOCK input, the connection from the Ql provides a divide by two function inherently from this connection to the circuit 72. Thus, a single CLOCK logic signal to the circuit occurs for each two reflective segments which are detected. Accordingly, the Ql output of the circuit 72 is connected to the divide by "4" pin 77 since it normally produces a divide two counter output.
The two input NAND gates 127 and 128 of the circuit 71 are required to achieve the divide by "6" output at pin 78 and the NAND gates 129 and 130 are required for the divide by "10" output at pin 80 since they involve division by the prod-uct of numbers including an odd number (2x3 and 2x5). The gates 127 and 129 have their inputs A and B and H and G sep-arately tied together to operate as an inverter circuit and provide the connection described on page 98 of the above identi-fied RCA Solid State '74 Databook Series. Accordingly, the output K of the gate 127 is connected to the divide "6" output at pin 78 with the short circuit inputs A and B of the gate 127 connected to the output K of the gate 128. The inputs C
and D of the gate 128 are connected to the Ql and Q2 of the circuit 72. The Q2 of the circuit 72 is the normal divide by two counter output and is connected to the divide by "8" pin 79. The gate 130 inputs F and E are connected to the Q2 and Q3 outputs of the circuit 72. The output L of the gate 130 is connected to the short circuited inputs H and G of the gate 129 and the output M of the gate 129 is connected to the divide by "10"
pin 80. The divide by "12", "16" and "20" pins 81, 82 and 83 are connected directly to the Q3, Q4 and Q5 outputs of the circuit 72 since they are programmed to divide the count input to the circuit normally by six, eight and ten.
Thus described, the photoelectric pulse initiator circuit 31 is responsive to the rotat.ion of the meter shaft 17 and disk 1~ rotating at a rate corresponding to consumption of electric power of the load 24. The alternate or staggered relationship of the reflective segments 30A, 30B, 30C and 30D, shown in Fig. 1, pass the sensing head 28 to alternating acti-vate the photo-transistor detectors 115 and 117 by rendering or switching them conductive four times with each complete meter shaft rotation. This develops a short low to high or positive going pulse signals across the resistors 119 and 120 which form the input signals in the pulse initiator circuit 31. The alternate positive going input signals to the SET 1 and RESET 1 inputs of the flip-flop F/Fl toggle or switch the flip-flop so that Ql and Ql output go between low to high and high to low logic states alternately and remain latched in this state until the next appropriate set or reset signal is received. It is important to note that Q and Q outputs of the flip-flop circuits in the circuit 70 characteristicly never both go high during the same instant so that one flip-flop output goes low before the other goes high. Positive going transitions at the CLOCK input at the presettable divide-by-N-counter circuit 72 advance the circuit count. The Ql, Q2, Q3, Q4, Q5 of circuit 72 produce divide by two, four, six, eight and ten. The connections at the circuit 71 pro -duce the additional divide by three and five logic operation.
The Ql output of the flip-flop F/Fl will only go high once for each two input pulses developed by the phototransistors 115 and 117. The circuit 31 then provides a product of two pulse counter dividing operations so that setting of the pulse division selector arrangement 74 produces either of divide by two, four, six, eight, ten, twelve, sixteen or twenty at the outputs of the flip-flop F/F2. This is produced as the DATA output of circuit 72 goes from low high at the CLOCK
2 input of flip-flop F/F2. Thus, with the selector arrange-ment 74 connected to pin 76 to be set at divide by "2", two transitions between low and high occur with a complete rotation of the four disk segments. Since the flip-flop F/Fl is togg-led or triggered when each disk reflective segment is detected, a one-to-one pulse transition output is produced at the Ql and Q2 outputs of the flip-flop F/Fl. The Q2 and Q2 outputs of flip-flop F/F2 provide the preselected pulse rate ratio as established by the position of the pulse di-vision selector 74 as noted hereinabove.
Fig. 5 illustrates CMOS transistor devices forming the output of each of the flip-flops F/Fl and F/F2. Each output consists of p-channel insulated gate field effect transistors 135 and 136 and n-channel insulated-gate field effect transistors 137 and 138. The pair of p-channel and n-channel transistors 135 and 137 are connected in series and the pair of transistors 136 and 137 are connected in series with each pair being connected between the VDD and VSS
terminals. The junction of each series transistor pair pro-vides the Q and Q outputs as shown with the gates connected 30 together to provide the two inputs 140 and 141 of each transistor pair. When Q is high and Q is low, transistors 135 and 137 are latched conductive and transistors 136 and 138 are latched nonconductive. Positive current flows in the direction of the arrow 143 through the resistor 57 and recording head coil 56A between VDD and VSS. The current flows in the opposite direction as shown by arrow 144 when the transistor has reversed conductive states to render the Q output high relative to the Q output. The data recording current flow represented by arrows 143 and 144 is in the order of two milliamperes in one preferred embodiment. The current values can be easily adjusted by changing the value of the resistor 57. The very high impedance of the noncon-ductive CMOS transistor is in the high megohm resistance range which makes its quiescent power drain quite low. The source to drain impedance of the conductive transistors is low but is a finite resistance value in the range of a hundred ohms.
Thus, the pulse initiator circuit output can be used with different recorders having different record drive current requirements up to about five ma.
In the operation of the recorder 16 shown in Fig. 1, the Q and Q outputs of the circuit 70 of Fig. 4 produce continuous current flow in the data record head 56 with a change in current polarity with change in state at the selected Q and Q outputs applied to the recorder terminals 58A and 58B by pulse current supplied from the pulse initiator circuit 31. Magnetically recorded data pulses are recorded on the magnetic tape in a NRZ fashion. The data pulse recording is in the same manner as with the prior use of a three-wire contact device which requires the data record head current to be supplied from within the recorder 16. Time interval pulses are recorded ~063205 concurrently in a separate recording track on the tape 45 by the time interval record head 54 as noted hereinabove.
Accordingly, power is supplied from the meter 12 through the wiring and connectors 41 and 42 to the recorder terminals 44A and 44B or 44C so that the recorder supplies the recorder circuits. The pulse initiator circuit 31 is supplied as well from the recorder 16 back through the wiring and connectors 41 and 42 from the recorder terminals 47A and 47B.
In Fig. 6 there is shown an alternative photo-electric pulse initiator circuit 31A intended to replace the photoelectric pulse initiator circuit 31 illustrated in Fig. 4 and mounted in the meter 12 as shown for the cir-cuit 31. The same power supply portion 100 and LED radia-tion emitters 114 and 116 and phototransistors 115 and 117 are connected together and are provided in the sensing head 2~ as described hereinabove. The same dual D type flip-flop digital integrated circuit 70 and presettable divide-by-N
counter digital integrated circuit 72 are used as described for the pulse initiator circuit 31 with connections as shown in Fig. 6. The digital integrated circuit 71 of the circuit 31 is not used to reduce the cost and produce a different pulse dividing operation in the circuit 31A. The RESET 1 and SET 1 inputs to the circuit are connected to the phototransistors 117 and 115 to toggle the flip-flop outputs Ql and Ql each time a phototransistor is switched conductive. The Q2 and Q2 outputs of the flip-flop circuit 70 provides preselectable pulse division ratios at the out-put terminals 150 and 151. The conductors 37A and 37B pro-vide the two-wire pulse initiator output as for the circuit 30 31. Common polarity ends of conventional diodes 153 and 154 are connected with the polarity shown to the Q and Ql outputs of the circuit 70. The opposite common polarity ends of the semiconductor diodes 153 and 154 are connected together and through a resistor 155 to the grounded supply conductor 112 and also to the CLOCK input of the circui.t 72.
The diode connections uniquely produce a low to high pulse transition at the CLOCK input of the circuit 72 with change in the logic states of Ql and Ql~ In effect, the diodes double the frequency of the low to high transitions normally occurring at either of the Ql or Ql outputs. The junction capacitances of the diodes 153 and 154 and the value of the resistor 155 assure that the required time spacing between consecutive low to high transitions is provided and also that the minimum CLOCK input pulse width is provided. The DATA input is connected to the CLOCK 2 input. The circuit 72 is programmed to divide the low to high pulse transitions from the diodes 153 and 154 so that divide by "2", "4", "6", "8" and "10" operations occur at the Ql, Q2, Q3, Q4 and Q5 outputs, respectively.
To preselect the desired pulse dividing ratio to be established at the terminals 150 and 151 a pulse division selector multiple contact switch arrangement 154 is provided.
A rotary switch arm 155 is positional to connect the switch common input terminal 156 with one of the switch terminals 158-1, 158-2, 158-4, 158-6, 158-8 and 158-10 which corre-spond to the divide by "1", "2", "4", "6", "8" and "10" when the terminals 157, 158-1, 158-2, 158-4, 158-6, 158-8 and 158-10 are connected to the DATA input, CLOCK input Ql, Q2, Q3, Q4 and Q5 outputs of the circuit 72, respectively.
Fig. 8 illustrates an alternative power input cir-cuit lOOA intended to replace the circuit 100 45,336 shown ln Flgso 4, 6 and 70 The LED's 114 and 116 are con-nected between the 12 volt AC input supplied by the conductors 35B and 36B and the same full wave rectifier bridge included in the power supply--portion 100. Oppositely poled serles connected Zener diodes 161 and 162 are connected acros~ the series connected LED's 114 and 116 and the.a~orementioned resistor 118 so that the LED's.are llghted.only during the positive hal~ cycle o~ the current occurring across the con-ductors 35B and 36B. This aids in extending the operating ll~e o~ the LED's 114 and 116.
In Fig 7 there is shown a further alternative em-bodiment o~ a pulse initlator clrcult 31B lntended to replace the circuit 31 as described herelnabove when either the output pulse rate of the pulse lnitiator may be equal to or 1/2 the input pulse rate from the phototranslstoræ 115 and 117. In the clrcuit 31B only the dual ~ type M ip-~lop digital inte-grated circult 70 ls used and is the same type as described for the clrcult 70 shown in Fig~ 4 including the two ~lip-flops F/Fl and F/F20 The Ql and ~1 outputs are connected to the circuit output terminals 160 and 161 and.the Q2 and Q2 out-puts are connected to the circult output termlnals 162 and 1630 The conductors 37A and 38A are connectable to the pair of out-put termlnals 160 and 161 or to the pair o~ output termlnals 162 and 163 to provide either a divide by "1" or divide by "2"
output to the recorder as descrlbed hereinabove ~or the clr-cuits 31 and 31A~
The SET 1 input and RESET 1 lnput ~re connected to the phototransistor 11~ and 117. The Ql output is connected to the CLOCK 2 input and Q2 output is connected to the DATA
2 inputO The DATA 1, CLOCK 1, SET 2 and RESET 2 are all 45,336 connected together-and to the grounded supply co~ductor 112.
The direct input photoelectric pulse lnitlator circuit 31B
provldes all the advantage~ and lower cost o~ the photo-electric pulse lnitlator ¢lrcuits 31 and 31A where the.addl-tlonal advantage Or preselectable output pulse ratios are not requlred.
While the embod~ments Or the dlrect lnput photo-electrlc pulse initiator and the pulse lnltlator and recorder pulse telemetry receiver descrlbed herelnabove ~or metering telemetry and recorder systems constltute prererred.embodl-ments o~ this lnventlon lt 18 contemplated that modi~lcatlons and substitution of equivalen~ parts may be wlthln the spirlt and scope o~ this lnventlon.
.
The Ql and Ql outputs of the flip-flop F/Fl are connected to the circuit board pins 87 and 90 respectively and the Q2 and ~2 outputs of the ~lip-flop F~F2 are connected to t,he pins 89 and 92. Depending upon the position of the aforementioned ~umpers 94 and 95 the meter data pulse output conductors 37A and 38A directly connect the data magnetic record head 56 ~o the Q and ~ outputs of one of the flip-flops F/Fl or F/F2.
It is an important feature of the present invention that the integrated circuits 70, 71 and 72 are of the low power CMOS integrated circuit type to be distinguished from the medium or relative high power solid state integrated cir-cuit types including the common logic na~es of resistor-tran-sistor-logic (RTL), diode-transistor logic (DTL), transistor-transistor-logic (TTL) and emitter-coupled logic (ECL).
These logic families operate at high operating quiescent current requirements in the order of sixty milliamperes and quiescent power requirements in the order of 200 milli-watts. In contrast the substantially lower requirements of the CMOS integrated circuits include operating quiescent current levels in the order of only ten microamperes and quiescent power requirements of 100 microwatts.
Referring now in more detail to the circuit 31 shown in Fig. 4 and in particular to the dual ~lip~flop cir-cuit 70, the SET 1 input to the flip-flop F/FI is connected across the emitter resistor 120 of the phototransistor 117 so that when a reflective disk segment is detected by render-ing the phototransistor 117 conductive so that a high level logic is applied to the SET 1 input. m e RESET 1 input is similarly connected across the emitter resistor 119 so that when the phototransistor 115 is rendered conductive, upon detecting a reflective segment, a high logic state is applied to the RESET 1 input. m e CLOCK 1, S~T 2 and RESET 2 inputs are not used and are connected to the grounded supply conductor 112 along with the VSS terminal of the I.C. circuit 70. The DATA
2 input is connected to the ~2 output. me VDD terminal of the circuit 70 is connected to the supply conductor 110 as shown. With above connection, the Ql and ~1 outputs develop a transition between high and low logic states to reverse cur-rent through the record heat 56. When the jumpers 94 and 95 are connected in the broken line position to the pins 87 and 90 7 the circuit ~1 produces a 1:1 pulse ratio at the pulse initiator circuit output because the pulse dividing part of the circuit 72, described hereinafter, is bypassed.
To product the divide-by-"N" operation of the cir-cuit 31 the CMOS digital integrated circuit 72 is a presettable divide-by-N counter type CD4018 described at pages 95 through 99 of the above-identified RCA Solid State '74 Databook Series SSD-203B. The circuit provides a programmable divide by counter function when connected to the integrated circuits 70 and 71 as shown. m e CMOS digital integrated circuit 71 is a CMOS NAND gate (positive logic) Quad two input type CD4011AD also described in the aforementioned RCA Solid State '74 Databook Series SSD-203B at pages 61 through 67.
The divide-by-N-counter circuit 72 includes five JAM inputs PRESET ENABLE, VSS terminal and RESET
INPUTS connected to ground. The DATA input is connected through a resistor 125 to ground and is also connected to the center pin 75 of the pulse division selector arrangement 74 and further to the CLOCK 2 input of the flip-flop circuit F/F2. The CLOCK input to the circuit 72 is connected directly to the divide by "2" pin 76 and to the Ql output of the flip-flop F/Fl. Since the circuit 72 only advances counting with the low to high transitions at the CLOCK input, the connection from the Ql provides a divide by two function inherently from this connection to the circuit 72. Thus, a single CLOCK logic signal to the circuit occurs for each two reflective segments which are detected. Accordingly, the Ql output of the circuit 72 is connected to the divide by "4" pin 77 since it normally produces a divide two counter output.
The two input NAND gates 127 and 128 of the circuit 71 are required to achieve the divide by "6" output at pin 78 and the NAND gates 129 and 130 are required for the divide by "10" output at pin 80 since they involve division by the prod-uct of numbers including an odd number (2x3 and 2x5). The gates 127 and 129 have their inputs A and B and H and G sep-arately tied together to operate as an inverter circuit and provide the connection described on page 98 of the above identi-fied RCA Solid State '74 Databook Series. Accordingly, the output K of the gate 127 is connected to the divide "6" output at pin 78 with the short circuit inputs A and B of the gate 127 connected to the output K of the gate 128. The inputs C
and D of the gate 128 are connected to the Ql and Q2 of the circuit 72. The Q2 of the circuit 72 is the normal divide by two counter output and is connected to the divide by "8" pin 79. The gate 130 inputs F and E are connected to the Q2 and Q3 outputs of the circuit 72. The output L of the gate 130 is connected to the short circuited inputs H and G of the gate 129 and the output M of the gate 129 is connected to the divide by "10"
pin 80. The divide by "12", "16" and "20" pins 81, 82 and 83 are connected directly to the Q3, Q4 and Q5 outputs of the circuit 72 since they are programmed to divide the count input to the circuit normally by six, eight and ten.
Thus described, the photoelectric pulse initiator circuit 31 is responsive to the rotat.ion of the meter shaft 17 and disk 1~ rotating at a rate corresponding to consumption of electric power of the load 24. The alternate or staggered relationship of the reflective segments 30A, 30B, 30C and 30D, shown in Fig. 1, pass the sensing head 28 to alternating acti-vate the photo-transistor detectors 115 and 117 by rendering or switching them conductive four times with each complete meter shaft rotation. This develops a short low to high or positive going pulse signals across the resistors 119 and 120 which form the input signals in the pulse initiator circuit 31. The alternate positive going input signals to the SET 1 and RESET 1 inputs of the flip-flop F/Fl toggle or switch the flip-flop so that Ql and Ql output go between low to high and high to low logic states alternately and remain latched in this state until the next appropriate set or reset signal is received. It is important to note that Q and Q outputs of the flip-flop circuits in the circuit 70 characteristicly never both go high during the same instant so that one flip-flop output goes low before the other goes high. Positive going transitions at the CLOCK input at the presettable divide-by-N-counter circuit 72 advance the circuit count. The Ql, Q2, Q3, Q4, Q5 of circuit 72 produce divide by two, four, six, eight and ten. The connections at the circuit 71 pro -duce the additional divide by three and five logic operation.
The Ql output of the flip-flop F/Fl will only go high once for each two input pulses developed by the phototransistors 115 and 117. The circuit 31 then provides a product of two pulse counter dividing operations so that setting of the pulse division selector arrangement 74 produces either of divide by two, four, six, eight, ten, twelve, sixteen or twenty at the outputs of the flip-flop F/F2. This is produced as the DATA output of circuit 72 goes from low high at the CLOCK
2 input of flip-flop F/F2. Thus, with the selector arrange-ment 74 connected to pin 76 to be set at divide by "2", two transitions between low and high occur with a complete rotation of the four disk segments. Since the flip-flop F/Fl is togg-led or triggered when each disk reflective segment is detected, a one-to-one pulse transition output is produced at the Ql and Q2 outputs of the flip-flop F/Fl. The Q2 and Q2 outputs of flip-flop F/F2 provide the preselected pulse rate ratio as established by the position of the pulse di-vision selector 74 as noted hereinabove.
Fig. 5 illustrates CMOS transistor devices forming the output of each of the flip-flops F/Fl and F/F2. Each output consists of p-channel insulated gate field effect transistors 135 and 136 and n-channel insulated-gate field effect transistors 137 and 138. The pair of p-channel and n-channel transistors 135 and 137 are connected in series and the pair of transistors 136 and 137 are connected in series with each pair being connected between the VDD and VSS
terminals. The junction of each series transistor pair pro-vides the Q and Q outputs as shown with the gates connected 30 together to provide the two inputs 140 and 141 of each transistor pair. When Q is high and Q is low, transistors 135 and 137 are latched conductive and transistors 136 and 138 are latched nonconductive. Positive current flows in the direction of the arrow 143 through the resistor 57 and recording head coil 56A between VDD and VSS. The current flows in the opposite direction as shown by arrow 144 when the transistor has reversed conductive states to render the Q output high relative to the Q output. The data recording current flow represented by arrows 143 and 144 is in the order of two milliamperes in one preferred embodiment. The current values can be easily adjusted by changing the value of the resistor 57. The very high impedance of the noncon-ductive CMOS transistor is in the high megohm resistance range which makes its quiescent power drain quite low. The source to drain impedance of the conductive transistors is low but is a finite resistance value in the range of a hundred ohms.
Thus, the pulse initiator circuit output can be used with different recorders having different record drive current requirements up to about five ma.
In the operation of the recorder 16 shown in Fig. 1, the Q and Q outputs of the circuit 70 of Fig. 4 produce continuous current flow in the data record head 56 with a change in current polarity with change in state at the selected Q and Q outputs applied to the recorder terminals 58A and 58B by pulse current supplied from the pulse initiator circuit 31. Magnetically recorded data pulses are recorded on the magnetic tape in a NRZ fashion. The data pulse recording is in the same manner as with the prior use of a three-wire contact device which requires the data record head current to be supplied from within the recorder 16. Time interval pulses are recorded ~063205 concurrently in a separate recording track on the tape 45 by the time interval record head 54 as noted hereinabove.
Accordingly, power is supplied from the meter 12 through the wiring and connectors 41 and 42 to the recorder terminals 44A and 44B or 44C so that the recorder supplies the recorder circuits. The pulse initiator circuit 31 is supplied as well from the recorder 16 back through the wiring and connectors 41 and 42 from the recorder terminals 47A and 47B.
In Fig. 6 there is shown an alternative photo-electric pulse initiator circuit 31A intended to replace the photoelectric pulse initiator circuit 31 illustrated in Fig. 4 and mounted in the meter 12 as shown for the cir-cuit 31. The same power supply portion 100 and LED radia-tion emitters 114 and 116 and phototransistors 115 and 117 are connected together and are provided in the sensing head 2~ as described hereinabove. The same dual D type flip-flop digital integrated circuit 70 and presettable divide-by-N
counter digital integrated circuit 72 are used as described for the pulse initiator circuit 31 with connections as shown in Fig. 6. The digital integrated circuit 71 of the circuit 31 is not used to reduce the cost and produce a different pulse dividing operation in the circuit 31A. The RESET 1 and SET 1 inputs to the circuit are connected to the phototransistors 117 and 115 to toggle the flip-flop outputs Ql and Ql each time a phototransistor is switched conductive. The Q2 and Q2 outputs of the flip-flop circuit 70 provides preselectable pulse division ratios at the out-put terminals 150 and 151. The conductors 37A and 37B pro-vide the two-wire pulse initiator output as for the circuit 30 31. Common polarity ends of conventional diodes 153 and 154 are connected with the polarity shown to the Q and Ql outputs of the circuit 70. The opposite common polarity ends of the semiconductor diodes 153 and 154 are connected together and through a resistor 155 to the grounded supply conductor 112 and also to the CLOCK input of the circui.t 72.
The diode connections uniquely produce a low to high pulse transition at the CLOCK input of the circuit 72 with change in the logic states of Ql and Ql~ In effect, the diodes double the frequency of the low to high transitions normally occurring at either of the Ql or Ql outputs. The junction capacitances of the diodes 153 and 154 and the value of the resistor 155 assure that the required time spacing between consecutive low to high transitions is provided and also that the minimum CLOCK input pulse width is provided. The DATA input is connected to the CLOCK 2 input. The circuit 72 is programmed to divide the low to high pulse transitions from the diodes 153 and 154 so that divide by "2", "4", "6", "8" and "10" operations occur at the Ql, Q2, Q3, Q4 and Q5 outputs, respectively.
To preselect the desired pulse dividing ratio to be established at the terminals 150 and 151 a pulse division selector multiple contact switch arrangement 154 is provided.
A rotary switch arm 155 is positional to connect the switch common input terminal 156 with one of the switch terminals 158-1, 158-2, 158-4, 158-6, 158-8 and 158-10 which corre-spond to the divide by "1", "2", "4", "6", "8" and "10" when the terminals 157, 158-1, 158-2, 158-4, 158-6, 158-8 and 158-10 are connected to the DATA input, CLOCK input Ql, Q2, Q3, Q4 and Q5 outputs of the circuit 72, respectively.
Fig. 8 illustrates an alternative power input cir-cuit lOOA intended to replace the circuit 100 45,336 shown ln Flgso 4, 6 and 70 The LED's 114 and 116 are con-nected between the 12 volt AC input supplied by the conductors 35B and 36B and the same full wave rectifier bridge included in the power supply--portion 100. Oppositely poled serles connected Zener diodes 161 and 162 are connected acros~ the series connected LED's 114 and 116 and the.a~orementioned resistor 118 so that the LED's.are llghted.only during the positive hal~ cycle o~ the current occurring across the con-ductors 35B and 36B. This aids in extending the operating ll~e o~ the LED's 114 and 116.
In Fig 7 there is shown a further alternative em-bodiment o~ a pulse initlator clrcult 31B lntended to replace the circuit 31 as described herelnabove when either the output pulse rate of the pulse lnitiator may be equal to or 1/2 the input pulse rate from the phototranslstoræ 115 and 117. In the clrcuit 31B only the dual ~ type M ip-~lop digital inte-grated circult 70 ls used and is the same type as described for the clrcult 70 shown in Fig~ 4 including the two ~lip-flops F/Fl and F/F20 The Ql and ~1 outputs are connected to the circuit output terminals 160 and 161 and.the Q2 and Q2 out-puts are connected to the circult output termlnals 162 and 1630 The conductors 37A and 38A are connectable to the pair of out-put termlnals 160 and 161 or to the pair o~ output termlnals 162 and 163 to provide either a divide by "1" or divide by "2"
output to the recorder as descrlbed hereinabove ~or the clr-cuits 31 and 31A~
The SET 1 input and RESET 1 lnput ~re connected to the phototransistor 11~ and 117. The Ql output is connected to the CLOCK 2 input and Q2 output is connected to the DATA
2 inputO The DATA 1, CLOCK 1, SET 2 and RESET 2 are all 45,336 connected together-and to the grounded supply co~ductor 112.
The direct input photoelectric pulse lnitlator circuit 31B
provldes all the advantage~ and lower cost o~ the photo-electric pulse lnitlator ¢lrcuits 31 and 31A where the.addl-tlonal advantage Or preselectable output pulse ratios are not requlred.
While the embod~ments Or the dlrect lnput photo-electrlc pulse initiator and the pulse lnltlator and recorder pulse telemetry receiver descrlbed herelnabove ~or metering telemetry and recorder systems constltute prererred.embodl-ments o~ this lnventlon lt 18 contemplated that modi~lcatlons and substitution of equivalen~ parts may be wlthln the spirlt and scope o~ this lnventlon.
.
Claims (7)
1. A photoelectric pulse initiator for a meter telemetry system transmitting metering data from a rotatable meter movement rotated at a rate related to a measured electric power quantity, comprising: a power supply circuit including a rectifier means connectable to a source of alter-nating current to establish a source of direct current therein;
first and second radiation source-pickup pairs connected to said power supply circuit, each of said first and second pairs including a solid state radiation emitter source and a solid state radiation responsive pickup, said radiation re-sponsive pickups being alternately activated by reflected radiations from said sources at a rate responsive to the rate of rotation of the meter movement; a low power solid state digital integrated circuit flip-flop circuit supplied from said source of direct current in said power supply circuit, said flip-flop circuit including a first flip-flop means in-cluding first SET and first RESET inputs and first Q and first ? logic outputs, said first SET and first RESET inputs being separately connected to one of said radiation responsive pick-ups, said first Q and first ? outputs having alternately latched high and low logic states in response to said alter-nate activation of said radiation responsive pickups; and output means including first and second terminal means con-nected to said first Q and first ? outputs, said output means being connectable to a data receiver means of the telemetry system such that continuous current pulses having either of opposite directions are supplied from said source of direct current to said output means in accordance with said alternate high and low logic states at said first Q
and first ? outputs.
first and second radiation source-pickup pairs connected to said power supply circuit, each of said first and second pairs including a solid state radiation emitter source and a solid state radiation responsive pickup, said radiation re-sponsive pickups being alternately activated by reflected radiations from said sources at a rate responsive to the rate of rotation of the meter movement; a low power solid state digital integrated circuit flip-flop circuit supplied from said source of direct current in said power supply circuit, said flip-flop circuit including a first flip-flop means in-cluding first SET and first RESET inputs and first Q and first ? logic outputs, said first SET and first RESET inputs being separately connected to one of said radiation responsive pick-ups, said first Q and first ? outputs having alternately latched high and low logic states in response to said alter-nate activation of said radiation responsive pickups; and output means including first and second terminal means con-nected to said first Q and first ? outputs, said output means being connectable to a data receiver means of the telemetry system such that continuous current pulses having either of opposite directions are supplied from said source of direct current to said output means in accordance with said alternate high and low logic states at said first Q
and first ? outputs.
2. A photoelectric pulse initiator as claimed in claim 1 wherein said low power solid state digital integrated circuit flip-flop circuit includes a second flip-flop means including DATA and CLOCK inputs and second Q and second ?
outputs of said low power solid state digital integrated circuit flip-flop circuit, said second DATA input being connected to one of the second Q and second ? outputs of said second flip-flop means and said CLOCK input being connected to one of said first Q and first ? outputs of said first flip-flop means so that said second Q and second ? outputs of said second flip-flop means are alternately latched once at high and low logic states for every two alternate latching of said first Q
and first ? outputs of the first flip-flop circuit means; and wherein said output means includes third and fourth terminal means directly connected to said second Q and second ? outputs and, wherein both said first and second terminal means and said third and fourth terminal means are selectively connectable to said receiver means of said telemetry system.
outputs of said low power solid state digital integrated circuit flip-flop circuit, said second DATA input being connected to one of the second Q and second ? outputs of said second flip-flop means and said CLOCK input being connected to one of said first Q and first ? outputs of said first flip-flop means so that said second Q and second ? outputs of said second flip-flop means are alternately latched once at high and low logic states for every two alternate latching of said first Q
and first ? outputs of the first flip-flop circuit means; and wherein said output means includes third and fourth terminal means directly connected to said second Q and second ? outputs and, wherein both said first and second terminal means and said third and fourth terminal means are selectively connectable to said receiver means of said telemetry system.
3. A pulse initiator circuit as claimed in claim 1 wherein said low power solid state digital integrated circuit flip-flop circuit includes a second flip-flop having associated DATA and CLOCK inputs and second Q and ?
outputs with said CLOCK input being connected to said second ? output, and wherein said pulse initiator further includes a low power solid state digital integrated circuit divide by N
counter circuit including DATA and CLOCK inputs and plural ? outputs, said counter circuit DATA and CLOCK inputs being connected to said CLOCK input and said first Q output respectively;
and wherein said pulse initiator further includes a pulse division selector means having plural terminal means each being connected to a different one of said counter circuit ? outputs and said pulse division selector means further having a common terminal connected to said counter circuit DATA input and selectively connectable to one of said plural terminal means for presetting said counter circuit to different count divisions, and wherein said output means includes third and fourth terminal means directly connected to said second Q and second ? outputs and wherein both said first and second terminal means and the third and fourth terminal means are selectively connectable to said receiver means to said telemetry system such that the continuous current pulses are generated at said third and fourth terminal means at a preselected rate which is a submultiple of said rate at which the pickups are activated.
outputs with said CLOCK input being connected to said second ? output, and wherein said pulse initiator further includes a low power solid state digital integrated circuit divide by N
counter circuit including DATA and CLOCK inputs and plural ? outputs, said counter circuit DATA and CLOCK inputs being connected to said CLOCK input and said first Q output respectively;
and wherein said pulse initiator further includes a pulse division selector means having plural terminal means each being connected to a different one of said counter circuit ? outputs and said pulse division selector means further having a common terminal connected to said counter circuit DATA input and selectively connectable to one of said plural terminal means for presetting said counter circuit to different count divisions, and wherein said output means includes third and fourth terminal means directly connected to said second Q and second ? outputs and wherein both said first and second terminal means and the third and fourth terminal means are selectively connectable to said receiver means to said telemetry system such that the continuous current pulses are generated at said third and fourth terminal means at a preselected rate which is a submultiple of said rate at which the pickups are activated.
4. A photoelectric pulse initiator as claimed in claim 3 including a low power solid state digital integrated circuit including a plurality of two input NAND gates, said inputs of each NAND gate being connected to two different ones of said counter circuit ? outputs and the output of each NAND gate being connected to one of said plural terminal means of the pulse division selector means for producing further counter count divisions.
5. A photoelectric pulse initiator as claimed in claim 3 wherein one of said first ? and first Q outputs of said first flip-flop circuit means and said CLOCK input of said counter circuit are connected to one of the terminal means of said pulse division selector means for producing a current pulse output at said first Q and first ? output which have the same pulse rate as said rate at which said radiation responsive pickups are activated.
6. In a meter telemetry system for transmitting pulse information from an electric meter including a rotat-able meter movement rotated at a rate related to an electric power quantity measured by said meter, the combination comprising: a reflective pattern means rotatable in response to the rate of rotation of the meter movement; a photo-electric pulse initiator circuit including first and second radiation source-pickup pairs, each of said first and second pairs including a solid state radiation emitter source and a solid state radiation responsive pickup, said pickups being alternately activated at a rate responsive to the rate at which radiations are coupled between said emitter source and said pickup by rotation of the reflective pattern means, said pulse initiator further including a power input circuit including a rectifier for developing a source of a direct current from an alternating current applied to said power input, a low power solid state digital integrated circuit means supplied by said source of direct current, said inte-grated circuit means including a flip-flop circuit including SET and RESET inputs alternately responsive to said alternate activation of said pickups of said first and second source-pickup pairs, and further including Q and ? logic outputs having alternately high and low logic states in response to the alternate inputs to said SET and RESET inputs, and output means including a pair of terminals connected to said Q and ? outputs for developing continuous opposite polarity current data pulses each having a predetermined polarity responsive to said high and low logic states of said Q and ? outputs, and a recorder telemetry receiver means including a two-wire recorder circuit including an electrical recording means, said receiver means including an alternating current power supply circuit energized by the electric power measured by said electric meter, said alternater current power supply having an output connected to said power input circuit of said pulse initiator for applying the alternating current thereto; and conductor means connecting said pair of terminals of said output means of said pulse initiator circuit to an input to said two wire recorder circuit to energize said recording means by said opposite polarity current pulses to effect data recording of said pulses.
7. In a meter telemetry system as claimed in claim 6 wherein said recorder telemetry receiver means is a magnetic recorder and said electrical recording means in-cludes a magnetic record head for generating non-return-to-zero data record pulses in response to said opposite polarity current data pulses.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/509,611 US3943498A (en) | 1974-09-26 | 1974-09-26 | Direct input photoelectric pulse initiator for meter telemetry and recording systems |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1063205A true CA1063205A (en) | 1979-09-25 |
Family
ID=24027381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA236,442A Expired CA1063205A (en) | 1974-09-26 | 1975-09-25 | Direct input photoelectric pulse initiator for meter telemetry and recording systems |
Country Status (11)
| Country | Link |
|---|---|
| US (1) | US3943498A (en) |
| JP (1) | JPS59880B2 (en) |
| AR (1) | AR209116A1 (en) |
| AU (1) | AU499584B2 (en) |
| BE (1) | BE833750A (en) |
| BR (1) | BR7506191A (en) |
| CA (1) | CA1063205A (en) |
| DE (1) | DE2542739A1 (en) |
| FR (1) | FR2286551A1 (en) |
| GB (1) | GB1518158A (en) |
| IT (1) | IT1050984B (en) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4034292A (en) * | 1976-02-18 | 1977-07-05 | Westinghouse Electric Corporation | Direction sensitive opto-electronic pulse initiator for electrical meters |
| US4327362A (en) * | 1978-10-23 | 1982-04-27 | Rockwell International Corporation | Meter rotor rotation optical sensor |
| US4281290A (en) * | 1979-02-27 | 1981-07-28 | Noranda Mines Limited | Voltage monitor |
| US4365251A (en) * | 1980-12-04 | 1982-12-21 | Westinghouse Electric Corp. | Electrically driven meter totalizing device |
| US4439764A (en) * | 1981-04-09 | 1984-03-27 | Westinghouse Electric Corp. | Dual mode meter reading apparatus |
| DE3401887C2 (en) * | 1984-01-20 | 1986-11-27 | Ingo 4830 Gütersloh Dohmann | Pulse generator for rotary measuring systems |
| US4686461A (en) * | 1984-07-12 | 1987-08-11 | Westinghouse Electric Corp. | Auxiliary equipment mounting ring for electric meter |
| US4707679A (en) * | 1984-10-22 | 1987-11-17 | Westinghouse Electric Corp. | Magnetic tamper detector |
| US4713610A (en) * | 1984-11-29 | 1987-12-15 | Westinghouse Electric Corp. | Electric meter with improved sensing head assembly |
| US4665358A (en) * | 1985-05-23 | 1987-05-12 | General Electric Company | Solid state electronic pulse scaler using ratio of two integers |
| US4646084A (en) * | 1985-06-21 | 1987-02-24 | Energy Innovations, Inc. | Meter reading methods and apparatus |
| US4881070A (en) * | 1985-06-21 | 1989-11-14 | Energy Innovations, Inc. | Meter reading methods and apparatus |
| GB2203920B (en) * | 1987-04-23 | 1990-05-16 | Iberduero Sa | Telemetering system for electrical power consumed by various users |
| US5010335A (en) * | 1988-11-29 | 1991-04-23 | Schlumberger Industries, Inc. | Optical port multiplexer for electric metering equipment |
| US5311068A (en) * | 1991-05-22 | 1994-05-10 | General Electric Company | Solid-state energy meter with time-of-use rate scheduling and load control circuit |
| CA2063620C (en) * | 1992-03-20 | 2000-11-21 | Steven A. Baker | Induction watt hour meter non-intrusive and concealed pulse initiator |
| US6885185B1 (en) | 1998-12-01 | 2005-04-26 | Itron Electricity Metering, Inc. | Modular meter configuration and methodology |
| IL145391A0 (en) * | 2001-09-11 | 2002-06-30 | Zacay Ely | In-head converter with display |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3083357A (en) * | 1961-11-29 | 1963-03-26 | Bell Telephone Labor Inc | Remote meter reading system |
| US3646539A (en) * | 1969-05-26 | 1972-02-29 | Sangamo Electric Co | Transmitting unit for meter extension system |
| US3686634A (en) * | 1971-04-02 | 1972-08-22 | Esb Inc | Pulse rate monitor and indicator system utilizing a burst pulse counter and a pulse internal counter |
| US3742472A (en) * | 1971-12-27 | 1973-06-26 | Texas Gas Transmission Corp | Electronic telemetering calibrator |
-
1974
- 1974-09-26 US US05/509,611 patent/US3943498A/en not_active Expired - Lifetime
-
1975
- 1975-09-15 GB GB37808/75A patent/GB1518158A/en not_active Expired
- 1975-09-24 BE BE160314A patent/BE833750A/en unknown
- 1975-09-25 DE DE19752542739 patent/DE2542739A1/en not_active Ceased
- 1975-09-25 CA CA236,442A patent/CA1063205A/en not_active Expired
- 1975-09-25 IT IT41701/75A patent/IT1050984B/en active
- 1975-09-25 BR BR7506191*A patent/BR7506191A/en unknown
- 1975-09-25 AU AU85177/75A patent/AU499584B2/en not_active Expired
- 1975-09-25 AR AR260552A patent/AR209116A1/en active
- 1975-09-26 FR FR7529631A patent/FR2286551A1/en active Granted
- 1975-09-26 JP JP50115708A patent/JPS59880B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR2286551B1 (en) | 1982-08-27 |
| AU8517775A (en) | 1977-03-31 |
| GB1518158A (en) | 1978-07-19 |
| BR7506191A (en) | 1976-08-03 |
| FR2286551A1 (en) | 1976-04-23 |
| DE2542739A1 (en) | 1976-04-08 |
| AR209116A1 (en) | 1977-03-31 |
| IT1050984B (en) | 1981-03-20 |
| US3943498A (en) | 1976-03-09 |
| AU499584B2 (en) | 1979-04-26 |
| JPS59880B2 (en) | 1984-01-09 |
| JPS5163639A (en) | 1976-06-02 |
| BE833750A (en) | 1976-03-24 |
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