CA1088178A

CA1088178A - Event data recording apparatus with digitally encoded time and date

Info

Publication number: CA1088178A
Application number: CA248,979A
Authority: CA
Inventors: Robert E. Dyer
Original assignee: Sangamo Electric Co
Current assignee: Sangamo Electric Co
Priority date: 1975-09-04
Filing date: 1976-03-26
Publication date: 1980-10-21
Also published as: FR2323189A1; US4122498A; FR2323189B1; GB1563510A

Abstract

Abstract of the Disclosure:
A data recording apparatus including a data recording circuit for recording event data provided by a data source on a first track of a magnetic tape and a time recording circuit which effects the recording of time reference data for the event data on a second track of the tape, the time recording circuit including a digital clock which provides encoded data represent-ing month, day, hours and minutes for recording on the tape and an identification data source which provides encoded data re-presenting an identification number for the data source for re-cording on the tape, the time and identification data being re-corded on the tape in a bi-phase format.

Description

~AC~CGROUN~ OF ~ INVEMTION
1. Field o~ the Inven~ion. Thi.s invention relates ~o data recordi~g apparatus, and more particularly, to a multi- -channel data recorder apparatus for recording even~ data and en-coded ~ime and date inf~rmation to provide a time reference for the event da~a

2. Descrip~ion of the Prior Art. Mk1ny types of data recording apparatus are employed to record event clata for various purposes Examples of such data recording apparatus include load survey recorders, billing recorders, or the like which are em-ployed by the utility industry to obtain data for use in customer ~:
s~udy analysis, load surveys, load monitoring, automatic billing, data collecting and the like. In such recorders, it is generally desirable to provide a time reference for the recorded data.
One such survey recorder disclosed in the US Patent 33829,772 to Norman F. M~rsh et al~ entitled "Load Survey Record-er for Measuring Electrical Parameters", comprises a two-track cassette recorder lncluding recorder circuitry having a data re-corder section which is responsive to input pulses representing a measuremen~ for recording data pulses on a first track of a magnetic t~pe~ and a time recorder section which is responsive to timing pulses to record time data on the second track of the tape to identify predetermined time intervals in which data re-cording occurs. The data relating to a load measured by the utility meter along with the time re~erence is recorded on the tape in a form which is compa~ible for use with available data pro essing equipment~
At a time determined by the natuxe of the usage of the equipment~ the cassette tape is removed rom the survey _ , ~ :

recorder and returned to a processing ce~ter where the tape is played back over tape proeessing equipment ~o retrieve the re-corded information which may be supplied to a compu~er for pro-cessi~g, In the patented survey recorder, timing pulses are re-corded on the tape at predetermined intervals, such as at one pulse every fifteen minutes. Accordingly, when the load survey data is processed~ the re~erence timing pulses must be converted to "rPal ~ime" to det~rmine the demand intervals at selected hours of a given day. Since the tape casset~es e~ployed ln such survey recorders typically record data for a period of approxim-ately one month, it is evident that the conversion of the time reference ~o a given day, or ~o a given hour of the day is dif-~ioult and time consuming.
Also, while the patented system provides data which is compatible for use with available data processing equipment and permits prin~out of ~he recorded data in a conventional computer : print out, in some instances, it may b~3 desirable to provide a visual display of the data as the data is being pr~cessed.
~20 A further consideration is identification of the data source. Normally, an identlfying code such as the serial number of the ut~lity device being m~nitored is hand written on the cassette cartridge to identify the utility device which provi-ded the data when the recorded cassette is returned to a process-i~g cen~er. In the event the tape cassette is not marked to iden~ify ~he utility meter, it may be impossible to determine the source of the data bei~g pro~e~sed, There~ore, it would be desirable to have a data record-ing apparatus which provides a more precîse time reerence for . ~ .. ~ . .

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recorded event data. It would also be desirable to have a data recording apparatus which reco:rds data in a format which i.s suitable for driving a conventional display apparatus, such as a segmented light emitting diode display unit. It would also be desirable to have a data recording appara-tus which automatically records an identification number for the source of the recorded event data.

STATEMENT OF TIIE INVENTION
It is therefore, an object of the present invention to provide a data recording apparatus which provides a time :
reference for recorded data which inc].udes encoded time of -day and calendar date information.
The invention as claimed herein is in a data recording apparatus having data recording means for recording event data provided by a data source on a multitrack recording medium, a time reference recording means for recording a time reference for the event data on the recording medium comprising timing means for providing timing pulses at a predetermined rate"
encoder means controlledby the timing pulses to generate time reference signals at the predetermined rate for recording on one track of the recording medium to provide a continuous time reference for the event data, ~ime reference data source .
means for supplying coded data representing time of day and ~.
calendar date information to the encoder means, and control means for periodically enabling the encoder means to respond to the coded data to encode the time reference signals with the coded data to provide modified time reference signals for .. -recording on the one track of the recording medium as a portion , of the continuous time reference. .~. ~
The invention as claimed herein is also in a data ~;:
recording apparatus having event data recording means for -recording event data which is provided periodically during a ,. "

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given time interval by a data source, on a first track of a recording rnedium which is rnoved continuously during the time interval, a time reference recording means for recording a tirne reference for the event data on a second track of the recording medium, the time reference recording means comprising time reference data source means operable to provide coded data re-presenting time of day information and calendar date information, and output means including timing means responsive to the time reference data source means for continuously providing timing signals, and encoder means responsive to the timing signals and the coded data to generate time reference signals, including signals coded to represent the time of day and calendar date information, for recording on the second track of the recording medium as a continuous time reference for the event data. .-~
The invention as claimed herein is also in a multitrack data recording apparatus having at least first and second recording head means, event data recording means for providing : -drive signals for the first recording head means to effect the recording of event dat~ provided by a data source on one track of a magnetic tape, a time reference recording means for re-cording a time reference for the event data on the tape during ..
predetermined recording intervals, the time reference recording , means comprising time reference data source means including ~:
digital clock means operable in a first mode to provide code :
words representing time information, the digital clock means .
being operable in a second mode to provide code words represent- ~
ing date information, timing control means for providi.ng timing ;:
signals for controlling the digital clock means to select the .

operating mode for the digital clock means, and output means including enabling decoder means responsive to a preselected one of the code wordswh.ich is provided by the digital clock means ::
at the start of a recording interval to enable the output means :~:.
to be controlled by the timing control means to receive the code :~

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words provided by the digital clock means during the recording interval in a predetermined sequence and to provide drive signals for one of the recording head sneans to effect the recording of both the time and date information on one of the tracks of the magnetic tape.
The invention as claimed herein is additionally in a multitrack data recording apparatus including event recording means for recording event data provided by a data source on one track of a magnetic tape, a time reference recording means for recording a time reference for the event data on the tape, the time recording means comprising time reference data source means including digital clock means operable in a first mode to provide multibit code words representing time information the digital clock means being operable in a second mode to provide multibit code words representing date information, timing control means for providing timing signals for controlling the digital clock means to select the operating mode for the digital clock means, and output means including phase encoder means operable during predetermined recording intervals to respond to the bits of the words to provide phase encoded signals at a prede- ~:
termined rate which represent the bits of the code words for -recording on the tape, the phase encoder means being controlled by the timing.control means during time intervals between successive recording intervals to provide further phase encoded recording signals at the predetermined rate for recording on the tape.
The invention as claimed herein is furthermore in a :data recording apparatus having data recording means for .
recording event data provided by a data source on a recording . : :
medium, a time reference recording means for recording a time ~ .
reference for the event data on the recording medium comprising ~ .
pulse generating means for providing timing pulses at a pre- - :
determined rate, phase encoder means operable during a first - 6 - : .
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time interval to be responsive to each of the time pulses to provide a biphase signal ineluding Eirst and second siynals at first and second logic levels at the predetermined rate to permit the time reference to be derived from the biphase signal, and time reference data source means for providing a plurality of multibit data words representing time of day and calendar date information, the phase encoder means being operable during a second time interval to be responsive to the timing pulses and the data words to provide further biphase signals including a biphase signal corresponding to each bit of each of the data words, each ~ . -of the further biphase signals including first and second signals at first and second logic levels in a sequence represent-ing the coding for the corresponding bit to permit the time reference to be derived f~om the further biphase signals, and : ~ :
means for recording the biphase signals on the recording medium.
DESCRIP~ION OF THE DRAT~INGS
Figure 1 is a block diagram for a data reeorder apparatus provided by the present invention;
Figure 2, is a bloek diagram of a time recorder circuit .: ~ -of the data recorder apparatus of Figure l; -:
Figure 3 is a timing diagram for the time recorder circuit shown in Figure 2;
Figures ~-6 when assembled as shown in Figure 12 show a partial bloek and sckematic circuit diagram for the time reeor~er eireuit of Figure 2;
Figure 7 is a sehematic circuit diagram for a manual ~
time set circuit employed in the time recorder circuit; : -Figure 8 is a schematie circuit diagram for a display unit for use with the time recorder circuit; :
Figure 9 is a timing diagram for the time reeorder .:
eireuit;

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Figure 10, which is located below Figure 8, is a timing diagram for a phase encoder circuit of -the time recorder circuit;
Fi.guresllA- llD show the time reference data format for the data recording apparatus; and, ~0 ,~
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Figure 12, which is located below Figure 7, S~OW8 how Figure 4-6 are to be assembled.
DESC~IPTION OF A PREFERRE~ EMBODIMENT
___ _ ~ __ Referring to the drawings, Figure 1 is a block diagram of a data recording apparatus 10 provided by the present invention which is operable to p~ovide a magnetic tape recording of event data along with a time reference for indic~ting predetermined ~ime intervals in which event data recording occurs. The data recording apparatus 10 may include a casse~.e-type tape supply 10 (not shown) and may employ a time record head Th and a data :
record head Dh to provide two-track record ~g of time and event data. It is apparent that a grea~er number of recording tracks may be provided through the inclusion of additional recording heads to permit a plurali~y of event data ~racks/ all referenced to a common time track to aid in recovery of the data.
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In the exemplary embodiment wherein two~track record-ing is employed, the data head Dh is lenergized by an associated data recording circuit 12 to record d.ata pulses representing event data on a first track of a m~gn~etic tape T as the tape T
is advanced past the data record head Dh by a suitable tape transport apparatus 19. The time record head Th i9 energized by an a~sociated time recording circuit 15 which records the time referen e data on a second ~rack of the tape T. In the exemplary embodiment, event data is recorded on the tape in a ~ :
non return-to-zero format and the reference data is recorded on the tape in a bi-phase format to permit a elock sign31 to be - -derived from t~e recorded time reference data when the data is processed.
The data reoord:Lng apparatus 10 may be employed as a ... .....
billing recorder or a load survey recorder to record measurement .
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data prov kied by a util:lty clevice, ~uch as an electric rneter, a gas m~er, a wa~er meter or the lik~ or any other type of peri.od-ically recurring data as may be provided by a monitoring or measuring device. The event data is provided by a data source 11 connec~ed to the utility device ~not shown) 7 which provides pulses indicative of such measurement da~a and extends the pulses to the data recording circuit 12~ The data recording circuit 12 includes a data record control cixcuit 13 which responds to the pulses to provide energizing signals for the data record head Dh over a sultable data record head driver circuit 14.
The time recording circuit 14 includes a time data reference source 16 which provides time reference data including time of day data and calendar date data. In accordance with the present invention, the time reference data source 16 pxovides a four digit representation including hour and minute of time and a four digit representation o date including day and month.
The time reference data provided by the time reference data source 16 is suppli~d to a time record control circuit ~7 which provides energizing signals for the time record head Th over a time record head driver circuit 18. -The time record control circuit 17 also e~ects the r~coxding of an identification number on ~he tape T -for identifying the da~a recorder 10.
While in the exemplary embodiment the time and date data and ~he iden~ification da~a are recorded on a common ~rack, it is apparent that multi-track recording may be used to permit the time and date data and the identifica~ion data to be recorded in sep-arate tracks or in a plurality of tracks. Also, timing pulses may be recorded in one track and the time and identification data may be recorded in one or more tracks. In addi~ion, the time and date J~ data and -10-~ t7~
the identification number may be recorded in one tr~ck~ and through the use of a suitable inverter~ the lnverse o such data may be recorded in a furtller track for redundancy checklng pur-poses.
The data recorder circuit 12 and the tape transport apparatus 19 may be similar to those employed in the load survey unit described in the U.S. Paten 3,929,772 to Norman F. M~rsh et al, referenced above, which records ~vent data in one track and a time reference in another track. For multitrack recording, 1~ employing more that two tracks, a multitrack recorder including a tape cartridge, a transport apparatus and an event data record-ing circuit of the type disclosed in the U.S. Patent 3,602,458 to W,P~ Doby, may be employed. Accordingly, such apparatus will not be described in ~etail in the present application.
Reerring to Figure 2~ which is a block diagram of the time recorder cixcuit 15 of the data recording apparatus 10, the t~me recorder circuit 15 includes the time reference da~a source 16 and the time re.cord control circuit 17. The time reference data souxce 16 comprises a digital clock 21 which provides digital encoded data representing time and date. A~select cir-cuit 22 is controlled by a tlming control circuit 23 to select time and date modes of operation for the digital clock 21. The digital clock 21 is operable in the time mode tc provide four outpu~ words, each of which has seven`bits~ representing hours and minutes over seven output lines 30a-30g. The first and second ou~put words represent uni~s and tens digits, respectively, for minutes, ~d the ~hird and ~our~h output words represent units and tens digits, respectively, for hours. Four digit sel-ect li~es DSl-DS4 multiplex each digit, , , . . ,. . , . , . , . . .. .: . . . , -.

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The digital clock is operable in the date Mode to pro-vide four output woxds, each of which ~s seven bits, representing day and month~ t:he firs~ and second output words repxe~,enting ~nits and tens digits 9 respectively, for-days, and the third and fourth output words representing units and tens digits, respec-tively, for months.
The recording apparatus 10 may include a four digit LED display unit 2~ to provide a visual readout o~ time of day and ca~endar date ~ata as provided by the digltal clock 21.
Accordingly, the seven bit output of the digital clock 21 .is encoded in a format suitable ~or driving the light emitting diode CLED) display 28 Each o the outputs a-g of the digital clock 21 energiæe a dif~erent one of the seven segments of the four LED arrays of ~he display unit 28 ~Figure 8) in a manner known the art. It is pointed out that the display unit 28 may be provided as optional equipment, and tha~ many recording units 10 employed in the field may not have an associated display unit 28. However7 such units are provided w~th an input/output port to permit the connes~ion of an e~ternal display unit 28 2;0: to the recorder apparatus by an i~staller to permi~ the display of the curren~ time and date data as provided by the digital clock when the recordin~ apparatus is insta:lled.
A ~ime set circuit 24 permits the digital clock 21 to be manually set ~or a selected date and time to provide the proper tlma and date reference when the da~a recording apparatus 10 is initially installed. The setting of the digital clock 21 : : is displa~ed by the display unit 28 while the digital clock 21 is being set to the current time and dats.
The time record control circuit 17 includes a multi ..... . .. . . ................... . . .
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plexer ci.rcui.t 25 whi.ch is operable under the control of tim~ngpulses which are provided by the timing control clrcult 23, to extend the data signals provided on output lines 30a-30g of the digltal clock 21 to a date latch circuit 26. The mul~iplexer circuit 25 receives the parallel data bits which are provided on output lines 30a 30g and serially -routes the seven bits which comprise each output word to the da~a latch circuit 26.
The multiplexer circuit 25 also extends the data output by an identification data source 29, which provides a twenty bit word, which identi~ies the data recorder apparatus 10, to the data latch circuit 26 after the time and date information have been recorded on:the tape~T.
The data latch circuit 26 is operable when enabled to receive each o th~ data pulses proveded by the multiplexer cir- :
cuit 25 and to extend the pulses to the record head driver cir-cuit 18 ~o permit the time and date signals and the identifica tion data to be recorded on the time track of the magnetic tape Tr A phase encoder circuit 27, which is interposed between the output of the data latch circ~it 26 and the recorder driver cir-cuit 18, enables the time reference and identification data to be recorded in a bi-phase ~ormat to permit a clock signal to be derived from the recorded data.
The ~equenc~ng of the time record circuit 17 is con~
trolled by the timing control circuit 23 which receive~ a timing input over lines 31 and 32 from output DSl of the digital clock 21~ The timing control circuit 23 provides timing outputs over lines 37 and 38 for enabling the mul~iplexer cixcu~t 25 and over line 40 for enabling the data latch circuit 26 and the phase en-coder circuit 27. In addition, a timing output provlded over , ~ ,' . , :

line 39 is extentled over a selec~ gate 3S and line 36 to the se-lect circuit 22 for enabling the selection of time and date oper-a~ing modes for ~he digital cloclc 21. The selec~ gat:e 35 enables ~he digital clock 21 to be normally operable in the time mode and to be operable in the date mode only when date information is to be recorded.
In the illustrative embodiment whereirl the data record-ing apparatus is employed as a billing recorder, the time re~ere-nce data and the identificatlon data are writ~en o~ the tape during a 180 second write period at five minute intervals synchro-nized to the lowest order diglt output of the dlgital clock 21, that is, the m~ute units digit. In other applications, the time reerence data may be written at longer time interuals. For ex-ample, in an applica~ion as a survey recorder, the time reference ~ata may be written at ten or fif~een minute intervals.
The encoded data is written at a rate of one binary bit for each t~ seconds ~four seconds for a survey recorder). The time data is wr~tten durlng the ~irst sixty-four seconds of the ; write period. The date data is written during the next sixty-four seconds of the write period. The total message time is 168 seconds. It is pointed ou~ ~hat the data is recorded in the re-verse order of playback, and accoxdingly, a four bit start code is written during the remaining twelve seconds to indicate the stsrt of a message when the tape is played back during processing.
Upon pla~back of the recorded data7 the start code is read first followed by month~ day, hours, and minutes data The 180 second wri~e period is dbfined by the set-ting of write gate 42 which ena~es the data latch circuit 26 for a three minute period. During nor~al operation~ the ~rite gate . . . . . .. .

42 is enabled b~ an output o~ a write gate enable decode circu;t~3 snd associated control logic 4~ whlch decode data xepresenting either a zero or a five pxovicled at the output o~ the dlgital clock 21 when the digital clock is operating in the time mode. A
write gate disable decocle circuit 45 inhibits the write gate 42, and th~is the data latch circuit 26, when data xepresenting the co-dlng of either a three or an eight is provided at the output of the digital elock 21. Accordingly, during a given ten minute in-terval, starting w;~h a zero output, that is at 0, 10, 20,...min-1~ utes) the write gate is enabled during ~he first ~hree minutes ofthe period and is disabled during the next two minutes and clock pulses at a two second rate are recorded on the tape. When the output o~ the digital cloek 21 becomes a five, that is, at 5, 15, 25.,.minutes, the write gate is again enabled for a three minute period and then disabled for two minute periodg after which the cycle repeats continuously. When the data recording apparatus is emplo~ed as a survey recorder, the clDck pulses may be p~ovided at a 4 second rate and ~he write interval may be six minutes in dwration followed by a four minute interval during which time 20 clock pulses are recorded on the tape. The w~ite cycle for such application is initiated upon the ~etection of 0, lo, 20...etc.
minutes.
The data latch circuit 26 is enabled upon the set~ing -o~ the write gate 42 to receive the data bits, which comprise the date time reference data and the identification data provided a~
the output of the mul~iplexi~g circui~ 25.
The setting of ~he write gate 42 also enables a reset circui~ 46 to provide a xeset pulse to the timing cvntrol circuit 23 to reset the t;mi~g control circuit 23 to start from a count

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. , ~ '7 For the purpose o-f preventing the erroneous writing o~
data in the event o~ loss of power or on start-up, a hold off latch circuit 48 is set upon th~ application of power to the time recording circuit 15 and remains set to inhibit the write gate until a data output representing a three or an eight is provided by the digital clock. The hold off latch 48 effects resetting of the control ~ogic so that the time source is operable in the time mode. ~t such time, the holdoff latch 48 is permitting the write gate to be enabled with the next zero or five output of the digi-tal clock 21.
Briefly~ in operation, assuming that the digital clock21 is opera~ing in ~he time mode and that the date on output l~nes 30a-30g o~ the digi~al clock 21 changes from a coding for the digit 9 to the coding for the digit 0, at such time the write enable dec~der circuit 43 is repc~sive to the output of the digital clock 21 to set the write ga~e 42 9 as indicated in line A of the ~iming diagram shown in Figure 3. The write gate 42 enables the d~ta latch circuit 26 to ~-eceive data pulses from the multiplexer circuit 25 and also enables the reset circuit 46 to provide a reset pulse, l~ne B of Figure 3, to effect the reset of the timing control circui~s 23. Accordingly, ~he timing con- :
: trol circuits 23 begin counting from zero to define th~ sixty-four second l~rite time" interval~ indicated in~ ne E of Figure 3, during which time~ the time data is trans~erred from the di-gital clock 21 to the data latch circuit 26 over the multiplexer circu~t 25~ When the timing control eircuit 23 is reset to zero output Q13 on line 39, incllcated on line C of Figure 3, enables the select circuit 22 to select the time mode for th~ digital clock 21.

The first word written is the seven bi~ word repre-senting the minutes ~mit d.igit, The seven data bits provided at the output of the digital clock 21 are ~xtended in parallel to the multiple~ex circuit 25 which is enabled by the digitalselect output DSl of the digl~al clock 21 and timing pulses provided over line 37 ~rom ~he timing control cir~uit 23 to output the bits serially to the data latch cixcuit 26 and thence to the phase en-coder circui~ 27 under the control of clock pulses provided to ~he data latch cir~uit 26 and the phase encoder circuit 27 over line 40 from the timlng control circui~ -~23. The data is written a~ two second intervals and thus a~ the end of a 14 second timing in~er~l, the seven data bi~s represen~ing the coding for the minutes unit digit have been written o~ the tape. At the end of ~he 14 second in~erval~ an additional logic 1 level bi~ provided by the multiplexer 25 is record~d on ~he tape to preven~ the re-currence of a 5 ~art code during the message.
: ~uring the next 16 second irlterval, th~ minu~es tens ;~
digit data i~ provided at the output o~ the digital clock 21 and ~ :
exte~ded OVQr lines 30a-30g to the mul~i-plexer circuit 25 and ~erially gated to the data latch circuit 26 and the phas~ encoder c~rcuit 270 Thereafter, in a similar manner, the digital clock 2~ provides the seven bit word representing the hours units digit a~d the hours ~ens digi~ which are extended over the multiplexer circuit 25 ~o the da~a latch circuit 26 to be written on the tape. :
A~ ~he end of th~ first six~y four second interval of the wri~ing period~ the timi~g control clrcui~s 23 provide an ;`
outpu~, line C o Figure 3 which is ex~ended over the selec~ gate 35 and l~ne 36 to the select circuit 22 to defien the six~y four second '~rite date" interval, indicated at line F of Figure 3, 71!~

durlng which t:im~ the date data is trans:Eerred :Erom the digital cloclc 21 to the data latch circuit 26 over the rnultlplexer circult 25. Accoxdingly, for the next sixty four seconds, the ~our digit representing the date infoxmation is written in corresponding 16 second intervals, The units and tens digits of the day are writ-ten in respective first and second 16 second intervals o~ the '~rite date" interval and the ~its and tens digits o~¦the month are written during the third and fourth 16 second portions, re-spectively, of the '~rite date" interval. Thus, after 128 ~econds have elapsed~ data representing the time and date have been passed over the data latch circuit 26 and the phase encoder circuit 27 and ~e~orded on the tape.
A~ter the fixst 128 seconds of the write cycle, the ~ -timing con~rol circuit 23 provides an output over line 38 which transfers ~he control ~rom writing time and da~e to wri~ing the identification code or the recording apparatus 10 At such time, ~` the timing control circuit 23 provides an output over line 38 5 shown ~n line D o~ Figure 3, which enables the mul~iplexer circuit 25 to gate the outpu~s of the identi~ication data source 29 ~o the data latch circuit 26 for a forty second period, indicated in line G o Figure 3.
Following ~he writing o the identiication number da~a on the tape, the multiplexer circuit 25 effects ~he writing of the beginning of message code duri~g an eight second period, in- .
: dicated in line H of Figure 3.
As indica~ed in line C of Figure 3, at the tlme the multiplexer circuit 25 is enabled to pass the identification code to the data latch circuit 26, the ou~put ofi line 39, shown in line C of Figure 3, enables the digital clock 21 to be operable ~ '7~

in the time mode ~ r a ~urther sL~ty four second period. Accor-dingly~ a~ter 180 seco~ds have elapsed, the digital clock 21 provides ou~puts which represent the cocling ~or the digit 3 and such outputs cause the write gate disable decoder circuit 45 to ~isable the write gate 42, inhibiting the data latch circuit 26.
The write gate ~2 and the data latch circuit 26 remain disabled for a two minute p~riod after which the cycle is repeated. Tim-ing pulses at a two second rate are recorded on the tape in a biphase ~ormat during such two minute interval. Accordingly, the biphase signals representing the time and date data and the timing pulses permit a two second time reference to be derived from the recorded in~oxma~ion.
In ~he event of the loss of power to the data recording circuit 15 3 the hold off latch 48 is enabled upon the restoration of p~wex to inhibit the write gate 42 to prevent the writing of time or date data until an output word represenking the coding or ei~her the digit 3 or ~he digit 8 is provided by the digital :: clock 21 ~nd detec~ed by ~he write gate disable decoding circuit 45. At such time, the hold of~ circuit 48 is disabled and its normal opera~ion is provided.
ETAIL~D DRSCRIPTION
Dig1~tal ~Clock Figures 4-6, when arra~ged as shown in Figure 12 provide a par~ial block and schematic circuit diagram for the time re-f~rence source 16 and the time record con~rol circuit 17. Re-ferring to Figure 47 the d:igital clock 21 may comprise a Digital Watch Intergrated Circuit, such as the Type M~680, which is com-mercially available from Ragen Semiconductor. The clock modu~e 61 provides month, day hour and minute data on seven segment '' ~

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output5 a-g~ and four d;glt c,elect OtltpUtS W,X~Z, an~l Z.
Power for the tirne reference ~ource 16 and the time xecord con~rol circuit l7 is provided b~J a voltage sotlrce 62 which derives a DC level -I-Vl,~ which may be 12 volts,~or example, rom a 120 ~AC source, and a voltage reglllator circuit 63 which derives a :Eurther DC level -'-V2, which may be 3 volts, for example, from the level ~Vl. The time record control circuit 17 is energized by the ~Vl level, and the ~ime reference source 16 is energiæed at level -~V2. ~ rechargeable battexy 65 main~ains power to the clock module 61 upon loss of AC power. The battery 65 is trickle charged when AC power is available. In ~he even~ of a power loss only the digital clock module 61 is energized, to~conserve power.
The clock module 6l provides tha month, day, hourg and minute data on the seven outputs a-g and the four digit select out-puts W-Z, which ~re multiplexed at a 64 Hz rate The clock module 61 provides uninterrupted time and dat:e data and automatically com-pe~sates for lsap years. Accordingly, once the clock module 61 is s~t for the currsnt time o~ day, and clay of mon~h, the outpu~ word ~or words) representing the month is automatically incremented at the end o each month and the coding of the output words repre-senting the day changes to that for the digit one, for indicating the ~irst day of tha month.
A ~rystal controll~d oscillator 66 comprising a crystal CRl, having a natural frequency of 32~768 RHz, and associated bias elements, including resistors Rl ancl R2 and capaci~ors Cl and C2, -~provide a drive frequency ~or the digital clock module 61 upon loss of AC power to enable the digital clock module 61 to remain op~rable until AC power is restored.
The seven sagment outputs a-g o~ ~he clock module 61 are . :
,. ' , .' ' '' ' " ' : ,, :'' '' ' ' :' ~' . ~ ,., . . . . ~ ,, .. . . , -~ 8 connected over repsective bufEer amplifiers 7~ 0 to respective output lines 30a-30g. The bu~er ampliflers 74-80, which may be the Type MC3301, commerciall~ ava~lable rom National Semiconduc~
tor, are operable to raise the 3 volt levels o~ the signals which are provided by Lhe digital clock module 61 to ~2 volt levels for the logic circuits which comprise the time record control circuit 17. Output lines 30b, 30e, 30 and 30g are also extended over inverters 81 84 to provide suitable inputs for the wxite enable and ~he write d~sable decoder c~rcuits.

The four digit select output w-æ, which are of opposite sense relative to the segment outputs a-g, are extneded over buffer ampli~iers 7 85-88 and associated inverters 89-92 to the digit select lines DS~-DSl, respectively. Line DS4 is the h~ghest order digit and line DSl is the lowest order digit. In the pres-ent example, for operation in the time mode, the li~e DS4 corres-ponds to the hours tens dlgit, and the line DSl corresponds to minutes unlts digit For operation in:the date mode, the line DS4 correspo~ds to the tens d~git for months, and the line ~Sl corresponds ~o the u~its digit for day~.
2~ The outputs DSl-DS4 are multiplexed at a 64 Hz rate and the 64 Hz signal on line DSl is extended to the timing control circui~ 23, shown in Figu~e S, to provide a time reference for ~he timing control circui~ 23.
The selec~ circuit 22 comprises switch~ng transistors Ql and Q2 and a~ inverter 72. Transistors Ql and Q2 control the voltage level at the date and time inpu~s, respectively, of the clock module 61~ Transis~or Ql has its collector connected to ~V2 and its emitter connected to ~he ~ime ~nput of the module 61 and over a resistor ~R4 to ground. The base of transistor Ql is , connec~ed over a resistor R5 ~o line 36 which extends the selectinput signal from the timing control clrcuit 23 to the select circuit 22 at point 73, The input oE ~he inverter 72 is connected to point 73 and the output of ~he inverter 72 i9 connected over a resistor R6 to the base of transistor Q2 which has its collector connected to +V2 and its emitter connected to the date input of the module 61 and over a resistor R7 to ground.
When line 36 is at logic 1 level7 transistor ~1 is en-abled and transistor Q2 is disabled to permit an enabling signal to be extended to the time input of the moclule 61. ~en line 36 is at a logic O level, transistor Q2 is enabled and transis-tor Ql is disabled to permit an enabling signal to be extended to the date input o~ the module 61.
The clock module 61 has reset inputs 61a, 61b, and 61c, pins 2~ 22 3 and 1 of the module 61, connected to the manual tlme set circuit 24 to permit setting of the minute, hour and day indication for the module 61 upon the application of pulses pro-vided by a pulse generating circuit of time set circuit 24.
Reerring to Figure 7~ there is shown one example o~
a pulse genera~ing circuit 68 which may be used for this purpose.
The pulse generating circuit 68 comprises a timing circuit 709 such as thc Type NE555, commercially available rom Signitics3 ~nd which is connected for operation as a multivibrator. Resis~
tor R21 and capacitor C3 determined the requency of the multi-vibrator circui~ 3 which may provide pulses at a 1 second rate when the pulse generating circuit 68 is enabled by operation of an advance pushbutton SW5.
.
The signal output of ~he multivibrator 60 at pin 3 is extanded over manually operable switches SWl-SW3 to the reset inputs 61a-61c of the clock module 61. A clouble-pole double-throw ,'.

.
-, :
. .
:. . . . . . ..

71~

switc~ SW~ con~rols the select circuit 22 to ~upply a~ enabling input to either the time or the date input of the clock rnod~le 61. The switch SW4, which has a center off position~ is operable to a "tlme on'l position to connect ~V2 to the base of transistor Ql and ground to the base o:E transistor Q2 to select the time mode, and is ope~ ble to Q "date on" position to connect ~V2 to the base of tr~nsistor Q2 and ground to the base of transistor Ql to select tlle date mode. Thus 9 when the advance switch SW5 is operated, the multivibrator circuit 70 provides 1 second pulses whieh are extended to one of the inputs 61a-61c, depending upon which of the switches SWl-SW3 is operated. When it is de-sired to step the minute or the hour count, the switch SW4 is operated to the "time on" position, and when it is desired to step the date, the switch SW4 is operated to the "date on" posi-~ion.
Re~erring to Figure 8, there is shown a schematic cir-cuit representation ~ an LED display u.nit 28, which may be in-corporated into the recording apparatus 107 or connected exter~a-lly to ~h~ apparatus 10. The LED uni~ 28 cimprises a four digit LED displ~y module 69, such as ~he Type l)L34, commerc~ally avail able from Litronics. The diglt selec~ lines DSl-DS4 are extended ~.
over bufer amplifiers Q3Z-Q3W to digit select inputs 69Z-69W of the display module 69. The segment outputs 30a-30g are extended over respec~ive buffer amplifiers 71a-71g to corresponding segment ~:
inputs 69a~69g of the display 69. Alternatively, a liquid crys~al display un~t may be employed.
As indicated above a not all of the recording units em-ployed may have an associated display unit ~8. H~wever~ the digi-~al clock module 61 has an l.nput/output port which permits connec--~3-~q)~

tion of an ex~ern~l di~play uni~ when it is desired to monitorthe output of the digital clock 61~ The d:Lsplay unit 28 normally displays tlme data except for the 64 second interval when date information is being recorded, At other times, the display of date information is inhibited by a microswltch SW6~ which is operated whenever a tape cartridge is inserted into the recorder apparatus 10. The operation of the manual time/date select switch SW4 is ine~fective to enable the clock module 61 from being op-erable in the date mode unless the ~ape cassette is first re-moved from the recording uni.t 10, permttting the switeh SW6 toclose, Switch SW6 i9 shown operated to an open position, as when a casse~te is loaded into ~he apparatus 10.
rimin ontrol Circui~
Referring to Figure 5, the t;mlng control circuit 23 comprises a 14 s~age ripple carry binary counter-divider 92, suGh as ~he type MC14020, commercially available from Motorola.
The ripple counter 92 has an input at pi~ 10 connected to line DSl to receive the 64 Hz signal provid,ed on line ~Sl by the clock module 61. The counter 92 is operable to divide the 64 Hz signal -:
over successive stages to provide clock or timing pulses at a one second rate at an output Q6 and pulses at a two second rate at an output Q7 which are extended over lines 40 to control the da~ latch circuit 26 and ~he phase encoder circuit 27. The ' .
counter 92 also provldes outpu~s at 4g 8, 16, 32 and 64 second r ates at respective ou~puts Q8-Q12. :~
The timing pulses provided at outputs Q8-Q10, shown in lines A-C of Figure 9, are extended over lines 37 to the multi-plexer circuit 25 to enable sequential routing of the seven bit output words provided by the clock module 61 over lines 30a-30g - --, , ~
~ .. . . .
.. . : , . - . ~ , , .
.

to the clata latch circuit 26, during ~he "write time" and the "write date" cycles. In addition, the timlng pulses are employed to gate the bits of the twenty bit iden~i~lcation code word pro-vided by the identi~ication source 29 to the data latch circuit 26.
The timing pulses provided a~ outputs ~11 and Q12, shown in..lines D a~d E of Figure 9 are extended over lines 38 to the multiplexer circuit 25 to enable selection of time and date data provided by the clock module 61 or identification data pro-vided by the identification d~ta source.
The ripple coun~er 92 also provides timing pulses at a128 second rate, ~line F, Figure 9) at ou~put Q13 and line 39 which e~ables selection o~ the time or date mode for t~e clock module 61. ~ further timing pulse at a 256 second rate is pro-vided at output Q14 of the divider circuit 92 and is used in the selection of data from the clock module 61 or the identification data source 29, The counter 92 is reset to æero in response to a reset : pulse supplied to a reset input R of the counter 92 a the start 20 of each write cycle. .
Mult~ple~er Circuit : THe multiplexer cirCuit 25 comprises five ~-channel data select c~rcuits lOl-105, which may be the type MC14512, commerc~ally avaiable from Motorola~ and dual binary l-out-of-4 :~ selec~ circuit 106, which may be the type MC14555, commercially available ~rom Motorola. The mulitplexer circuit 101 receives the ~our digit select outputs provided over lines DSl-DS4 over resp~cti~e inputs lOlXO-lOlX3, and serially routes the signals extended to inputs lOlXO-lOlX3 to an output 101z of the mul~-~ 7~
plex~r cir~uit 101 under the control o~ timing pulses provided over lines 110 and 111 which ar~ connected to ou~puts ~11 and ~12 of the divider circu:it 92.
Multiplexer circuit 102 receives the seven segment out- :
puts provided over lines 30a 30g by the clock module 61 over re-spective inpu~s 102X0-102X6 of the multiplexer circuit 102. A
further input 102X7 of the circult 102 is connected to the out-put lOlZ of the multiplexer circuit 101 to enable a logic one level bit to be gated to the data latch circuit 26 af~er the seven segment bits appearing on 102X0-102X6 have been gated to the data la~ch circuit 26.
The multiple~er 102 serially routes the signals extend- :
~d to inputs 102X0-102X6 to an output 102Z o~ the multiplexer circuit 102 ~nder the control of timing pulses pro~ided over lines 112-114 which are connected to respective outputs Q8-Q10 of the ~:.
divider circuit 920 The mul~ipl~xer circuit 102 is enabled to respond to the timing pulses provided on line 37, which includes lines 112-114, to route the signals supplied to inpu~s 102X0-lO~X7 of the 2a cireuit 102 to the output 102Z whenever an enabling signal is supplied to an inpu~ 102D by a gate 116. Gate 116 comprises a .
NAND gate havi~g a first input connected to the outpu~ lOlZ of the circuit 101~ The output Ql4 of the divider circuit 92 is connected over an in~erter 115 to a second input of gate 11~ to enab~e gate 116 during th~ first 128 seconds of each write cycle.
Multiplexer circuits 103~105 are controlled by the tim-ing pulses provided over lines 112-114 to extend ~he twenty b~t ~-identification code to ~he data latch circuit 26. Inputs 103X0-103X7 and lO~X0-104X7, of respec~ive multiplexer circui~s 103 -~6-,.' ~- ~ ` ' ~ ' .' -and 104 and inpu~s lOSXO-lOSX3 of multiplexer circuit 105 are connec~ed to a different one of the OlltpUtS, indicated ~s 2 2 9 of the îdentification data source 29 to receive the twenty bit identi~ication code. The identification data source 29 provides harcl wired logic inputs to the multiplexer circuits 103-1053 rapresented by block 2g,which e~tend either a logic one or a logic zero to the input of the multiplexer circuits 103-105 connected thereto. A further input 105X4 of multiplexer circuit 105 is connected to an output indicated 22 of the identification source 29 which provides a logic zero level to sllch input.
Further inputs 105X5-105X7 of multiplexer circuit 105 are commonly co~nected to the output lOlZ of multiplexer circu~t 101 are ..
commonly connec~ed to the output lOlZ of multiplexer circuit 101 which is normally maintained at a lo~ic one level as multiplexer :~ ~ 101 operates~ :
The multiplexing circuits 103-105 are enabled to respond to the timing pulses provided over lines 112-114 whenever an associated enabli~g circui~, respectîve ga~es 118-120 are enabled.
Gates 118~120 each have a respec~ive inpu~ commonly connected to the output Q14 of the divider circuit 92. Gates 118-120 each : have second inputs connected to respective ou~puts 1~1-123 o~ the select cLr~uit 106~ The select circui~ 106 responds to the tim-.
ing pulses provided ovex lines 110 a~d 111 to se~uentially apply a lo~ic one level to outputs 121, 122 and 123 in sequence. ;
~ ' AccordinglyD when output Q14 o~ the divider circui~ 92 becomes a :: logic one level after 128 seconds have elapsed during a write cycle, gates 118~120 are enabled in successive si~teen second periods as defined by ~he outpu~s of ~he selec~ circuit 106.

~: ' ' , , ~: . ' : . -.

~ 8 accordingly, during ~he firs~ sixteerl second period, mul~iple-xer circuit 103 will be enabled to gatQ t:he ~irst eight bits of the identification code to ~he dat~ latch clrcu1t 26. During the next sixteen second period, multiplexer circuit 10~ will be enabled by gate 119 to respond to the clock pulses provided on lines 112 114 to gate the next eight bits of the identiication number to the data latch circuit 26. Thereafter3 during the next sixteen second period, multipLexer circuit 105 is enabled by gate 120 to gate the las~ four bits of the identification da~a and the four bits which comprise ~he beginning of message code to the data latch cixcuit 26.
Data La~ch Circuit The data latch circuit 26 comprises a D type latch c:Lrcuit 130 and a retriggarable one shot circuit 131. The data latch circuit 130 may; for example, be a D-type latch such as the type 4013, commercially available froM RC~. The one shot circuit 131 may be the type 145~8 retriggerable monos table circuit, com-merc-Lally av~ilabl~ from Mororola, The data bits provided at the output of the multiplexer circu~t 25 at point 109 are extended to the latch circuit 130 over ~he retriggerable one shot circuit 131. Inasmuch as the logic levels at point 109 are not sustained for a full two second pcriod due to thP switching times of the multiplexer cir~uits 102-105~ the one shot cixcui~ 131 provides a continuous signal .
to the data input of the la~ch circuit 130 for ~he two sacond bit write period, The one~shot circ~it 131 is ~riggered by the leading edge of each positive going pulse prov~ded at output 109 of the;. multiplexer circuit 25. When a logic 0 level bit is provided at outpu~ 109, the one shot circuit 131 is not triggered, ., ~ ' ' ' ' and af ter lts time out, pxovides a lo~ic 0 input ~ the data la~cch circuit 130~
The latch circuit 130 rec~ives a clock pulse at a one second rate provided a~ output Q6 of the divider circuit 92 and is operable when enabled by the wri~e gate 42 during the 180 second time interval, whirh defines the write cycle~ to store each data bit provided at the multiplexer output 109 for a two second interval to provide continuous inputs to the phase incoder ~ -circuit 27.
Phase Enc~der Circuit ~ ~.:
The pha.se encoder circuit 27 comprises three NAND gates 141-143 and a time delay circuit 144 embodied as a latch circuit 145 which may be the type 4013 Data Latch, circuit commercially available from RGA . Gates 141 and 14~ have respective inputs 146 and 147 connec~ed to the true and fal3e outputs j respectively o~
the latch circuit 130. In addition, gates 141 and 142 have re~
spective inputs 148 and 149 connected to the true and false out- -pu~s respectively, of la~ch circuit 145. The outputs of gates ; 141 and 142 axe connected to inputs of ga~e 143 the outpu~ of : 20 which ~s ext ended to the record head driver circuit 18.
The latch circuit 145 provides a two second outpu~
Figure 10) delayed 1/2 second from the ~wo second ou~put of the ; clock signal supplied at ou~put Q7 o~ the counter 92 ~o assure ;~ that the state of data latch 130 has stabilized be~ore gates 141 ;~
and 142 are enabled to gate-the data to the recording circuitry ov~r the phase encoder circuit 27. The làtch circuit 145 has a data i~pUt con~ cted to the output Q7 of the divider circuit 92 which provldes a timing pu~se at a two second ra~e. Clock slgnals for the latch circuit 1~5 are provided at a one second rate by the timinp pulses prvvidecl ~t output ~6 of the divider circuit 92, Phase encocler circuit 27 is operable to write pahse encoded timing pulses on the ~ape ~t a two second rate to provide a time refexence for the event da~a. A log:ic 1 is written on the tape by recording a logic ) level pulse for the first half of each two second period and logic 1 level pulse for the last half o~ the period. A logic O is written by recording a logic 1 level for the first half o~ the two second bit write period and a logic O ~or the last half of the period. The zero crossover provided be each biphase sîgnal enables a two second clock pulse to be de-xived from the recorded dat~, including the timlng ~ulses and the message data permitting reconstruction of date and time informa-tion recorded on a single track~ It should be noted that upon playback, each phase encoded logic 1 is defined by a logic 1 level ollwoed hy a loglc O level, and each phase encoded logic O is de- ~ -fined by a logic O level follo~ed by a loglc 1 level. -Write Gate .... _ :
~ eerring to Figure 6~ there is shown a symbolic re-presentatio~ of the write gate 42 and the associated control logic circuits 43-45. The write gate 42 is compr.ised o a pair of NA~D gates 151 and 152 con~ected as a latch circuit having a set input 153, reset inputs 154 and 155, a true output 156 and ; a false output 157. The write latch 42 is set by the write gate .. j.. . .
enable decode circuit 43 in response to the detection o~ the cod-ing of the digit O or 5 as provided by the clock module 61. The write gate enable decode circuit 43 is comprised of NAND gates 161-163 whlch are operable to extend an enabling input to the set i~put 153 of ~he write gate 42 over ga~es 164-~65 of the control ~ 7logic ~
The wrlte gate 42 ls rese~ upon the detection by the write gate disable decode circuit 45 of the coding for a digit 3 or 8 provided by the clock module 61. The write gate disable decode circuit 45 is comprised of gates 171-173 which enable a ~urther NAND ga~e 174 of the control logic to apply a reset input 154 o~ the write gate 42..
When the write gate is set, the write gate 42 enables gate 181, whi.ch co~prises the select gate 35 to pass the time and date select signal provided at output Q13 of the divider circuit 92 to the select circuit 22 ~Figure 4). In addition, the false outpu~ 157 of the write gate 42 is connected to the reset input : of the data latch circuit 130 to enable the data latch circui~
130 whenever the wrlte gate 42 is set.
Referring to the write enable decode circuit 43, gate 161 has: inpu~s 161a-161d connected to respective output lines 30b, 30e~ 30f and 30g such that gate 16l is e~abled whenever the coding or the d~ O is provided by the clock module 61. Gate 162 has inputs 162a~162d connected to respective output lines 30b, 3W , 30f, and 3~g such that ga~e 162--is enabled whenever the coding for the digit 5 is provided by the clock module 61.
Gate 163 ~unctions as an OR gate to pass the output of gates 161 and 162 to an input 164a of gate 16~ which has second and third inputs 164b and 164c connec~ed to the ou~puts of inver~ers 169 and 1709 respectively3 which are co~nected to outputs of respec-tive gates 167 and 168. Gate 167 has inputs 167a-167c co~nected to output lines 30a, 30c and 30d, resp~ctively, and is enabled wheDever the codi~g for the digi~s a, 3, 5~ or 8 is provided by the clock mod~le 61. Gate 168 has an input 168a connected to -31~

..

~ 8 digit select line DSl and an input 168b connec~ed to the output of the select gate 35 to be enabled whenever the clock module 61 is operable in ~he time mode.
Considering the write gate disable decod~ circuit 45~
gate 171 has ~nputs 171a-171cl connected to outputs 30b, 30e, 30~, and 30g, respectively~ and is enabled whenever the coding for the digit 3 is p~ovided b~ the clock module 61. Gate 172 has inputs 172a-172d connected to output lines 30b, 30e, 30f and 30g, re-spectively, and is enabled whenever the coding for the digit 8 is provided by ~he clock module 61 Gate 173 functions as an OR
gate to gate the ou~puts of gates 171 and 172 to an input 174a ~ :
of gate 174 which has second and third inputs 174b and 174c con-nected to ~he ou~puts of inverters 169 and 170 a~d is enabled whenever gates 167 and 168 are enable~ in response to the coding ~ -for one of the digits 0,3,5,or 8 provided by the clock module 61 at the start of each write cycle. ~ -Re~et ~cui~
The reset circuit 46 comprises a discrete one-shot circuit comprised of a NA~ gate 191 and inver~ers 192 and 193.
: 20 The input of the rese~ circuit at the ~nput of inverter 192 is connected to the false output 157 of the wr1te gate 42. Timing ~lement~, including resistor R22 and capacitor C8 es~ablish the pulse width for the reset pulse, which may be 200 ns. The output o the reset circuit at the output of gate 191 is extended to the reset lnpu~ of the divider circu~t 92. A second input to the ; reset circuit 46 is provided by ~he hold off circuit 48 which en-ables the counter 92 ~ be reset in the event of a power loss for the time record circuit 15.

. ~

- ~ . . : . : . ~ : -HolcI Off Circuit The hold of~ circuit ~ i9 compri5e(l of ~ pair of ~ND
gates 195 and 196, connec~ecl for operation as a latch circuit 197. The hold of circuit 48 furtlI~r comprises a pulse generat-ing c~rcuit 194 comprised of inverters 198 and 199 and a timing circuit 200 including resistor R23 and capacitor C9. The set in-put 201 of the hvld off latch 197 1s connected to the output of inverter 199 which is also connected to a further reset input 155 of the write gate 42. In the event of a power loss, the timing circui~ 200 rese~s upGn reapplication of power to effect the gen-eration of a pulse which is exte~ded over inverters 198 and 199 to set the hold off latch 197 to reset the write gate 42. The hold off latch 197 is reset by gate 174, which is enabled hy th~ write gate clisable decoder circuit 45 when the clock module 61 provides an ou~put representing the codlng for a 3 or an 8.
The falsP. output of ~he hold off latch 197 at point 203 is conne-cted to an input 166b of gate 166 to preven~ the se~ting of the write gate 42 whenever the hold off latch 197 is set.
~eration of ~he Tlme Rerord Circuit Referring to!Figures llA~llC, ~here i5 shown represen-tations for the time~ date and identification n~m~er data~ rP-spectively, which is recorded on ~he tape when the write gate 42 is set to de~ine a give~ write time interval. The time, date and identification number data are shown in separate Figures lLA-llG~ respectively9 to simplif~ the drawings. However9 during a given record1ng interval, the recorded message is comprised of the da~a shown in Figures llA-llC. Th~ ~ the left hand por~
tion of Figure llA corresponds to the right hand portion of F~-gure llB9 and the left hand por~ion of Figure llB corresponds ~o : . . . ~ - .: , . .
- :

the righc hand porti on of :F:Lgur~ l:lC, Each o:~ the Figures lLQ~
llC should be re~d ~rom right to left as this corresponds ~o the order in wh~ch the cla~a is recorded on the tape, ancl 1~, ~he re-verse of the order in whLch the data :is ~layed back.
Referring to F:igure llA, by way o~ example, it is as-sumed that the recording is occurring at 8:10 A.M. The time At which the write gate 42 is set to enable ~he transfer of clata rom the digital clock 21 to the data latch circuit 26 ls indi-cated at ~he righ~ hand portion o~ Figure llA in line I. Line II represents clock pulses provided at a two second rate which corresponds to ~he wri~e time for each bi~ of the output data.
Lines III and IV represent the digital coding for the segment outputs appearing o~ output ll~es 30a-30g and the phase encoded data provided by the ph~se ancoder circuit 27, respectively.
Priox to ~he se~ting o the write gate 42, the phase encoder cir cuit 27 e~ects the writing of logic 0 bits on the tape, encoded as logic 1 and logic 0 levels, as shown in line IV of Figura llA.
When the wri~e gate 42 is enabled, and the data is supplied to the da~a 3.atch circuit 26 over the mul~iplexer circuit 25, the da~a 2~ la~ch circuit 26 con rols the phase encoder circui~ 27 to write each logic 1 level bi~ as a logic 0 level ollowed by a logic 1 level in a two second time period3 and each logic O level bit as a logic 1 level followed by a logic O level In a ~wo second period~
As shown in Figure lLA, during the first 16 seconds of the '~rite time" cycle~ the coding for the digit 0 is provided over output lines 30a-30g. Dring the next 16 second period, the coding for tha digi~ 1 is provided on ou~put lines 30a-30g. During the time :l~rom 32 -~8 seconds " the coding for the digit 8 is provided.

- ~ . . ' ' ~3~

Referring ~o Figure llB, which shows the date data by way of example, it is assumed the data recording is occurring on the 29~h day o~ April. Accordingly, the date in~oxmation which is recorded on the tap0 includes the coding for the digit 4 ~or the month, and the coding for the digits 2 and 9 corresponding to the tens a~d the units digits, respectively, of the day, such data being recorded during the '~rite date" cycle during the time ~rom 64 seconds ~o 128 seconds of the write cycle~
Referring to Figure llC~ by way of illustration~ it is assumed ~hat the identifica~ion code number to be recorded on the tape to identify the recording apparatus 10 is 867560. The binary coding or such number is shown at line III of F~gure llC.
The ide~tification code ls writ~en on the tape during the time from 128 seconds to 168 seconds o~ the write cycle Durin~ the time from 168 second~ to 176 seconds o the write period, the st~rt o~ message code, which is compri~ed o~ a logic 0 level æo:Llowed by three logic 1 levels, is written on the tape, and for the remainlng 4 second~ o the write cycle, logic 0 bits are en-coded and written o~ the tape. As shown in Figure llC, at ~he end o~ the 180 second write cycle, the ~rit~ gate 42 is disabled, and the pha~e encoder circuit 27 effects the writing of logic 1 and logic 0 Levels~ alter~ately on the tape, representing the coding ; ~oP logic 0, such encoded logic 0 bits be~ng recorded on the tape at two second ~n~ervals~ In the axemp~ary embodiment, the star~
code~ as ~ecorded, is shown to b~ comprised of a logic ~ level followed by thxee logic 1 levels. However9 it is appare~t that other combinations of bits may be employed as the start ~ode.
Referring now to Figures 4-69 the clock module 61 is normally opera~g in the time mode due to select ga~e 35,, and -35 - .

thus~ when the digit output of the cl:i.git~l elock 21 chanzes ~rom 9 to 10 minutes~ ~he dlgital cJ.ock module 61 provide~ the coding for the digit 0 ~n outputs a-g ~line III, Figure 11~ :lth out-puts a~ being logic 1 levels and outpu~ g being a logic 0 level so that line 30g is at logic 1 level. Such outputs are extended over the buffer amplifiers 74-80 to the output lines 30a-30g, and thus to the :inputs 102X0-102X6 of the multiplexer circuit 102. In addition, the lowest order digit, provided on digit se-lec~ line DSl i~ a~ a logic 1 level3 and accordingly, a logic 1 level is e~tended to input lOlX0 of multiplexer circuit 101 while logic 0 levels, provided on digit select lines DS2-DS4 are ex-tended to inputs 101X1-101X3 of the multiplexer circuit 101.
I~ response to the l~ogic 1 levels on output lines 30b, 30e, 30f and 30g, gake 161 of the write gate enable decode cir-cuit 43 is enabled, enabling gate 163 providing an enabling in-put at input 164a of gate 164. Also, gate 167 is enabled by the lc)gic 1 levels appearing on outpu~ lines 30a9 30c9 and 30d, pro-viding a logic 1 level input to gate 164 over input 164b thereof.
~ate 168 is also ena~led at this tLme by the logic 1 level pro-vided on digit select line DSl and the logic 1 level provided atthe output of gate 181 of the select gate circuit 35, which is disabled at this time by the write gate 42. Accordingly, gate 164 is enabled and, assuming that the hvld off la~ch 48 is reset, gate 166 ~s enabled to set the wri~e latch 42 Whe~ the write gate 42 is set~ the reset ~ircuit 46 is .
enabled to provide a 200 ns reset pulse to the divider circuit 92 9 allowing reset of all outputs Q6-Q14 of the divider circuit 92 to loglc 0.
Referring to ~he timing diagram shown in Figure 9, lines A-F show respective OUtp-ltS Q8 ~13 o~ the dlvider circuit g2; lines G-M show the ~imes at whic~- ou~put line,s 30a 30g a~e selected by the multiplexer circuit 102, and lines N-~ show the times digit select lines DSl~D54 are selected by the multiplexer circuit 101. As shown in Figure 9 at lines A-F, outputs Q8-Q13 ~re at logic 0 levels.
The logic 0 levels provided on output lines 110 and 111 (outputs Qll and Q12) enable the multiplexer circuit 101 to sel~
ect input 101XO (line N of ~iguxe 9) which is connected to digit select line DSl, to gate the logic 1 level signal on line DSl to the output lOlZ of the multiplexer 101, enabling gate 116 to provide an enabling signal for multiplPxer circuit 102. Since clock lines 112-114 ~vutputs Q8 Q10) are also at logic 0 levels, th~ multiplexer circuit 102 is e~abled to select input 102X0 at ~he tlme indicated in line G of Figure 9. Inpu~ 102~0 is connect- :
: ed to output line 30a, enabling the logic 1 level signal appear- :
: ing thereon to be gate~ to the output 109 of the multiplexer circuit 25, The retriggerabLe one-shot :ls enabl~d in response to the logic 1 level provided a~ output 109 to provide an inpu~ at : logic 1 level to the data la~ch circuit 130 which has been en-abled to receive da~a pulses in response to the setting of the write gate 42. Re~arring to Figure 10~ whan the divider circuit 92 ls resetj clock pulses provided at outputs Q6 and Q7 are at logic 0 levels ~lines A and B), the delay latch circuit 145 of the phase encoder cîrcuit 27 is set ~line C), and the data latch 130 is~reset ~line D). T~e first one second clock pulse sets the :; :
data latch 130 slnce the multiplexer output 109 is at logic 1 level ~line E~ and rese~s the deLay latch 145 s mce ~he two second , . . ..

~ 7 ~
clock pulse is a~ logic 0q Accordingly, ga~es 141 and 142 pro-vide logic 1 outputs, ancl gate 143 provides a logic 0 level out-put to effect the recording of :Loglc 0 on the tape.
The two second clock pulse provided at output Q7 of the divider circuit 92 enablss the delay latch circuit 145 to be set by the leading edge of the next one second clock pulse provided over output Q6, and since the data latch 130 is set, gate 141 provides a logic 0 output and gate 142 provide~ a loglc 1 output.
Thus, gate 143 is enabled to provide a logic 1 output to the time 10 - record head driver circuit 18. The p~ase encoded data; xepresen-ting the coding for the first bit of the ~ime data, is sh~wn in Figure llA at li~e IV.
Ater two seconds have elapsed~ which corresponds ~o the wri~e time :for the ~irst bit of the output word, tlm~ng out- . -put Q8 of the divider circuit 92 becomes a logic 1 level as shown in line A of figure 9. When output Q8 becomes a logic 1, : ~ whil~.outpu~s Q9-Q12 remain at logic 0, multiplexer circuit 102 : is enabled to selec~ inpu~ 102Xl which is connsc~ed to outpu~ line .
: 30b. As shown in line N of Figure 9, multiplexer circuit 101 continu~ to select input 101X0 for a 16 second period, and ~hus, ..
gate lI6 remains enabled for such time Accordingly, the signal o~ outpu~ line 30b is rou~ed to the output 109 9 triggering the one-shot circuit 131 to maintain the data latch 130 set for the next ~wo second period as shown in li~e D of Figure 10 S.ince at this time, the two second timing pulse at output Q7 is a logic 0 level, the delay latch 145 is reset, and gate 143 provides a logic 0 output to drive circuit 18. One second later, output Q7 agai~ becomes a logic 1 level, causing delay latch 145 to ~et, thereby enabling gate 143 to provide a logic 1 level to drive -3~-l7~
circuit 18.
Therea~er, inputs 102X2-102X6 are selected in sequence, snabling the remaining bits of the flrst output word to be written on the tape. Wh0n ~he input 102X0 is selected3 the logic O level on line 30 g is ext2nded to output 109 of multiplexer circuit 25.
Accordingly, one ~ shot circuit 131 is not retriggered and times out~ enabling the data latch 130 to be reset, permi~ing a logic 0 to be encoded by the phase encoder circult 27. Then input 102~7 is selected, and the additional logic 1 level bit is en-coded on the tape.
At the end o~ the firs~ 16 second interval, clock mo-dule 61 outputs a logic 1 level on digit select line DS2 and lo-~ic 0 levels on digit select lines DSl, DS3 and DS4. Also, at such time, ou~put ~11 of the divider 92 becomes logic 1 while output Ql2 of the divider circuit 92 remains a logic 0, enabling the multiplexer circuit 101 to select input 101~1 for extending thb logic 1 level on digit select line DS2 to the output lOlZ
: o~ the circuit 101, maintaining gate 1167 and thus the multiplexer ; circu~t 102 enabled. Also, at such time, the clock module 61 Z0 prov~des outpwts over output li~es 30a-30g, representing the coding for the tens digit of minutes, which in the present example is 1. Accordingly~ the timing pulses on lines 112~114 control the multiplexer circuit 102 to select the inputs 102X~-102X7 in sequ~nce ~o output the ~even bit code representing the coding for the digit 1, and the addltio~al logic l level bit or rou~ing such bits to the data latch cîrc~it 130 to control the phase en- :
coder circuit 27.
During ~he thirld and ~ourth 16 second intervals which compri~e the balance of ~he '~rite time" c~le, multiplexer cir~Y

.
.

cuit 101 is enabled to select inputs 301X2 and lOlX3 which corres-pond to digit select lines ~S3 ancl DS4 to ma:in~ain the multiplexer circuit 102 enabled. Also, the digital clock module 61 outputs the coding or the units digit for hours, 8 in the present ex-ample. The ~ens digit o~ hours, which is zero in the present example is suppressed by the cl.ock module 61.
At the end o~ the 64 second "wr;te time" interval, out-put Q13 o~ the divider circuit 92 becomes a logic 1 level, as indicated at line F in Figure 9, enablirLg the select gate 35, since the write gate 42 is set, providing a loglc 0 level over line 36 to the select circuit 22 causing transistor Ql to be cut-off and enabling ~ransistor Q2 to provlde an enabling input to the date inp~t of ~he clock module 61. Accordingly, during the next 64 second interval~ the time recording circuit is operable in the "write date" mode and the four digits representing the units and the tens digits for the month are provided by the di-gi~al clock module 613 each o~ the dig:its codings being provicled in successive 1~ second intervals of the '~rite date"cycle. As each o~ the owx digits are provided3 the code words are extend-~ ed over the multiplexer circuit 102 to the data latch circuit 26 which undex the control of the timing control circuit 23 which controls the ph~se encoder circuit 27 to provide the phase encoded data representing the month and date, as shown in Line IV Figur~ llB. The sequencing operation is similar to that for the '~rite time t1 cycle.
After an elapsed time of 128 seconds, that is, at the end o the '~rite date" cycle, output Ql4 of th2 divider circuit 92 becomes logic 1 level, inhibiting gate 116 over inverter 115 and providing an enabling input to gates 118-120 whieh are selec--~o - ..

7 ~
ively operable to enable respective Multiplexer c:ircuits 103-105.
At 128 seconds, outputs Qll and Q12 are both l.ogic a enabling the select circult 106 to provide a lo~ic 1 level at output 121 which effects the enabling of ga~e 118, in turn enabling multi~
plexer circuit 103 to gate the first 8 bits of ~he iden~ification code ~Flgure llC~ line III~ provided by the iden~ification source 29 to the outpu~ 109 of the multiplexer circuit 103. The inputs - 103X0-~03X7 of the multiplexer circuit 103 are selected in sequence in accordance with the timing pulses prov~ded on lines 112-114 b~ -outputs Q8~Q10 of the divider circuit 92.
As the first eight bits of the identification code areserially extended to the data la~ch circui~ 130, the da~a latch cixcuit 130 controls the phase encoder circuit 27 to provide the phase encoded data as shown in line IV of Figure llC~
After the end of the first 16 second portion of the '~xite identi~ication code" cycle, the select circuit 106 provides a loglc 1 level output at outp~t 122, a~ logic 0 levels on out pUtS 121 and 12~5 which enables gate 119 and permits gate ll8 to be di~abled. Accordingly, the multiplaxer circuit 104 is enabled to gate the next 8 bits of the identifica~lon code to the data Latch circui~ 130 to control ~he phase encoder circ.uit 27 for ~writing the e~coded bits on t he tape.
A~ter 32 seconds have elapsed~ the select circuit 106 provides a logic 1 level on outpu~ 123, while outputs 121 and 122 are at logic 0 levels, disabling gate 119 and enabling gate 120 to enable multiplexer circuit 105 for routing the remaining four bits of the identiication code and the four start of message . :~
bits to the data latch cirlcui~ 263 which controls the phase en~
coder clrcuit 27 to write the information on the tape.

.. . .
, . , :, . , . , ~ . . ..

Since no addi~ional clata is provided or the ollor.~ing seconds, the one shot 131 is not triggered and the data latch 130 is ~hus reset with the next clock pulse, enabling enco~ed logic 0 bits to be written on the tape for the next 4 seconds.
Thereafter, clock pulses at cL two second rate are written on the tape ~or the two minute interval before the next write cycle is initiated.
It is pointed out that when the divider circuit 92 reaches a count of 128 seconds, the clock module 61 is rendered operable in the time mode ~or a further 64 second period. Thus, at the end of the write cycle9 the clock module 61 is operating in the time mude, providing the coding for the digit 3 which is ex~ended to the w~ite gate disable decoder circuit 45. The w~ te gate disable decode circuit 45 is thus operable to effect the re ; set of the write gate 42, ~hich in hibits the data latch circuit 130 to prevent the writing of further dcLta on the tape for the next two minute ~Lterval. During such time, logic 0 bits are en-coded on ~he tap~
In the event of a loss of power during the write cycle, 20~ the clock module 61 continues to be er.Lergized by the battery supply ~5~. However, the wr~te gate 42 is disabled and the hold off Iatch 197 maintains the write gate disabled for a predeter-, mined time af~er the power is res~ored.
Reerring ~o Figure llD, assuming there is a powerfailure for our seconds during the '~rite ~ime" interval, then the wri~e gate 42 is disabled as i~dicated in line 1 o~ Figure llD.
When power is restored, the charglng of capacitor C9 of the timi-ng circuit 200 CFigwre 6) of the hold of~ circuit 48 oauses a pulse to be provided over inverters 198 and 199 which eects the -~2-~'.

.
-setting o:E the holcl latch 197, the reset of the wrlte ~ate ~2 and the reset of the divider clrcuit 92 over gate 191 of the reset circuit 48.
When the hold o.~ latch 197 is set, gate 166 is disabled, thereby preventing the setting of the write gate 42. The hold off la~ch 197 i5 reset when gate 16~ i5 enabled in response to the enabling of gate 171 or 173 when the cod.ing for the digit 3 ox ~ is provided by the clock module 61. At such time~ gate 166 is enabled to follow the output of gate 164 over inverter 165 to permit the write gate 42 to be set the next time the coding or the digit 0 or 5 is provided by the clock module 61.
As inclicated above, in the event of a po~1er loss~ the clock module 51 is energized by the battery source 65, and accord-l.ngly, upon restora~ion o powar the time and date are correct.
Thus~ adjustme~t of the digital clock 21 is required only on start up through the use of the manual t~ne set circuit 24 shown in Figure 7.
Montha ~re se~ by advancing ~he days to the last day of the indicated month, observing the outpltt of the digital clock ~1 on the clisplay unit 28 ~Figure 8), and advancing the hours to 23 hour~ and advancing the m~nutes to 59 minutes after which one more advance o.~ the minutes will cause the month to advance 1, tha~ is, into the next month. This sequen~e is repeated until ~ .
such time as the required mon~h has been reached by advancing on .. -a one month basis. Depression of advance switch SW5 when day select switch SW3 is operated causes days to advance at a one .
second rate. HOurs are set by depressing the advance switch SW5 when the select s~itch SW2 is operated causes days to advance a~
a one second rate. Mi.nutec are advanced upon depression of t~
-~3-. . . . - - . . . . .. . . .. . .

advance switch S~5 when the minutes select swi~ch SWl i5 operated.
To insure that time mode will be functional at 2 and 5 minute in-~ervals, ~he advance switch SW5 rnust be depre.ssed abouk 30 seconds a~ter the display un;t 28 reads b~ minutes, or a time ending in

4, 14~ 24, 34, 44, 54 minutes~ Then , when minutes is to be detected, the system will be in the time mode.

~ ;' ' ' : .
':

,: :
" ..

., .
; : ~ - :, . ,

Claims

The embodiments of the invention in which an ex-clusive property or privilege is claimed are defined as follows:

1. In a data recording apparatus having data recording means for recording event data provided by a data source on a multitrack recording medium, a time reference recording means for recording a time reference for said event data on said recording medium comprising timing means for providing timing pulses at a predetermined rate, encoder means controlled by said timing pulses to generate time refer-ence signals at said predetermined rate for recording on one track of said recording medium to provide a continuous time reference for said event data, time reference data source means for supplying coded data representing time of day and calendar date information to said encoder means, and control means for periodically enabling said encoder means to respond to said coded data to encode said time reference signals with said coded data to provide modified time reference signals for recording on said one trace of said recording medium as a portion of said continuous time reference.

2. A data recording apparatus as set forth in Claim 1 wherein the coded data representing the time of day information indicate the minute and hour at which the time reference data is recorded and the coded data representing the calendar date information indicate the day and month on which the time reference data is recorded,

3. A data recording apparatus as set forth in Claim 1 which includes identification data source means for providing to said encoder means further coded data repre-senting an identification number for said apparatus, said control means periodically enabling said encoder means to be responsive to said further coded data to provide signals representing said identification number for recording on said recording medium.

4. A data recording apparatus as set forth in Claim 3 wherein said recording medium comprises a magnetic tape and wherein said signals representing said time and date information and said signals representing said identi-fication number are recorded on a common track of said magnetic tape.

5. A data recording apparatus as set forth in Claim 3 wherein said time reference recording means is operable to effect the recording of a start of message code on said recording medium after said time and date information and said identification number have been recorded on said recording medium,

6. A data recording apparatus as set forth in Claim 1 wherein said time reference source means comprises digital clock means operable in a first mode to provide a first plurality of code words representing the coding for the minute and hour that the time reference is being recorded and operable in a second mode to provide a second plurality of code words representing the day and month that the time reference is being recorded.

7. A data recording apparatus as set forth in Claim 6 wherein said control means includes select means operable to normally maintain said digital clock means operable in said first mode and means enabled in response to code words provided while said digital clock means is operable in said first mode to permit said time of day information to be recorded on said recording medium during a first time interval, said select means periodically enabling said digital clock means to be operable in said second mode to permit said calendar date information to be recorded on said recording medium during a second time interval,

8. A data recording apparatus as set forth in claim 1 which further comprises means for normally providing power to said time reference data source means from a source of power for said data recording means, and means for powering said time reference data source means indepen-dently of said data recording means at least during a time of interruption of power from said power source for said data recording means.

9. A data recording apparatus as set forth in Claim 8, wherein said time reference data source means comprises digital clock means, and a crystal controlled oscillator for providing drive signals for said digital clock means, and means for connecting a battery to said oscillator and said digital clock means to enable said os-cillator to continue to provide drive signals for said digital clock means during a time of interruption of power from said power source for said data recording means.

10. In a data recording apparatus having event data recording means for recording event data which is provided periodically during a given time interval by a data source, on a first track of a recording medium which is moved continuously during said time interval, a time reference recording means for recording a time reference for said event data on a second track of said recording medium, said time reference recording means comprising time reference data source means operable to provide coded data representing time of day information and calendar date information, and output means including timing means responsive to said time reference data source means for continuously providing timing signals, and encoder means responsive to said timing signals and said coded data to generate time reference signals, including signals coded to represent said time of day and calendar date information, for recording on said second track of said recording medium as a continuous time reference for said event data.

11. A data recording apparatus as set forth in Claim 10 wherein said output means further comprises control means for defining recording intervals for recording said time of day and calendar date information on said recording medium and hold off means operable to disable said control means to inhibit the recording of said time of day and calendar date information in the event of a momentary loss of power to said recording apparatus during a recording interval, and for reenabling said control means to permit recording during the recording interval next following the interval in which the momentary power loss occurred.

12. A data recording apparatus as set forth in Claim 10 wherein said output means further comprises control means for defining recording intervals for recording said time of day and calendar date information on said recording medium, and hold off means operable to inhibit said control means until the end of a recording interval in which power is first applied during a startup condition.

13. In a multitrack data recording apparatus having at least first and second recording head means, event data recording means for providing drive signals for said first recording head means to effect the recording of event data provided by a data source on one track of a magnetic tape, a time reference recording means for recording a time reference for said event data on said tape during predeter-mined recording intervals, said time reference recording means comprising time reference data source means including digital clock means operable in a first mode to provide code words representing time information, said digital clock means being operable in a second mode to provide code words representing date information, timing control means for providing timing signals for controlling said digital clock means to select the operating mode for said digital clock means, and output means including enabling decoder means responsive to a preselected one of the code words which is provided by said digital clock means at the start of a recording interval to enable said output means to be controlled by said timing control means to receive the code words provided by said digital clock means during said recording interval in a predetermined sequence and to provide drive signals for one of said recording head means to effect the recording of both said time and date information on one of the tracks of said magnetic tape.

14. A data recording apparatus as set forth in Claim 13 wherein said digital clock means when operable in said first mode provides a first plurality of code words in a sequence representing the coding for the minute and hour that the time reference is being recorded, and when operable in said second mode provides a second plurality of code words in a sequence representing the coding for the day and month that the time reference is being recorded.

15. A data recording apparatus as set forth in Claim 14 wherein said output means further comprises dis-abling decoder means responsive to a code word provided at the end of each recording interval to prevent said output means from responding to code words provided during the time between successive recording intervals.

16. A data recording apparatus as set forth in Claim 15 wherein said control means includes means responsive to an output of said digital clock means and said timing signals to enable said output means only when said digital clock means is operable in said first mode at the start of said recording interval.

17. A data recording apparatus as set forth in Claim 15 wherein said enabling decoder means and said disabling decoder means respond to code words which represent the unit digit for minutes.

18. A data recording apparatus as set forth in Claim 15 wherein each of said code words comprise a multibit word which is provided at parallel outputs of said digital clock means, said output means including phase encoder means operable when enabled to respond to the bits of said code words to provide phase encoded drive signals representing said code words, and parallel-to-serial converter means responsive to further timing signals provided by said timing control means to extend the bits of each code word to said phase encoder means in sequence as each code word is provided.

19. In a multitrack data recording apparatus in-cluding event recording means for recording event data provided by a data source on one track of a magnetic tape, a time reference recording means for recording a time reference for said event data on said tape, said time recording means com-prising time reference data source means including digital clock means operable in a first mode to provide multibit code words representing time information, said digital clock means being operable in a second mode to provide miltibit code words representing date information, timing control means for providing timing signals for controlling said digital clock means to select the operating mode for said digital clock means, and output means including phase encoder means operable during predetermined recording intervals to respond to the bits of said words to provide phase encoded signals at a predetermined rate which represent the bits of said code words for recording on said tape, said phase encoder means being controlled by said timing control means during time intervals between successive recording intervals to provide further phase encoded recording signals at said predeterminedrate for recording on said tape,

20. A data recording apparatus as set forth in Claim 19 wherein said phase encoder means includes data storage means responsive to output timing signals provided by said timing control means for storing each bit in sequence, a phase encoder circuit operable when enabled to provide a phase encoded drive signal corresponding to each bit, and delay means responsive to said output timing signals to enable said phase encoder circuit at a predetermined time after each bit is stored in said data storage means.

21. A data recording apparatus as set forth in Claim 19 wherein said output means includes hold off means for inhibiting said phase encoder means until the end of a recording interval during which a momentary power loss occurs.

22. A data recording apparatus as set forth in Claim 19 which includes identification data source means for providing a further multibit code word which represents an identification number for said apparatus, and means responsive to further timing signals provided by said timing control means to enable the bits of said further code word to be extended to said phase encoder means during each recording interval

23. A data recording apparatus as set forth in Claim 22 wherein said time recording means provides drive signals for said second recording head means to enable the code words representing said time and date information and said identification number to be recorded on a second track of said magnetic tape.

24. A data recording apparatus as set forth in Claim 22 wherein said timing control means is operable to define first, second and third time periods within each recording interval, said time of day information being re-corded on said tape during said first time period, said calendar date information being recorded on said tape during said second time period, and said identification number being recorded on said tape during said third time period.

25. A data recording apparatus as set forth in Claim 19 which includes a mulit-digit segmented light emitting diode display means which is controlled by the code words provided by said digital clock means, the bits of said code words providing the binary coding for each digit of said time of day and calendar date information to permit the current time and date information to be displayed by said display means,

26. A data recording apparatus as set forth in claim 19 which includes time reference pulse generating means operable to provide time reference pulses at predetermined intervals, and control means for preventing the code words provided by said digital clock means from being extended to said phase encoder means and for enabling said phase encoder means to provide signals representing said time reference pulses for recording on said magnetic tape,

27. In a data recording apparatus having data recording means for recording event data provided by a data source on a recording medium, a time reference recording means for recording a time reference for said event data on said re-cording medium comprising pulse generating means for providing timing pulses at a predetermined rate, phase encoder means op-erable during a first time interval to be responsive to each of said time pulses to provide a biphase signal including first and second signals at first and second logic levels at said predetermined rate to permit said time reference to be derived from said biphase signal, and time reference data source means for providing a plurality of multibit data words representing time of day and calendar date information, said phase encoder means being operable during a second time interval to be responsive to said timing pulses and said data words to provide further biphase signals including a biphase signal corresponding to each bit of each of said data words, each of said further biphase signals including first and second signals at first and second logic levels in a sequence representing the coding for the corresponding bit to permit said time reference to be derived from said further biphase signals, and means for recording said biphase signals on said recording medium.

28. A data recording apparatus as set forth in Claim 23 wherein said time recording means effects the recording of signals representing the complement of the bits of the code words representing the time and date information and the identification number on a further track of said magnetic tape.