CA1164098A - Billing recorder with non-volatile solid state memory - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
A billing recorder for providing a record of customer usage of electricity has a controller which may include a microprocessor for receiving and processing pulses from an electric meter. Data from one or more input channels is temporarily stored in random access memory by the controller in data words representative of energy consumed in predetermined time ("demand") intervals. The accumulated measurement ("event") data and time reference data are transferred to a non-volatile, solid state memory at the end of rel-atively long collection periods which comprise a number of demand intervals.
The solid state preferably is energized by the controller only during data transfers. The entire memory module is removable for processing at a central location, and it is replaced with a new one when it is removed. During mem-ory replacement, which may occur at most times with minor exception, the processor prepares a special Removal Record and transfers that record to pre-determined locations on the memory module being removed. The processor also prepares a special Insertion Record for the new module. The cumulative counts recorded on these special records as well as the normal records estab-lish reliable data continuity. A field test enables testing of the meter, data inputs and processing circuitry in the field. Further, the identifica-tion data (I.D.) may be set on the recorder in the field after installation or replacement. Provisions are made for incorporating various options such as Daylight Savings Time, one or two input channels and operation on 50 or 60 Hz. line frequency.

Description

~i6~8 Back~round of the Invent ~n The present invention relates ~ rec~:c ng apparatus for recording measured event data a'ong ~;i-h a time reference for the event data; and more particularly to a recorder of the type used by eleetrical utilities to record energy consumption by customers. The recorder includes non-volatile memory providing permanent storage for usage (i.e. event) data along ~-ith time reference da.a and which can be removed at the end of a billing period for remote tabulation or load analysis and replaced ~th an unrecorded memory for the next billing period.

Billing or survey recorders are used by elec-trical utility companies for recording the event data provided by an electric21 meter which indicates t~e amount of energy used b~ a consumer. The billing recorder accumulates data for a period of time called a rePd or ~illing period, typically a month long,and it also stores time signals or "marks", ge~erated by ~he billing recorder.
A time mark is simply a signal recorded at a predetermined interval (called "demand" periods) during which the associated event data occurred. That is, the dista~ce be~ween time marks on the tape define a predetermined time period, assuming the tape speet is constant and the same for both recording and playback. Demand periods conventionally are 5, 15, 30 or 60 minutes.

The event data and ;he time marks of con~er.tional recorders are typicallv recorded on magne~ic ta~e in a car~ridge to allow processing or analvsis of the da;a at a ~ 8 central transla~ion center ~Ihich is remote from the point of service. The recorded data provides .ime marks and event data pulses for customer billing and ioad analysis, bu~ it does not provide data representative of a particular start time or the source (recorder) from which it came.
Start and stop times, customer identification such as meter or recorder number (I.D.), and beginning and end meter register readings are all recorded in writing by the exchange personnel, thereby leaving considerable room for human error.
When such error does occur, any loss must ~e suffered by the utility, not the customer.

Most.billing recorders in use today-employ m2gnetic tape as the storage medium, even though ~.agnetic t2pe has temperature and humid'ity limitations which make it less reliable as a storage medium than is desired in the demanding environment of use by a utility. The tape must be advanced past the record head continuously and at a precise speed during recording. Accordingly, a complex mechanical tape drive system is required to insure prope~
operation at all environmental specifications. The requirement of drive motor,s for advancing the tape adds considerable cost and limits miniaturization of the unit.
Also, peri~dic servicing is required to maintain the recording mechanism drive elements, battery carryover system, and to periodically clean the recording head.

It will be appreciated that such recoIders are required to operate in a wide range O r te~.peratures (typ~ Ca1 -20 C. to ~5c C.), due to the worst cases of heat and cold 4~8 they are l.Kely to encounter over tne lar~e g~gra~hical area h;ch a given model is marketed.
A further consideration affecting cost, reliability and performance is that billing recorders employed for record ng data representing electrical energy usage are occasionally subjected to power interruptions. In recent years, there has been a trend to employ power outage circuits which provide transfer to an auxilary power source, such as a battery during intervals of primary power loss. It is evident that maintaining the drive to the tape advance motors during primary power loss results in a heavy drain on the battery, thereby limiting the carryover time for which recording can be continued. This is particularly disadvantageous in cold climates.
Summary of the Invention One aspect of the present invention is directed to data recording apparatus for providing a record of event measurement data from at least one data source comprising:
input means for receiving data signals representing said event measurement data; timing means for generating digital signals representative of real time; controller means for receiving said data signals and for generating data word signals representative of the quantity of data signals received during a predetermined time interval; first memory means for storing real time signals defining said intervals and said data word signals associated with said intervals;
and second memory means comprising non-volatile solid state memory means and memory control circuit means responsive to said controller means for transferring said real time signals and said data word signals accumulated in said first memory 1~64~8 means to said non-volatile memory means for s~oring iie -C~l~;e in predetermined relation.
Anothe, aspect of the present invention is directed to data recording apparatus for providing a record of event measurement data from a data source comprising: input means for receiving data signals from said source representing said event measurement data; controller means for receiving said data signals and for generating data words representative of the number of data signals received from said source during a given interval of time; non-volatile solid state signal storage means for storing said data words; energizing means connected to a source of power for deriving power signals for selectively energizing said signal storage means; said controller means including timing means for generating timing signals indicating writing intervals during which the data words processed by said controller means are stored in said signal storage means; and power switching means responsive to said controller means for energizing said signal storage means only during writing intervals.
A preferred embodiment of the present invention provides a billing recorder which includes a non-volatile, solid-state magnetic memory, such as magnetic bubble memory, for storing event data representative of electrical energy consumption measured by an electric utility meter. Solid state memory has the significant advantage that energy need not be spent on mechanical motion of the storage medium; and bubble memories are advantageous because the data is not lost if power is lost. A controller, including data processing circuits receives pulses generated by a pulse initiato;
associated with the electric meter and generates coded event i164Q~8 data words represen.ing ~he !~U!I~De~ e~r ~lent ~ i e~ measurement) pulses received durir~3 ~ edetermined demand intervals. The data, along with time reference data is transferred to the solid state memory at the end of a pe~iod called a "collection"
period, which may include a number of demand intervals.
During a collection period, the controller temporarily stores the event data in random access memory. At predetermined clock times marking the end of a collection period, such as every four hours, the controller transfers the event data (i.e. quantized measurement data for all intervening demand intervals comprising a collection period) to the bubble memory which serves as a permanent data storage for the event data. Time reference data is generated by the controller, and it is transferred to the bubble memory at the same time as, and in association with, the event data for defining the period over which the event data was obtained. To conserve memory, the time reference data is stored only once for a number of demand intervals, and the quantized event data is stored in predetermined memory locations associated with respective demand intervals so that when event data is recovered from known storage locations, it can readily be determined with which demand interval the recovered event data is associated.
For example, for a "normal" record (i.e. separate provisions are made for insertion and removal of the module, as will be discussed), encoded time reference data identifying only the beginning of the collection period is generated and stored. A
collection period is thus the time between transfers of event and time reference data temporarily stored in random access memory in the controller before being transferred to the solid state memory for more permanent storage.

1164~8 The state of tne art in bubble ~emory manu-facture ~s such that a separate ~emory, called a "mask"
memory cr mask ROM (read only memo-y), is associated with each bubble me~ory to indicate which minor l~ops are not available for use due to failure to operate or meet performance specifications. For example, a memory may have 157 or so minor loops and only 144 o~ these are required because one `'page" of memory is 144 bits (18 bytes of 8 bits each). ~urther, each memory normally has associated with it a resistor for compensating for temperature varia-tions in the write current. The mask ROM and com?ensation resistor associated wqth each memory may be provided by the manufacturer; and in any case, since they are associated with a particular memory they are packaged with the memory in what is referred to as the memory module.

The bubble memory module is mounted on a remov-able memory card which facilitates removal of the bubble memory from the recorder apparatus at the end of a billing period, and the insertion of a new, erased bubble memory card. All of the recorded memories are then taken to a translation center for.further processing or the recorded information. Each of the memory modules is provided with a visual indicator to indic2te to exchange pe sonnel whether the memor-~ is erased or recorded.

The con~roller may include a microprocessor including a Central Processor Unit (CPU), Re2d Ollly Me~,orv (ROM), and Random Access I~Ie~ory (RAM), together wi;h associated buses and in,erface circuitry. A device is 1~64~8 associated ~ith the memory card to signal to the system tllat the memoly module is going to be replaced. In the illustrated embodiment, this device takes the form of a mechanical latch which locks the memory card in place in one position and permits its removal in another position.
Other sensing mechanisms may equally well be employed, but it is preferred that some action be required on the part of exchange personnel, in the form of mechanical motion or the like, to permit a short time delay between actuation of the device prior to removal to unlock the memory module or per-mit access to it, and the actual removal of the memory module. Actuation of the device to the removal position signals the microprocessor that removal is imminent, and the microprocessor prepares a special Removal Record in Random Access Memory and transfers this data along with the event data for the partial collection period up to actual removal to predetermined locations in the bubble memory.
After the new memory module is inserted in the recorder and the exchange person actuates the device to the operative position, the microprocessor prepares a special Insertion Record which is normally transferred to the bubble memory at the end of the current collection period. These special Removal and Insertion Records contain the time and date of insertion or removal, an identifier number permitting the utility to identify the recorder, and the event data for the partial collection period prior to removal of following insertion, as the case may be.
Further, each record (Insertion, Removal or Normal) contains a total count (called a "running total") of measured events for each collection period. That is, the total co~mt for all demand intervals for a collection period is added to the previous running total and stored as an integral part of the new record for that collection period.
In the case of two input channels, the running totals are stored in alternate records for each channel. The Insertion and Removal Records include these running totals, but in addition, they include total counts of larger magnitude (called "Insertion Total" and "Removal Total" respectively) for each channel which is representative of cumulative event data for collection periods at the time of replacement of a memory module. These total counts establish continuity of data from one memory module to another without loss of data.
When a memory card is to be removed before the end of a full collection period, the operator has to move a mechanical latch to the unloaded position before the memory card OT module can be removed. The unlatching operation is sensed by the microprocessor which then prepares the Removal Record for the partial period up to that time, and stores it in the bubble memory in the brief period before the card is removed. A visual indicator mounted in the memory module indicates whether the memory module is erased or recorded.
Another aspect of system design to be considered is operation of the bubble memory at elevated temperatures.
This can be a limitation because a manufacturer's upper temperature operating specification for a bubble memory system manu~actured according to available technology is about 70 C. If the bubble memory is operated continuously, 1~6~8 ~he temperature rise due to applied power alone is 20 C~, thereby limiting the environmental temperature to 50 C.
The present invention energizes the bubble memory only during the access time between collection periods, accumulating data in the Random Access Memory of the microprocessor for the complete collection period and assembling it in a predetermined format for storage in the bubble memory. This is considered an important advantage of the present invention because for collection periods of four hours, the average temperature rise of the bubble memory is less than 1 C.
This has been found to greatly relax the environmental stress on the bubble memory module, and as indicated above, a wide range of operating temperatures is important in the particular application with which the present invention is primarily concerned. Energizing the memory module only during access time also conserves power during power outages when conservation is important. By using CMOS technology in the controller, microprocessor and logic circuitry, carryover time can be extended substantially over prior magnetic type recorders which power the tape drive continuously.
Description of the Drawings FIG. l is a functional block diagram of a system incorporating the present invention;
FIG. 2 is a block diagram of a magnetic bubble memory for the system shown in FIG. l;
FIG. 3 is a diagrammatic representation of a removable memory card used in the billing recorder;

--lo--~164~8 FIG. 4 is a block diagram or a sy~t~n whi~h permits readout of the memory data by way o~ a communication link;
FIG. 5 is a diagrammatic front view of a recorder according to the invention; and FIG. 6 is a timing diagram illustrating the power fail modes.

DESCRIPTION OF A PREFERRED EMBODIMENT

Referring to FIG. 1, the billing recorder provided by the present invention records quantized measurement or "event" data provided by an electric utility meter which measures electrical energy consumption. Each pulse from the meter represents the consumption of a predetermined amount of energy or reactive power. At periodic billing intervals, typically a month, the event data recorded is processed at a translation center for billing the customer or to provide load analysis data. The recorder may be a multi-channel recorder; and in the exemplary embodiment the recorder is illustrated as a two-channel system which receives measurements data from two sources over separate data channels A and B.
Briefly, the event data is fed to the recorder circuits over two data channels A and B (which may be separate sources or two different quantities from the same source), and stored in a non-volatile solid state memory 23, such as a magnetic bubble memory, under the control of a controller which includes a microprocessor 11. Alter-natively, the data from two sources may be totalized before 4~
preparation of the record to be stored~ and thell stored in a totalized format. The controller processes the incoming data b~ accumulating it in predetermined time intervals called "demand" intervals prior to storage in the bubble memory 23 and controls the writing of the processed data into the memory 23.
Referring to Figure l the microprocessor system 11 includes a central processing unit (CPU) 16, a read only memory (ROM) 17, the random access memory lS, a time refer-ence generator 13, and an input/output (I/O) interface 19.
The CPU 16, which may be a Type CDP1802 Microprocessor manufactured by RCA, Inc. which uses CMOS circuits to conserve power, processes the event data pulses received from the input/output interface 19 via data bus 51 and stores the processed data in the RAM 1~ for each demand interval over a complete collection period before writing it in the magnetic bubble memory 23. The ROM 17 stores the control instructions for the CPU 16.
The event data supplied to the reaction circuits is coupled over the data channels A, B, C and D (which are latches) in the form of pulses generated by conventional pulse initiator devices (not shown), one for each channel.
The illustrated embodiment may accommodate one or two sep-arate input channels, such as A and B, designated 19A and 19B, at the option of the customer. In addition, if de-sired, additional channels l9C and l9D may be provided for and totalized respectively with l9A and l9B. The initiators may be of the type sold by Sangamo Weston~ Inc., under the designation SPI. Each level change at the output of the initiator represents the consumption of a predeter~ined ~ ~6 ~'f~

quantity of electrical energy. This train of pulses i.; fed to the controller via input/output circuit 19.

The incoming data is processed by the micro-processor which accumulatesth~ quantized data in predeter-mined demand intervals and proYides temporary storage in a Random Access Memory (RAM) 18 for a fixed number of de~and inter~als (it could be any number, one or more) which com.prise a collection period. During this time, the microprocessor prepares the event data nd time refer-ence and other information, which will be described, in a format for recording; and the bubble memory is not energized.
The bubble memory is energized only as necessary for writing data at the end of a collection period. Such write times are referred to as access times:

The controller includes a digital clock/calenda~
which provides time reference information for defining the demand intervals in Teal time. The controller stores date and time inform~tion representative of the be~inning of a collection period. For the two-channel recorder illus-trated, the microprocessor accumulates the pulses trans-mitted over each data channel for demand intervals of fifteen minutes duration for a collection period of four hours; and generates data words representin~ the number of pulses accumulated for each channel for each of the sixteen demand inter~als of a collection period.

For a "norm~l" collection period (i.e. one in which there is no power outage or no insertion or removal of a memory module), these data words are formatted ~164~8 together with time reference data (month, day and hour) ancl a running total count. The normal record data is transferred fr~m the R~l 18 to the bubble memory at the end of each collection period during the access time.

To conserve storage space in the bubble memory, time reference data is not stored for identifying each demænd intervali rather, theevent data is formatted by the microprocessor such that the event data for successive demand intervals is assi~ned to and stored in predeter-mined memory locations. If additional memory space is available, of course, or if it is otherwise found to be desirable, additional time reference data may be stored for each normal record. Twelve bits of memory (4095 resolution) are allocated for each demand interval per channel. This is one and one-half bytes. In the case of a two-channel recorder, the event data for one demand interval for Channel ~ is followed for the event data for ~he same demand interval for channel A.

In addition to the normal record data described ~boYe, the microprocessor p~epares a sep~rate Remo~al ~ecord for storage in predetermined locations of the bubble memory when it receives an indication from the exchange personnel that a memory module is being replaced. ~urther, after an erased memory module is inserted, the micro-processor prepares a special Insertion Record ~hich is recorded at the beginning of the newly inserted bubble memory. Both of these records will be explained in further detail below.

The bubble memory 23 of this exen~llaly embodiment is capable of storing data accumula~ed over a period of approximately thirty-five days ~i.e. 213 4-hour collection periods). The bubble memory module is mounted on a remov-able card, represented by the dashed line 24, in Figure 2, to facilitate replacement of the "recorded" memory module with an erased (zeroed) memory module at the end of each billing period. After removal, the recorded memory is transported to a translation center where the data is trans-lated. The memory is then preferably erased for reuse, al-though this is not absolutely necessary since the micropro-cessor could have an erase subroutine before writing.
Referring to Figure 3, the memory card or module 24 contains the bubble me ry itself, designated 23, a Read Only Memory 45 which contains the information identifying usable minor loops, a memory readout circuit 46 which may include a sense amplifier, and the temperature-compensating write resistor explained above. The card includes printed circuit conductors which provide the necessary interconnec-tions between the elements of the bubble memory card and terminals 24A of an edge connector 24B which is insertable into a receptacle 24C (see Figure 5) on the front of the billing recorder unit.
A device generally designated 49 is used to signal the microprocessor that the recorded memory module is going to be removed and an erased module inserted. This defines the end of a collection period. Preferably the device 49 requires some action by the operator to be accomplished a short time before actual removal. This delay may be as short as 100 milliseconds, and the purpose is to give t~ mlcroprocessor su~ficient time to prepare the Remo~al Record and transfer it to the ~emory module before actual removal. In the form illustrated, the de~ice 49 includes a handle 49A which is rotatable between a locking position shown in solid line which prevents removal of the m~dule 24, and a removal position shown in dashed line which permits removal of the module. The handle 49A is mounted on a shaft 49B which contains a cam 4gC. In the locking position, the cam 49C engages a flrst contact 49E and may p~ovide a ground for that contact. When the handle 49A is moved to the remo~al position, the microprocessor prepares the Removal Record and transfers it to the memory module 23.
Wnen the new m~dule is inserted and the handle 49A is moved to the locking position, the microprocessor senses this signal and prepares an Insertion Record and transfers th2t record to a predetermined location in the newly inserted memory (preferably, the first four pages thereof, as will be described~.

Devices other than the locking handle 49A could equa~ly well be employed, for example, a cover or lid pivotally mounted to the face of the recorder unit which would be required to be opened before remo~al of the module could also be used. It is not necessary that it be directly associated with and lock the module in p'ace, but it is believed that such a device would minimize error on the part of the replacement personnel, which could c~use loss of data.

~164~8 ~ o further minimize error, the memory module is provided with a visual indicator such as thc~ shown at 47 in FIG. 3 for indicatin~ whether or not a particular memory mc,dule is recorded or erased. Such devices are commercially available and may comprise a magne~ic bi-stable element ~hich~ if magnetized in one polarity will exhibit a first color and, if magnetized in the opposite polarity will generate a second, easily distinguishable color. This may be accomplished by transmitting the write current in one direction in a loop or coil associa-ted with the indicator 47 to generate the first color during insertion, and by transmitting the erase current throu~,h the coil in the opposite direction, thereby ~enerating the second color, upon erasing. Alternatively, a mechanical indicator responsive to being inserted in the recorder to give one visual indication (of recorded data) and responsive to being inserted in the reader to give a second visual indication of being erased, may be used.
The Re~oval Record which is recorded just prior to the time the recorded memory module is removed and after operator actuation of the device 49, includes time reference data representing the mon~h,-daj, hour and minute of module removal as well as partial period event data. The event data is stored in particular memory locations as defined by a predetermined memory map, which are preassigned to the respective demand intervals. Those locations associa-ted with demand intervals for a partial collection period after removal are filled ~ith zeros (that is, no e~ent measurement data is inserted). The partial collection period event data is stored temporarily in R~M 18 and _ ~ 7-~ 1~ 4~8 and transfer-~ec jltS ~ prior ~o removal of the memory module as indicated. i'he Removal Record also includes an iden-tifier code which identifies a customer or eustomeIs by correlating the me~ory module with a particular billing recorder from which ~he memory had been removed. Total pulse counts for the two channels A and ~ are also recorded as part of the Re~oval Record.

The Insertion Record is recorded at the end of the partial collection period following insertion of an erased me~ory module. This record includes time infor-m2tion, month, day, hour and minute of module insertion, and a five digit BCD identifier code. In addition, time data representing the month, day and hour ~efining the current collection period is recorded as part of the Insertion Record along ~ith any event data stored in RAM 18 ~t the end of the collection period. The event data is stored in particular memory locations associated with demand intervals for the collection period prior to insertion are filled with zeros.

The recorder circ~its normally obt~in power from an AC line source, but include battery carryover to main-tain selected circuits energized in the event of an AC
power outage. A power supply circuit 14 provides the required DC levels for the microprocessor system 11 via a power bus 50. A DC to DC converter 28 is energized by the AC line power or, if that is not present, the battery, via solid state swiich 29 under control of the CPU 16 which continuously senses for the presence of the 60 Hz. line signal for determining whether a power outage or failure is present. The converter provides the required DC
le~els for the bubble me~ory and its associated drive circuitry, ~hich comprise the magnetic bubble memory system 12. By means of the switch 29, the microprocessor de-energizes the bubble memory system during collection periods and selectively energizes it only for & ~a transfers at access times at the end of normal collection periods or at re val/insertion times.

In the case where the operating temperature specifications of the bubble memory meet or exeed those for the entiTe ~ecording system, the solid state switch 2 may be energized by the CPU 16 at the end of every data collection pe-iod for writing whatever data might have been accumulated during that period, without depleting the battery substantially since it takes less than about 100 milliseconds to write all of the data for a complete collection period. H~7ever, where the tem~erature speci-fications for the ~ubble memory do not meet the overall operating temperature specifications for the recorder system, particularly where'the recorder system is required to operate at a temperature below the manufacturer's specification for the bubble memory, the present system does not permit the writing of any data into the bubble memory (due to the possibility that data might be lost or errors mi~ht occur if the temperature of the bubble memory has in fact fallen below its operating specificatio,.), and the CPU 16 further initiates a thermal recoverv perio~

~ 4~8 which may be 45 minutes upon ~he return of AC line power by sensing a 60 Hz. signal on the line 30. As wi.ll be described m~re fully below, a special power recovery or power failure mode is implemented ~y the CPU and such a system will have additional Rando~ Access Memory 18 in which to store event data between the occurrence of a power outage and the termination of a thermal recovery period in a manner that will optimize the use of the additional ~emory, as will be understood from subsequent description.

Time reference data is generated under program control by the ~icroprocessor in units of minutes, hours, days, months, dzy of the week and year. The time base generator 13 includes a 60 Hz. signal received directly from the power line by the CPU. A crystal oscillator 32 and digital countdown circuit 33 provide an auxiliary timing signal input to the CPU in the event of loss of primary AC power. The latter signal has a frequency of approximately 61 Hz.

The CPU 16 counts the pulses transm~tted over each data channel A and B separately for the demand inter-vals. During each demand interval, the number of pulses recei~ed from each channel is encoded into a twelve bit binary word (one and one half bytes) representative of the total count, and this word is stored in the RAM 18. At the end of each full collection period, the sixteen data words (for a four-hour collection period and 15 minute demand interval) for each channel together ~Tith all other _ 2~ _ data comprising a complete record, as will be described, are transferred via data bus 51 from the RAM 18 to the bubble memory 23, under the control of the CPU 16.
The magnetic bubble memory system 12 includes a memory control circuit 21, a drive circuit 22 and the bubble memory module 23. The bubble memory systems are commercially available, and accordingly its structure and operation are not described in detail. Bubble memory systems are available from Texas Instruments, Inc., Dallas, Texas; and they are described in a publication by the same company entitled "Magnetic Bubble Memories and System Inter-face Circuits", 1977. The drive circuit 22 includes a func-tion driver 43 and coil drivers 44. The memory controller 41 responds to commands from the microprocessor system 11 and enables the necessary control functions to the function timing generator 42 to access a page (or pages) of the mem-ory 23, For a write operation, the CPU 16 supplies an address to the controller via address bus 48, and writes the data into an input buffer 41A of the memory controller 41. The memory controller 41 accesses the proper page and effects writing of the data into the memory. For a read operation the CPU 16 generates an address to select the module locations, loads the controller 41 with the proper page number and generates a read command. The memory controller accesses the designated page and stores the data in its buffer 41A. The memory controller 41 also synchronizes the operation of the memory control circuits and the operation of the bubble memory module.

;-~ ~6 ~

The function timing generator 42 provides input t;ming control to a function dri~er 43, a coil dri~er 44 and a readout circuit 46 on a per cycle basis. The function timing generator, under the control of the memory controller 41, generates five functions, including generate, replicate, annihilate, ~ransfer in, and transfer out for the two function drivers. The function timing generator also provides contrDl signals to the coil drivers ~o m~intain the proper phase relationship between the coils in each of the memory modules.

The function driver 43 converts lo~ic level signals from the.function timing generator into an analog form usable by the memory module 23. The coil drivers 44 respond to outputs of the function timing generator 42, and generate the prope~ current waveforms for driving the bubble memory devices.

The bubble memory module for the two channel system comprises a Texas Instruments Type TBM0103 bubble memory module which provides 641 pa~es of non-volatile, solid state memory having 18 ~ytes of data per page with 8 bits pe~ byte. The assignment of the bub~le memory store locations is illustrated in Ta~les I, II and III
which show, respectively, memory assignments for pages 1-4 (Insertion Record); pa~,es 5-7 (comprising one Normal Record~, and pages ~3~-641 (Rem~al Record). In all cases, other than module insertion/removal (and po~er recovery after an outage), the information is ~ritten from the RAM ~ to the bubble memory at the nor~.al access time at the end of collec-tion periods. In the illustrated embodiment, these occur every four hours starting at midni~t.
,~, ~16a~8 TABLE I - I~SERTIO~ RECORD

Pa~e D~ta No. of Bytes l Month, day, hour, min. (of Insertion)4 Identifier Number (I.D.) 5 Insertion Total Count (Channel A) 3 Insertion Total Count (Channel B) 3 (zero-filled) 3

2 Month, day, hour (Start of Current Col- 3 lection Period) Event Data for Channels A and B for five 15 Demand Intervals

3 Event Data for Channels A and B for six 18 Demznd Intervals

4 Event Data for Cnannels A and B for five 15 Demand Intervals Running Total (Channel A or B, depending 2 112 on which had been written last) Status l/2 TABLE II - NORMAL RECORD

Month, day, hour (Start of Current Col- 3 lection Period) E~ent Data (A and 8 for five Demand 15 Intervals) 6 Event Data (A and B for six Demand 18 Intervals) 7 Event Data (A and B for five Demand 15 Intervals) Runnin~, Total tA or B, altern.~tively) 2 1/2 Status 1/2 ~i64~8 TABLE III - REMOVAL REC~R~
. _ Pa~e Da~a ~o. o Bv.es 63~ Month, day, hour, min. (Removai Time) 4 Identifier Number (I.D.) Channel A Remo~al Total Count 3 Channel B Removal Total Count 3 (zero-filled) - 3 639 Month, day, hour (Collection Period Start 3 Time) F,vent Data (A and B for five ~cmand 15 Inter~als) 640 E~ent Data (A and B for six Demand 18 Interva~s) 641 Event Data (A and B for five Demand 15 Intervals) Running Total (A or B) 2 1/2 Status l/2 The records to be discussed presently are illustrations for a two channel (A and B) recorder since the single channel de~ice is more simple. With reference to Table I, the first page of,an Insertion Record contains the time (current month, day, hour and minute) of module insertion in the first four bytes and a five-digit Identifier Number (in BCD for~at and comprising the I.D. referred to throughout) is contained in the next fi~e bytes. The Channel A and Channel B Insertion total counts (i.e. cumulati~e counts of event data as of the time of insertion) are each contained in three bytes and the remaining bytes of the first page are zero-filled. The remainin~ three pages of an Insertion Record are the same as a Normal Record, to be discussed presently, excep.

~64~8 that the memory locations associated witll demand intervals that have transpired prior to insertion for the current access period are zero-filled up to the location associated with the current demand interval. The event data for remaining demand intervals for the current collection period are entered in the normal fields for that record.
~ ith reference to Table II which illustrates a Mormal Record, data for each collection period is recorded on three pages of the bubble memory in the following order.
The first three bytes of the first page store the time (month~
day, and hour) of the commencement of the collection period for which the associated event data is stored. The next forty-eight bytes record the measured event data for Channel A and Channel B for the sixteen 15-minute demand intervals comprising the four-hour period collection. It takes twelve binary bits (one and one-half bytes) to record up to 4096 (212) event pulses for a given channel in one demand interval.
Hence, in the case of a two-channel recorder, the twelve bits for Channel A are recorded in one full byte ~memory word location) and the first four bits of the next succeeding byte.
The event data for Channel B for the same interval is stored in the last four bits of the second byte mentioned and the full eight bits of the next byte. The order of storage makes no difference as long as it is accounted for in the software of the translator (actually Channel B data is recorded first).
Running Total count for Channels A and B is recorded in alternate Normal Records in two and one-half of the last three bytes of the third page. Thus, the Running Totals are cumulative counts of measured event data which are up-dated at the end of each collection period.

:1164~8 One-half byte (four ~its) of storage is reserved for status information. Bits B20 and B21 are reserved for failure indication of the Read-AfteT-Write test. Bit B22 indicates whether the accompanying Running Total for that record is associated with Channel A or Channel B. Bit B23 indicates whether a power failure has occurred during the collection period associated with that record.

Referring to Table III ~hich defines a Removal Record, upon removal of the memory card, the partial period data is written into pages 638-641. Page 638 contains the time (month, day, hour and minute) of module removal in the first four byt,es and the I.D. code in the next five bytes.
The Channel A Removal Total count is recorded in bytes 8-10 and the Channel B Removal Total is recorded in bytes 11-13.
The remaining bytes of page 638 are zero-filled. The last three pages are similar to a Normal Record (Table II) except that the partial data for the period of removal is written into the memory locations associated with demand intervals prior to removal, and the remaining locations sepresenting subs.equent demsnd inter~als are filled with zeros.
.

To illustrate the various records just described, reference is made to Chart A in which the left-hand column indicates running time. Assuming four-hour collection periods, at time 1200, a Running Total for Channel A is transferred as part of a Normal Record (Table II) to a first solid state memory module. Assuming that the first memory module is to be replaced at 1415, when the handle 49A (FIG. 5) is turned to the removal position, the contacts 49C, 49E open; and the microprocessor prepares a Remo~al Record (Table III). The Removal kecord includes, on pag~e 638, Removal Tot21 coun,s fo~

4~.Q8 Chart_A
1200 Normal Record-Running Total for Channel A

1415 Removal Record-Running Total for Channel B, Removal Total for Channel A, Removal Total for Channel B
1421 Insert New Module 1600 Insertion Record-Running Total for Channel A, Insertion Total for Channel A, Insertion Total for Channel B
2000 Normal Record-Running Total for Channel B
0000 Normal Record-Running Total for Channel A
0400 Normal Record-Running Total for Channel B
0430 Removal Record-Running Total for Channel A, Removal Totals for both Channels A and B
Channel A and for Channel B, each comprising three full bytes.
In addition, the Removal Record includes a Running Total for Channel B (since the Running Totals are alternated for the two channels). The Running Totals comprise two and one-half bytes --in other words, the lower order twenty bits of the Removal Total (which is three full bytes or twenty-four bits). In other words, in this case, the Running Total for Channel B
will correspond to the lower order twenty bits of the Channel B Removal Total count.
When the new memory module is inserted, at 1421 in the example, the microprocessor prepares an Insertion Record (Table I) in RAM; and this Insertion Record is trans-ferred to the memory module at the end of the collection period during which the new memory module was inserted --namely, at 1600 hours. At this time, the Insertion Record includes a Running Total for Channel A (twenty bits) as well ~64~?8 as Insertion Totals (twenty~four bits) for both Channels A
~2nd B. ~e I,nser~ion To..als on the Insertion Record will be identical tD the Removal Totals stored on the first module, but the Running Total for Channel A will include any measured event data occurring between removal of the first module (at time 1415) and the end of the collection period (time 1600).

At the end of each subsequent collection period, Normal Rec~rds are stored with Running Totals fos alternate channels. Assuming that this memory module is removed at 0415 hours, a Running Total (twenty bits) would be part of the Removal Record for that partial period; and Removal Totals would also be stored f~r both Channel A and Channel B.

By thus storing both Remov21 Totals and Insertion Totals, as well as Running Totals, complete data continuity can be maintained for the records, and if an error does occur, it can be isolated to a give demand period, so as to mini~ize the loss of data.

~ eferring now t~ FIG~. 1 and 5, the recorder includes a five digit LED type display 37 for displayin~ various information provided by the microprocessor. The display data is coupled from the CPU 16 via I/0 device 34 and the data bus 51.

There are two push button switches designated 39 and 40 in FIGS. 1 and 5 which are used to select the data that is to be displayed on the display 37 as ~ell as to se~
the I.D., time and calendar data. It is considered an ~' ~164~

important advantage that this data can be set by main tenance personnel on site. For example, if it appears that the recorder is inoperative or faulty, the system can be built such that either a complete new unit or in-dividual circuit boards may be replaced. He would then set the identification number of the old recorder, as well as time and calendar information, without having to return to the factory. This not only saves a maintenance trip, but it reduces the loss of billing data.
Normally the system displays the hour and minutes.
If the operator wants to set data he first sequentially presses switch 40 (or simply leaves it depressed) in which case the items to be set will be sequenced in the same order, but by the internal clock of the system. Referring to Table IV, the first time that switch 40 is depressed, the five digit I.D. number will be displayed, and the first digit (the most significant digit or digit 5) will be flashed. If the display is left in this state, subsequent depressions of switch 39 will sequence that digit to the ten possible states (decimal digit ~-9).
If, before setting that digit, the operator had continued depressions of switch 40, the system would cycle through the parameters shown in the middle column of Table IV. For example, on the eighth depression of switch 40, the month and date would not be displayed, the month would be flashed on the display, and subsequent depressions of switch 39 would sequence the month (1-12).
Ultimately, with sequential depressions of switch 40, the g8 s~ste~. reverts to program control in which the h~ur and minute are displayed.

If switch 39 is depressed first, the system goes into a Command Display Mode. In this mode, sequential depressions of the switch 39 causes the display of the following information in the order listed: (I) word 1:
I.D.; (II) word 2: year/day of week; (III) word 3 monthl day; (IV) word 4: hours/minutes; and (V) word 5: "PULSES"
(which represents the Field Test Function). If switch 39 is held down in the Command Display ~lode, the system will cycle through these words in the above order display time long enough to.perceive the Field Test Function on the five-digit display 37.

- To implement a field test function, the operator simply pushes switch 39 first. The controller, which normally displays hours and minutes, immediately displays the information the CPU has received from the I~O circuits 19 on data bus 51 and stored in a register. Channel A is displayed in one digit location (the furthest one on the left, for ex2mple~, Channel B on another, and so on, if more channels are employed. As the state of the associated pulse initiator changes responsive to the consumption of energy, the signal being displayed alternates between a "I" and a "O" to indicate operativeness to the operator.

In its cyclic operation of the program, the CPU
looks at the contents of the register and if they have changed from the data previously stored in RA~I memory, . . _ thereby indicating a change of state in the associated pulse initiator, then a display subroutine is entered which changes the digit being displayed in the display location associated with that particular channel. It is an important function of this type of test that not only is the pulse initiator work-ing, but also the data input channel electronics and micropro-cessor and RA~I storage, etc., are also functioning properly, as well as the display logic and display.
To describe the Read-After-Write test in more de-tail, after a complete record is written in the bubble mem-ory, the data is read out in a first-in first-out (FIF0) register in the memory controller. The data in the FIF0 register is then transferred a byte at a time to the D
register in the microprocessor which then compares the contents o the D register with the data that had been written to the bubble memory. Any detection of non-equality indicates a failure of the test. This procedure is repeated three times. If the Read-After-Write test fails three successive times, bits B20 and B21 are set to l's in RAM to indicate such failure, and this record is written into the bubble memory a fourth time for permanent storage. A visual indicator 48 of Figure 5, which may be an LED, may be caused to flash to alert personnel.

~6 IABLE IV

Word Seleeted Parameter Set ~y_Swi~ch_40 Parameters Displaved y Switch 39 l 5 Digit ID . Digit ~
2 5 Digit ID Digit 4 3 5 Digit ID Digit 3 4 5 Digit ID Digit 2

5 Digit ID Digit l

6 Year/Day of Week Year

7 YearIDay of Week Day of Wee~
~ Month/Date ~onth 9 Month/Date Date Hours/Minutes Hours 11 Hours/Minutes Minutes 12 Re~erts to program control and starts internal clock ~-- 3 _ _ ~1~4~8 ~ s indicated above, the device 49A is operator actuated ancl has two states indicating respectively whether the memory module is in operative relation witll the recorder or not. ~len the operator actuates it to permit the memory module to be removed, it generates a signal for enabling the CPU 16 to write the special Removal Record (Table III) into a predetermined location of the bubble memory. This takes only about 100 Ms. Similarly, when the new module is inser~ed and the lever 49A is moved to the position shown in solid in Figure 5, it generates a signal to cause the CPU to prepare the Insertion Record (Table I) in RAM. It is noted that this record is not written into the first four pages of the new memory until the end of the collection period during which the new module is inserted. Briefly, the device 49 operates switch contact 49E (Figure 1) which triggers a sensing circuit 62 for generating a control signal which is transmitted to the CPU 16 via I/O circuits 34, which may be conventional peripheral inter-face adapter circuits.
The foregoing description of the magnetic bubble mem-ory system 12 describes a two-channel billing recorder. For a single channel recorder, the bubble memory module provides data storage for 213 8-hour collection periods. The assignment of memory locations for a single channel recorder is similar to that illustrated in Tables I-III for a two channel recorder in that 12 bits (one and one-half bytes) are provided for each demand interval. Hence, the 48 bytes which contain event data provide storage for 32 demand intervals for a single channel input, rather than 16 demand intervals as in the two channel recorder.

~;~ ~

~6~t~
Also, those bytes assiglled for storage of the Rullnill~
Total for the second channel of a t~o-chanllel recorder contain the single channel Running Total in the case of a single channel recorder.

~6~

OPeration ~ eIerring to FIGS. 1 and 3, each billing period (comprisi.n~ a p:Lural~ of collection periods) is commenced ~hen an erased (zeroed) bubble memory module is inse~ted into the recorder. By way of example, let it be assumed that the erased module is inserted on December 1~ at

8:35 A.M. Upon operation of the device 49 to latch the memory card 24 into place, the cam 49C engages contact 49E
causing the sensing circuit 62 to generate a control signal which is transmitted to the CPU 16 via I~0 circuit 34, causing it to prepare the Insertion Record in RAM. Speci-flcaily, it storés data representing the mont~, day, hour ant minute in RAM 18 along with the identifier code word for subsequent transfer to the bubble memory. The CP~ 16 causes zeros to be written into RAM 1~ in s~orage locations ~llocated to demand intervals of the current collection period for the ltwo !intervals-which~ haie aiready ~ranspired, namely, the two demand intervals from 8:00 A.M. to 8:30 A.M.

After the module insertion time has been stored in RAM 18, the CPU 16 accumulates data pulses for the ~est of the current access interval. The CPU 16 via input/output interface 19, scans the output of the data channels A and B and maintains a running count of the number of event pulses received for each channel for the balance of the collection period. The running count is also maintained in the RAM 18.

A~ ~n~ ena o~ each demand interval, as indicated by the digital clock of the microprocessor system 11, the CPU
under control of instructions stored in ROM 17 selects different storage locations in the RAM 18 for storin~ data words repre-senting respectively the total numbers of pulses recei~ed over channels A and B during each demand interval. Twel~e bits are allocated for each channel for each demand inter~al. The CPU 16 also ~intains a runnin~ total of the data pulses received over each data channel A and B in separate total count registers.
These totals are continuously updated for each timing pulse deri~ed from the line frequency, in the normal case ~i.e., where there is no power outage).

At the end of the partial period following insertion of the new memory module, the CPU 16 transfers the data stored in RAM 18 to the bubble memory 23 to provide the Insertion ~ecord in accordance with Table ~. First, the CPU 16 generates a signal fcr enabling solid state switch 29 to apply DC power to the DC to DC converter 28 for energizing the memory system 12. The CPU 16 also generates an address for the bubble memory system 12 to address the first page of the bubble memory module 23.
"' The four data words representing the month, day, hour and minute of insertion are transferred as a page to a FI~O ~egister in the memory controller 21. A write-command is then issued by the CPU 16 to cause the data to be written into the bubble memory. The memory controller 21 responds to the control signals provided by the CPU 16 to enable the function timing generator 42 to generate the control signals or effecting the wIite operations for application to the function driver 43 and coil drivers 44. The i~entifier code word as well as all other data of page one o~ ~I7 `~nser~i n Record is transferred to the ~emory control'ler at the same time. The read-after-write test described above is per~
formed after each complete record is transferred to the bubble memory.

When this first page of Inser~ion Record has been written into the memory 23, the CPU 16 then effects the transfer to the memory 23 of the demand data for the current collection period. The CPU generates an address for the bubble memory system to access the second page of the bubble memory module 23 and causes data representing the month (December), the day (18), and the hour (12 o'clock), defining the end of the current dem~nd interval, to be written into the first three bytes of page 2 as shown in Table V. The ~emory locations (bytes 4-9) allotted to event data from the time 8:00 until the end of the demand interval immediately preceding insertion are zero-filled -- namely, the demand intervals beginning at 8:00 and 8:15 for each channel~ The data for channel A for the first partial demand inter,val (8:30 -,8:45) is recorde,d i~ the tenth byte and the first four bits of the eleventh byte. The corresponding data for channel B is recorded in the last four bits of the eleventh byte and the eight bits of the twelfth byte. Event data for the demand intervals up to 9:15 A.M. are entered in the nor~al fields for that record on page 2 of the memory.

~ ~ 4~

TABLE ~ ERTIO~ RECORD - Page 2 Byte In~ormation Data 1 ~oIl~h 12 2 Day 18 3 Hour 12 4 8:00 - 8:15 (B) zero OO(B)/OO(A) zero 6 8:00 - 8:15 (A) zero 7 8:1~ - 8:30 (8) zero 8 15(B)/15(A) zero

9 8:15 - 8:30 (A) zero ~ 8:30 - 8:45 (s) partial 11 30(B)/30(A) partial 12 8:30 : 8:45 (A) partial 13 8:45 - 9:00 (B) filled 14 45(B.)/45 ~) filled 8:45 - 9:00 ~A) filled 16 9:00 - 9:15 (B) filled 17 OO(B)/OO(A) filled 18 9 oo _ a 15 (A) filled _~

~J,64'~8 Tlle CPU 16 then addresses page 3 of the memory and causes the remainder of the data for successive demand intervals up through the demand interval beginning at

10:30 for both channels to be recorded. The fiTst fifteen bytes of page 4 then record event data for demand intervals up through the demand interval beginning at 11:45 A.M. The running total count for the data for channel A is written as the first twenty bits of the last three bytes in page 4, as explained above.
After the partial data for the first collection period has been written into the bubble memory and verified by recall in the CPU, the CPU 16 disables the solid state switch 29 thereby de-energizing the bubble memory system 12 during the next four-hour collection period. Also, the insertion of the bubble memory is sensed by the CPU which generates a current to change the state of the bistable indicator 47 to indicate that the bubble memory now stores data.
When a new (i.e., erased) bubble memory is inserted in the recorder, the CPU decrements interval mechanically register which is originally set to represent a predetermined thermal time period representative of the worst-case time for the bubble memory to achieve its operating temperature. The writing of data into the bubble memory is inhibited until the end of the thermal recovery period. The thermal recovery period could be implemented mechanically, and would not even be required, of course, if the bubble memory specifications permitted operation through the full range. If the thermal recovery period overlaps the access time (i.e., extends into the next collection period) the CPU transfers the Insertion 1~6~

Record ~o an unused section of RAM until the time-out si~n21 is generated; and it then tr~nsfers the Insertion Reco~d da~2 for storage in the bu~ble memory, even though it is not at the normal access time.

During the next collection period, the data is a~cumulated in the ~AM 18 and transferred to the bubble memory 23 as a Normal Record, as shown in Table II. It will be observed that for ~his collection period the running total count for channel B is recorded in the first twenty bits of the last three bytes of page 7 of the bubble memory. The remaining pages are filled with Normal Records in like manner such that a total of up to 213 four-hour collection periods are recorded, including the two partial intervals when the memory card is inserted and removed, are recorded. The total count register of each channel is updated at the occurrence of each timing pulse.

Should a power failure occur (that is, the loss of 60 Hz. line ~oltage) during a collection period, an oscillator 32 (which may be the internal oscillator of the CPU) is used to generate th,e time base. The frequency of the oscillator signal is counted down by a divider circuit 31 to supply a time reference for the CPU 16. The CPU
deter~ines the power outage ~y sensing for the 60 Hz. line signal. Briefly, the 60 Hz. line signal is shaped into a pulse, and the CPU enters a loop comprising an interval timer. If the internal timer times out before the line fre-quency pulse is detected, the CPU defines it as a power outage and switches to crystal clock of oscillator 32 " ~(, ~

~16~8 divided by divider circuit 31. This signal has a repeti-tion rate of approximately 61 llz. The DC power maintains the controller circuits energized during the power outage preventing loss of stored data and allowing the CPU to con-tinue generating its time reference. However, the displays are disabled to conserve battery power.
When it is time to remove the memory card 24 at the end of the billing period, the device 49 is actuated by the exchange personnel and the CPU effects the recording of the Removal Record in accordance with the format set forth in Table III. If the memory module is removed before the end of an access period, the partial record, which is recorded in the last four pages of the bubble memo~y in-cludes all of the data recorded in RAM during the access period. The CPU 16 also energizes an indicator 35 to indicate that a data transfer operation is in progress.
As illustrated in Table III, the month, day and hour of module removal are recorded in the first three bytes of page 638. The data in the partial demand interval is transferred to RAM. Whenever event data is written in the bubble memory and has been verified, whether at the end of a normal collection period or at the end of a billing period when the memory is being replaced, the ~ ~6 ~?~8 interval counters are rese~ to zero. The t~tal c~unter~
~em~ updated at all times, and they roll over at a predetermined cumulative count. However, upon the first application o~ power, whe~her as a result of a power outage or recorder installation or replacement, the total counters are initialized by se~ting the contents to zero.
Then the event data for both channels is written into pages 639-641 of the memory, preceeded by the five digit identifier and the running total counts for channels A and B as illustrated in Table III.

The customer has an option as to whether or not to account for daylight saving time changes via the Select D.S.T. input 33B of ~IG. 1. In this embodiment, a computation is made to define the-last Sunday of the month during which a DST/ST change is implemented. If he selects this option, in the spring when the change is to be implement~d, two functions are performed: (1) the clock is incremented by one hour at 2:00 A.M. on the Sunday in which daylight saving time is implemented; and (2) the four demand intervals for each channel (assuming a 15 minute demand interval) associated with the hour 2:00 A.M. to 3:00 A.M. of that day have to be zero-filled. This is accomplished, briefly, by loading zeros into the associated demand interval :1 ~L6 4, ~CA~ ~3 portions of RAM and then ~riting that infor~ation into the bubble memory. Thus, the bubble memory is zero-filled for the demand intervals between 2:00 A.M. and 3:00 A.M. The event data is collected for the daylight saving time hour 3:00 A.M. to 4:00 A.M., and this data is written into the bubble memory in association with the proper demand intervals at the end of the next collection period.

In the fall, the clock is turned back an hour in switching from daylight saving time to standard time.
Two separate records are prepared. In the first record, the four demand intervals for the hour between 12:0~ and 1:00 as well as the four intervals for the hour between 1:00 A.M. and 2:00 A.M. have normal event data. The remaining two hours for that collection period are zero-filled to comprise record Rl. This is written into the bubble memory at or shortly after 2:00 A.M. At the same time, the second record, namely record R2, is prepared by zero-filling the first four demand intervals comprising the hour 12:00 to 1:00, and thereafter, normal data is collected and stored.
This record is written into the bubble memory at 4:00 A.M., the end of the current collection period.

Remote Interro~ation In the foregoing description, the recorded bubble memory modules are exchanged for an erased module at the end of each billing period, and the recorded modules are transported to a translating center for reading.

In FIG. 4 there is illustrated a bloc~ dia~ram of a system which ~ermits remote readout of the recorded data over a co~munication link 7Q, such as a telephone link, established between the translating center 71 and the point of service 72 where the billing recorder is located.

An interrogate controller 73 at the translating center generates audio fre~uency interrogate signals which are tr~nsmi~ted over the link and coupled via line coupler 74 to a data transponder 75 associated with the ~illing recorder. The data transponder receiver 81 detects the audio frequency interrogate signals and generates suitable logic level control signals for application to the billing recor~der circuits to effect readout of the recorded data. The data transponder includés a transmitter 82 which converts the logic level data signals read out into audio requency signals, coded to represent the data, for transmission to the translating center.

A conventional telephone set 78 at the trans-lating center is used to place a call to the number assigned to the telephone line coupler 74 causing the da~a transponder 75 to be coupled to a telephone line 79 which f orms part of the telephone link. When the link is established, a read signal at a preselected audio frequency fO is transmitted from the translating center to the data transponder and detected by audio frequency receiver 81 which includes a line detector which converts the received 1 audio signal to a logic level read command sig.l~l. The comm~nd si~nal is extended to the billing recorder controller by way of 1/0 circuit 34 (FIG. 2), for exam~le.

~6~ C~

The CPU 16 responds to the read command to effect sequential readout of the data stored in the bubble memory 23. The data read out is extended via the I/O circuit 34 to the transmitter 82, which responds to the logic 1 and logic Q
level data signals to generate audio frequency reply signals at different audio frequencies fl and f2 respectively, for transmission to the translating center, the frequency coded audio signals are converted to a data format suitable for processing and transferred to a suitable storage medium.

User Options There are three user options in the system, and they are diagramma.ically represented in FIG. 1 by blocks designated respectively 33A, 33B and 33C. These represent selections of: (a) one or two input channels; (b) Dayligh Saving or Standard Time Select; and (c) Fifty or Sixty Hz.
line frequency. Each of these selectors may comprise a wired logic state, a toggle switch, or a binary circuit.
According to the first option, namely Channel Selec-t, the user has the option of determining whether one or two input channels are stored in the bubble memory. ~he output signal, referred to as EF2 is sensed by the CPU 16 and used as appropriate throughout the data processing. For example, in Chart B, block 132, the CPU has to determine whether there are one or two input channels for storing demand interval data in the appropriate RAM locations, as described in detail elsewhere. Similarly, the DST/ST Select generates a logic signal EF3 which is used by the CPU 16 in block 1~6 of FIC. 2 to effect changes as they occur and as ~, rF

~64~

selected by the user. Finally, block 33C generates a signal as selected by the user and designated EF4 which accommodated the system to either fifty or sixty Hz. line frequency; and this information is used in block 125 of Chart B to generate clock and calendar data. Briefly, this data is generated by incrementing a register to a predetermined count (namely, to sixty in the case of 60 Hz. line frequency or to fifty in the case of 50 Hz. line frequency) for incrementing a register which counts seconds and determines the program execution time.

To~alizer Operation Referring to FIG. 1, there are four input channels designated respectively A, B, C, and D. Each of these channels is associated with a conventional pulse initiator for receiving input data; and each of the input channels, designated respectively l9A, l9B, l9C and 19D comprises a latch circuit responsive to incoming data from an associated pulse initiator for storing it temporarily. The output signals of the data channels are fed in parallel to the input/output circuits 19 of the microprocessor which also are latching circuits.

Data channels C and C are shown in chain line because, as indicated above, the system may be a single channel or a two channel recorder. In the case where channels C and D are used, the system may be a totalizer --that is, the event data from two input channels is accumulated and stored. Where data channels C and D are ~ ~L64~

present, and it is desired to sum or ~totalize" the inputs, for example, the inputs on channel A can be totalized with those on Channel C, and those on Channel B can be totalized with the data inputs on Channel D. In this case, the microprocessor reads the data on channel A, and the data on channel C and adds either zero, one or two counts to the appropriate Running Total count for the current demand period and separately, the cumulative counts for Insertion and Removal Totals, as described above. This updating of the registers happens every input data sample period which, in the illustrated embodiment, is derived from line frequency.
Because of the high speed at which the microprocessor is capable of sampling input data relative to the time periods during which input data is expected to change, this capability of totalizing is inherent in the system. That is, the problems associated with coincidence of data inputs in conventional totalizers are inherently overcome due to the structure of the system.
Having thus disclosed in detail preferred embodiments of the invention, persons skilled in the art will be able to modify certain of the structure which has been disclosed and to substitute equivalent elements for those which have been illustrated. For example, the length of demand interval and collection period may be changed. The device 48 may merely sense the insertion and removal of the module. The number of channels, data storage allocations and event data representations (totalized, for example) may also be varied, among other things. It is, therefore, intended that all such modifications and substitutions be covered as they are embraced within the spirit and scope of the appended claims. ~7 -,.

Claims (29)

The Claims

1. Data recording apparatus for providing a record of event measurement data from at least one data source comprising:
input means for receiving data signals representing said event measurement data;
timing means for generating digital signals representative of real time;
controller means for receiving said data signals and for generating data word signals representative of the quantity of data signals received during a predeter-mined time interval;
first memory means for storing real time signals defining said intervals and said data word signals associated with said intervals; and second memory means comprising non-volatile, solid state memory means and memory control circuit means responsive to said controller means for transferring said real time signals and said data word signals accumulated in said first memory means to said non-volatile memory means for storing the same in predetermined relation.

2. The apparatus of claim 1 further comprising switchable power source means for said solid state memory means, said controller means being responsive to said timing means for selectively energizing said power means during access times for said solid state memory means for writing said data word signals and said real time signals therein.

3. The apparatus of claim 2 wherein said timing means includes a line frequency signal, said controller means sensing the absence of said line fre-quency signal for controlling said switchable power source means for de-energizing said solid state memory means during power outages.

4. The apparatus of claim 3 wherein said con-troller means includes additional capacity in said first memory means for storing event data during power outages while said solid state memory means is inhibited.

5. The apparatus of claim 1 wherein said data source generates serial data and said recording apparatus is a recorder unit associated with said meter defining receptacle means, said second memory means comprising a removable memory module including said solid state memory means and adapted to be removably received in said receptacle means for operative association with said memory control circuit means.

6. The apparatus of claim 5 further comprising actuatable means actuatable to generate a first state signal representative of said memory module's being inserted in said receptacle means and a second state signal representative of said memory module's being prepared for removal from said receptacle means, said controller being responsive to said first state signal for preparing Insertion Record data and for storing the same in said solid state memory means after insertion of said memory module in said receptacle means, said con-troller means being further responsible to said second state signal for preparing Removal Record data and for storing the same in said solid state memory prior to removal of said memory module from said receptacle.

7. The apparatus of claim 1 wherein said data source is an electric meter and said signals from said data source comprise pulses, each representative of a predetermined quantity associated therewith, and wherein said controller means generates a total count data word representing a continous running total count for said pulses for all of said intervals and stores said total count data word in said solid state memory means.

8. The apparatus of claim 1 wherein said second memory means is adapted to store said data words for a complete billing period, each billing period comprising a plurality of collection periods, and including preassigned memory locations for separately recording data words associated with said measured events occurring within collection periods associated with said locations res-pectively said controller means generating a further data word representing a running total count for detected events during successive collection periods and storing said total count data word in said solid state memory means at the end of each collection period.

9. The apparatus of claim 1 wherein said input means includes means for receiving data signals from a plurality of data sources, said controller means processing the data signals received from each data source and generating separate data words representative of the number of data signals received from each data source during the same time interval.

10. The apparatus of claim 1 wherein said solid state memory means is removable from said data recording apparatus and replaceable by another solid state memory means, and wherein said controller means stores identifica-tion data signals representative of the particular data re-cording apparatus with which said controller means is asso-ciated, said controller means further transferring said identification data signals for storage in said solid state memory means.

11. The apparatus of claim 10 further comprising externally accessible set means actuatable by an operator for selectively setting said identification signals stored by said controller means, whereby the identification of said recording apparatus may be changed on site.

12. The apparatus of claim 1 wherein said controller means is responsive to said timing means for generating sig-nals representative of calendar data words, and for storing calendar data words in said solid state memory means in pre-determined relation with data words associated with intervals defined by said stored calendar data words.

13. The apparatus of claim 1 wherein said solid state memory means comprises a magnetic bubble memory for storing event data words serially according to source, said memory characterized in that the signals stored therein are retained in the absence of power supplied to said memory, said controller ener-gizing said memory means only when accessing the same for storing data therein.

14. The apparatus of claim 10 wherein said non-volatile memory means further comprises bistable visual indicator means for providing a first indication whenever the magnetic bubble memory is erased, and for providing a second indication, distinguishable from said first indication, whenever data is stored in the magnetic bubble memory.

15. The apparatus of claim 4 wherein said data recording apparatus includes a receptacle for removably receiving said memory module, said data recording apparatus further including means actuatable by an operator and having means for generating first and second control signals in response to operation thereof after insertion and before removal of said memory module respectively;
and said controller means being responsive to said control signals for generating associated records in said first memory means and transferring the same to said second memory means.

16. The apparatus of claim 15 wherein said controller means is responsive to said first control signal from said actuatable means upon insertion of a memory module for storing time reference data from said timing means indicating the time of insertion in said first memory means for subsequent transfer to said second memory means.

17. The apparatus of claim 15 wherein said controller means is further responsive to said first control signal from said actuatable means for storing in said second memory means signals representative of the identification of said recording apparatus.

18. The apparatus of claim 17 wherein said controller means is further responsive to said first control signal for storing Removal Total data in said second memory means representative of total counts of measured events up to the time of removal of said first memory.

19. The apparatus of claim 15 wherein said controller means is responsive to said second control signal from said actuatable means prior to removal of a memory module for storing time reference data from said timing means in said second memory means indicating the time of removal of said second memory means.

20. The apparatus of claim 19 wherein said controller means is further responsive to said second control signal from said actuatable means for storing identification data in said second memory means repre-sentative of said particular data recording apparatus prior to removal of said second memory means therefrom.

21. The apparatus of claim 20 wherein said controller means is further responsive to said second control signal for storing Removal Total data in said second memory means representative of a cumulative running total of said measured events prior to removal of said second memory means.

22. The apparatus of claim 15 wherein said control signal generating means of said actuatable means comprises a switch having contacts operable between open and closed positions in response to operation of said locking device, and sensing circuit means responsive to operation of said switch contacts to generate said control signals.

23. The apparatus of claim 1 wherein said controller means is responsive to said timing means for generating signals representative of calendar data and wherein said controller means is responsive to data representative of changes to and from daylight saving time, for generating special records for storage in said solid state memory means when said changes are effected.

24. The apparatus of claim 1 wherein said controller means generates a data word representative of the quantity of data signals received during a pre-determined demand time interval for a predetermined number of such time intervals comprising a collection period, and stores the event data for a complete collection period in said first memory means prior to storage in said second memory means, said controller means generating a normal data record at the end of each collection period including calendar data identifying said collection period and event data words for each demand interval in said collection period and for transferring said normal data record to said solid state memory means at the end of each collection period.

25. The apparatus of claim 1 wherein said controller means performs a comparison test after each transfer of data from said first memory means to said second memory means by retaining the data in said first memory means, writing the same data into said second memory means, retrieving the data written into said second memory means and comparing said data with the corresponding data retained in said first memory means, said controller means further transferring test failure signals for storage in said second memory means if a failure of said read-after-write test is detected.

26. The apparatus of claim 1 further comprising display means and externally accessible control means, said controller means being responsive to said externally accessible control means for coupling the contents of said first memory means representative of said data word signals to said display means for displaying changes in said data word signal in real time, said changes being representative of the opera-bility of said input means, said first memory means and said controller means.

27. The apparatus of claim 1 further comprising a data transponder associated with said data recording apparatus and including receiver means for receiving an interrogate signal generated by an interrogate means at a location remote from the location of said data recording apparatus and transmitted to the location of said data recording apparatus over a communication link, said receiver means being responsive to said interrogate signal to generate a control signal for application to said controller means for retrieving the data words stored in said second memory means, and said data transponder means including transmitter means responsive to the data words read out for generating information signals representing data words for transmission over said communi-cation link to said interrogate means.

28. The apparatus of claim 27 wherein said communication link includes a telephone line, said inter-rogate means including means for establishing said communication link between said first and second locations and for connecting said data transponder to said telephone line. -57-

29. Data recording apparatus for providing a record of event measurement data from a data source comprising:
input means for receiving data signals from said source representing said event measurement data;
controller means for receiving said data signals and for generating data words representative of the number of data signals received from said source during a given interval of time;
non-volatile solid state signal storage means for storing said data words;
energizing means connected to a source of power for deriving power signals for selectively energizing said signal storage means;
said controller means including timing means for generating timing signals indicating writing intervals during which the data words processed by said controller means are stored in said signal storage means;
and power switching means responsive to said controller means for energizing said signal storage means only during writing intervals.