CA1203285A - Solid-state electrical-power demand register and method - Google Patents

Abstract

SOLID-STATE ELECTRICAL-POWER DEMAND
REGISTER AND METHOD

ABSTRACT OF THE DISCLOSURE

A solid-state demand register is described for determining the maximum electrical-power demand made on an electric utility by a load. The register, which employs a microprocessor, provides noncumulative, cumulative, and continuous-cumulative electrical-power demand measurement capabilities. The microprocessor, operating under a control program stored in a read-only memory, employs computing constants and generates computed results. A
nonvolatile read/write memory, which stores the computing constants and computing results, is of the type that retains stored data even when deenergized. These constants and results can be visually displayed by an optoelectronic display. Error detection and correction of data are performed by the programmed microprocessor by means of an eight-bit Hamming code. The register further includes pulse generators for generating pulses indicative of the electrical-power demand and the end of a demand-monitoring time interval, and includes a controller for inhibiting the optoelectronic display when the ambient light adjacent the controller falls below a preselected threshold level.

Description

44 .337 X AND M~E~D

OF ~E Ihv~

lo Field of the Invention . The present invention relates generally t~ electrical-pcwer demand re~isters and methods. ~ore particularly, the present invention is direct~d bo a solid-state electrical-pcwer de~and register and method emplcying a nonvolatile read/write memory which re~a m s stored da~a even when d~energized, and also e~ploying error detectlon and correction of data.

2. Description of the Related Art Custoner electrical loads draw el~ctrical power fro~ an electric~l utility. For the utility bo be capable of su~ply mg electric 1 po~er to all its custGmers under worst-case conditions, 15 th~ utility must ~e able to predict the peak power demand of each custcmer and have sufficient pcwer-generating capacity to meet the worst-case peak demand. Failure to be able to meet the ~orst-case peak demand results in brownouts or even blac~outs, which subject the utility and its customers to adverse consequences.
The larger the worst-case peak de~and, the greater the peak pcwer-generating capacity of the utility must be. If custcmers can reduce peak demands, the utility can concomitantly reduce rese~ve power-generating capacity. The reduce~ reserve capacity will ultLmately be reflected in lower bills to the customers.
To foster custcmer reduction of peak demands, two types of metering arrdng~.~lLs or registers have develcped to provide the ~uS~ r and the utility with needed electrical pcwer consumption information: the de~and meter or register and the ti~e-of-day energy ~a,~u~,~Lio~ meter or reg~ster. Briefly, a d~and register i~dicates the peak pcher demand by a custcmer within a preselect.ed time measurement in~erval, irrespective o~ wh~n the demand oocurs. A tlme~of day, energy-c~..s~ ~ion register, on the other hand, measures electrical-pcwer c~n,~tion during preselected pericd~ whic~ are characterized according to time o~ day, type of

3$

;~-: h ,~, day (for example, w~ekday, ~eekend, or holiday), and season (ror example, sunmer or winter).
Turning bo the demand register, there are at least three types of measure~ent data that ~n ~e provided: n~n~ tive;
S ~umulative; and, con~inuous-cumulative. A n~ tive or block-interval de~and register measures, stoses 3nd displays the 1 rgest electrical-pcwer dem~d incurred durin~ a measurem~nt interval within ~ billing period. At the end of each billing period, the stored value is reset to zero by the meter reader or billing apearatus.
~ c~ tive demand register measures and stores the largest el~c rical-~oher d2ma~d incurred d~xin~ a rent billLng Fericd (t~at is, the ~ame value measured by a norr~r~ tive demand register). It ~lso measur2s, stores and displays the running sum of the larges~ denands incurred during each previous bill~ng period. At the end of the billing period, the stored value corr~cr~rKling to the largest electric~l-power demand for the billing p~riod ~ust ende~ is added t~ the runni~g sum and is then reset to zero.
Durirlg a curre~t billin~ per~od, cont m uous-e l~tive demand register measures and stores as a first stor~d value eaeh s~rc~csive~ e~e~trical-pcwer de~and which is larger than a previcusly largest de~nand that was in~urred since the beginning of this billing period. Each time a higher peak i5 deL~L~d, the firs~ stored value is updated wi~h the even larger demand value, and a se~x~ld stored value is increased a3~0rdingly. This second stored value ~Y;LI~ ~ bo a runnin~ sum of the largest electrical-power demands incurred during previous billing periods and the largest electrical-pc~er demand incurred up to the present time o the current billin~ period. Only this second stored value is normally displayed. At ~he end of each billing period, the first s~ored value is reset to zero.
Until recently, demand registers have been mirh~n;~l, Such a~paratus have a register coupled to and driven by eddy-current 3~ ind~ction motors of the type found m oonventional electrical-energy us2ge ~kilowatt-hour) meters ccmnc~ly e~ployed by utilities ~or biLling purposes. In fact, it is not ~

for a r~h~n;~l electrical-energy usage register (either of the time-of-day ~ype or otherwise) also bo include a mech~nical derand re~ister.
~P~h~n;c~l demand registers ~xhibit several disadvantages.
Ihe ~-h~n;c~l demand re~ister places an increased me-h~n;c~l load on the edcy-c~rrent induction mob~r. In addition, because demand is t~pically measur~d cver a fixed time interval ~typically frcm ten to thirty minutes) means must be inr7~l~e~ to actuate the m~sh~n;r~l de~nd regis~er ~or the denand-monitorin5 interval.
o miS means c~rlicates the design of the cverall meter.
With the advent of solid-state el~ctronics, electronic demand registers have b~en develcped. These circuits are often small enough to fit inside the housing of a stand2sd kilowatt-hcur æ ter. Su~h solid-state de~2nd registers calculate peak pcwer demand cn the basis of signals which define a deman~- nitoring interv?l and which descri~e ~he ~ ion of electrical energy during the demand-monitoring intervals. Micrcprccessccs have be~n emplcyed in scme solid-state dem~nd re~isters.
Stat~ of-the-art t~-of-day registers also emplc~
mi~yL~:essors. Unlike demand registers, which do rx~t require their timing pulses to ~e generated Ln a.L~ ;c~e with the actual ti~e caf c y, a time-of~day energy-consumption register must in~lude a ~ackup battery so that its cl ~k will rot be turned off when electrical pcwer to the register is cut off due to a power outage, c~stomer ~ampering or the l;ke.
In rnic~ o~ss~L-based, time-of-day and de~and registers of recent design, randcm-access mernories ~Ms) have been em~lc~ed~
A backup battery is re~uired to energize the randcm ac~ess memory during a voltage dip on or failure of the alternating-current to prevent loss of data stored in such a memory.
m e use of su~h a backup battery results in sever~ tPrhnir~l fi~j~nri~ Tn~ ;n~ a battery in a register increases its ~-nrl~;ty, cost ar~d naintenance requirements. Should the battery ma~Lfunction and a power ma m s failure or severe voltage dip occur, the data stored in the memory wil1 be lost. Furthermore, batteries have limited life and thus require periodic r~p~ m~t.
In addition, the envi~onments in which many registers are used put extre~e tem~erature cr h~udity or both stress the batteries s These requirerl~ents point to the necessity of includiny some provision for ensuring ar~ maintaining the integrity of storecl cornputing constants and cor~uted results. ~hile certain demand registers of recent design employ simple data error-detectior techniques such as the use of checks~ns, more effective error detection is required. Furthermore, these registers have not included data error-correction techniques. The lack of error-correction capability means that s~ch registers must be removec~ from use and either replæ ed or put back in ~roper working cor~ition.

SUMMARY OF r~lE INv~NrIoN

A general object of the present invention is to provic~e an improved methc~ and apparatus for measurirK3 electrical-power demand.

This and other objects are attained, in accordance with one aspect of the invention by a register for rnonitoring electrical-power dennand made upon alternating current mains, colr~prising: (a) means, responsive to power conr;~lnl~d from said mains, for computiny values of electrical-power demand over a succession of demand-monitoring intervals, said c~n~ut-n~ rneans including: 5i) sensing nleans for providing pulses at a rate substantially proportional to consumption of electrical eneryy in said mains, said pulse rate being ele trically prograrnnable; (ii) means for defining said succession of demand-monitoring intervals; (iii) means, responsive to said SenSlnCJ means ancl said de~ining n~earls, for accumulating said pulses generated durir~ each said demand-monitoring interval; and ~iv) means, responsive to said ac-cumulating meansl for generating said dernanci-monitoring interval values of electrical-power demand; (b) rneans, responsive tc) said computing means, for determining a maximwm demand-monitoring interval value oE the electrical-power demand; and (c) nonvolatile read/write memory means, responsive to said determining means, for storinc3 said maximwn deman~ monitorin~
interval value even when saic~ memory means is deenergizec~.

~ lother aspect of the invention includes d register for n~nitorlng electrical-power de~nan~ made upon alternating current mains, com~rising: (a~ means, res~onsive to power conSumed frolrl said mains, for computirg values of electrical-power de~nand over a succession of d~Nand-mon:itoring intervals; (b) means, responsive to said computing means, for determinir~3 a ~imln~ demand-~onitorirlg interval value of the electrical-power d~ nd; (c~ rneans, responsive to said dernand interval determining means, for encoding said ~naximum deJnans.-monitoring interval value in accordance with an error-detecting and error-correctir~3 code; (d) nonvolati.Le read/write memory meansr responsive to said encodin~ n~ans, for storing said encoded maximum demana-monitoring interval value even when said memory means is deenergi~ed; (e) means, coupled to said storing meansl for decoding said encoded maximum demand-monitoring interval value; (f) means, responsive to said decoding means, for produciny an error indicatiorl when said encoded M~ximlrm demand-monitoring interval value contains a particular error, and (g) means, responsive to said error indicating means, for disabling said canputirlg means in response to said error indication.
Yet another aspect is attained by a register for monitoring electrical-power d~nand made upsn alternating current mains, com~rising: (a) means, responsive to power consumed from said mains, for co~sutin~ values of electrical-power demand over a succession of demand-monitoring intervals; (b) means, responsive to sai~ con~uting means, for determining a maximwn demand-monitoring interval value of the electrical-power demand, said maxim~n demand-morlitoring interval value being encoded as a set of digital data bits; (c) means, respons.ive to said d~land interval determining means, for encoding said maximum deman~-monitor.Lng interval value in accordance with an error-detecting and error-correctir~ code; (d) nonvolatile read/write memory means, responsive to said encodir~ means, for storing said encoded maximum demand-monitoring interval value even when said memory means is deenergized; and (e) means, co~pled to said storir~ means, for decoding said encoded maximum demand-monitorir~ interval value in accordance with said error-detectin~ and error-correcting code and for detecting any double-blt error containecl in saio en~ode~ set of digital data bits.

~2'~ S

- 5a -A further aspeet is attaine~ by d register for Inonitoring electrical-power demand made upon alternating eurrent mains~
comprisiny:~a) mRans, responsive to power eonsumed from said mains, for eomputing values of electrical-power de~nand ov~r a suecession of demand-monitoring intervals, said com~uting means ineluding:
(i~ sensir~ rmeans for providing pulses at a rate substantially ~roportional to eonsu~tion of eleetrieal energy in said mains;
~ means for definir.g said sueeession of dernand-monitoring intervals in accordance with the Lrequency of the alternating-current mains;
(iii) means, responsive to said sensing means an~ said defining rneans, for aceumulating sai~ pulses generated during each said dernand-rnonitorir!g interval; and (iv) means, responsive to said aceumulating means, for generating said demand-rnonitorilly interval values of eleetrical~power demand; (b~ means, res~onsive to said eomputing rneans, for determining a maximum ~emand-monitoriny interval value of the elee-trieal-power demand; and (e) nonvolatile read/write memory means, responsive to sai~ determining ~leans, for s~oring said m~ximl~n demand-monitoring interval value even when said memory means is deenergized.
Another aspect is attained by a register for monitoring eleetrieal-power demalld made upon alternating eurrent mains, eomprisir~: (a) means, res~onsi.ve to power consurned from said mains, for eon~uting values of electrical-power demand over a suecession of demand-monitorirlg intervals; (b) means, responsive to said camputir~
means, for determining a r:rcKilllurlldemalld-morlitorirlg interval value of the electrieal-~ower d~nalxl; (e) reset means for gener~tir~ successive reset indications; (d) first means, responsive to said determining means and said reset means, for determinil~ a current mc~xim~n demand-monitor.ing interval value of tile electrieal-power ~emand occurrir~ subsequerlt to the most recent of said sueeessive reset indieatiorls; (e) means, responsive to sai~ first means, for encoding each said current mc~x.~l~rldemand-nlonitoring interval value in aceordanee witl~ an error-detecting ar~ error-eorreeting ccde;
(f) non~>latile read/write memory meanst responsive to said er~oding rneans, for storing said eneoded maximwn de~nand-monitoring interval :..

~2~3~

- 5b -value even when sai.d memory means is deenergized; an~ (g) addressing means, responsive ~o sai~ encodir~ means~ for cclusir~ said storir~3 means to store only sai~ encode~ current maxlmullldemand-monitorillg interval value determined sin~e sai~ most recent of said successive reset irldicat .iOllS .
Yet a further aspect is attained by a register for monitorirlg elec-trical-power ~eman~ mdde UpOII alternating current mains, cor~)rising: (a) means/ responsive to power cons~ned from said mains, for cor~uting values of electrical-power deman~ over a succession of demand-monitoring intervals; (b) means, responsive to said ccTputing means, for determining a max~num demand-monitoring interval value of ~he electrical-power demal~; (c) reset means for generatir~ successive reset indications; ~d) first means, responsive to sai~ detern~ning means and said reset means, for determinir~ a m~ximl-rn billing perio~
value of the eLectrical-~ower demand occurriny between each pair of successive reset indications; (e) means, responsive to said first means, for ca1culating a runnilly sum equal to the summation of the m~ximl~n billing period values; (f) enccding means, responsive to said running sum r~ans, for er;coding said running sum in accordance with an error-detecting and error-correcting code; (g) nonvolatile rea~/write memory means, responsive to said encoding means, for storing said encoded running sum even when said memory means is deenergized; and (h) addressing means, responsive to said encoding means, for causing said storing means to store only the most recent value of said encoded running sum.
Another aspect is attained by a re~ist~r for Inonitoring electrical-power demand made u~)on alternating current mains, coloprising: (a) means, res~onsive to power cons~ned from said mains, for c~nl~u~ing values of electrical-power demar~ over a succession of demarld monitoring intervals; (b) mRans, responsive to said computing means, for determining a maximum demand-rnonitoring interval value of the electrical-power demand; (c) reset means for generating successive reset indi~ation~; (d3 first mealls, r~sron~ive to said determining means and said reset means, for determining a ~xi~l~ billing period value of the electrical-power demand occurring between each pair of ':,~,,,J~
:.

- sc -SLc~eSSiVe reset ir~ications; (e) seconc~ eans, responsive to said determil~ng mean~s and saicl reset means, for determining a current maxirnum demand-monitoring intervdl value of the electrical-~ower delnand occurril~ subsequent to tne most recent of said su~cessive reset indications; (f) means, responsive ~o said first and second means, for calculatir~ a running sum equal to the sur~nation of each said maximum billing perioc~ values and said current ma~imum dernand-monitoring interval value; Ig) means, responsive to said runnincJ sum means, for encodir~g said runr~ng swn in accorda~e with an error-detectirg and error-correcting code; (h) nonvolatile read/write memory means, responsive to said encoding means, for storing said encoded running sum even when said mernory means is deenergized; and (i) addressing means, responsiv~ to said enco~ing rneans, for causing said st~rirg rneans to store only the most recent value of said encoded running s~un.
Another aspect of -the invention is attained by a register for monitorincl power d~nand made upon alte matir~ current mains, cornprising: (a~ first pulse generating means, responsive to power consumed frosn said mains, for generating first pul æ s dt a rate substantially proportional to consurnption of electrical energy froln saià mains; (b) seconcl pulse generatiny means for generating seconc pulses at a rate in accordance with the frec~uency of the alternating-current mains; (c) microprccessor rneans, couple~ to said first and second pulse-generatin~ means, for defining successive ~emand-rmonitoring intervals, for calculating a numerical value in~icative of the power delnand made durir~ e~h successive demand-rnonitoring interval, an~ for determining a maximum nulnerlcal value indieative of the power deman~; (d) pulse-initiator means, coupled to said microprc~essor means, for providillg energy pulses at a rate proportional to e~x~l of said n~nerical values; and (e) nonvolatile read/write mernory means, coupled to said microprocessor rneans, for storin~, even wllen deenergizecl, said maxirmuln n~nerical value.

~32~35 - 5d -A further aspect is attained by a r~ister for r~nitoring ~ower denland made UpOIl alternatirg current maills, comprisir~: ~a) first pulse generating means, responsive to power con~ frolll said mains, for generating first pulses at a rate substantially pro~ortlonal to consumption of electrical energy from said mains; (b) second pulse generatir.g means for generating second pulæ s at a rate in accordance with the frequency of the alternating-current mains; (c) microprocessor means, coupled to said first and second pulse-generatir~ means, for defining successive demand-monitoring intervals, for calculating a numerical value indicative of the power demand made durlng each successive dernand-monitoring interval, for determining a maximum numerical value indicative of the power demand and for encoding said maximurn numerical value in accordance wit~ an error-detecting and error-correcting code; and (d) nonvolatile read/write memory means, coupled to said microprccessor means, for storing, even when deenergized, said encoded m~in~lm numerical value.
Yet another aspect is ~tt~in~d by a metho~ of monitoring electrical-power demand made upon alternating-current mains, comprising the steps of: (a) IT~asurin~ electrical energy consumed from said mains; (b) computing values of electrical-power dernand from said measured electrical energy over a s~cesslon of time intervals;
(c) deterrnining a maxirnum value of electrical-power demand frorn said computed values; (d) encodin~ said maximum value in accordance with an error-detectir.g and error-correcting code; ~e) storing said encoded maximum value in a nonvolatile read/write memory means which, even when deenergized, retains said encoded r~Yi~TTn value; (f) retrieviny said stored encoded maximum value from said nonvolatile reaq/write memory means; (g) decodir~ in accordance with said error-detecting an~
error-correcting code said retrieved, stored enco~ed maximurn value to produce a decoded rnaximum value; (h) producing an error indication when said decoded maximum value contains a particular error; and (i) preventing the execution of step (b) in response to said error ir~ication of step (h).

- 5e -Another aspect is attained by a method of monitoring electrical-power demand m~ie upon alternating-current mains, canprisir~
the steps of: (a) measuring electrical energy cons~uned from sa1d mains; (b) canputin3 values of electrical-power dernand from said measured electrical energy over a succession of time interv~Ls;
~c) determining a maximum value of electrical-power demand from said computed values; (d) enco~in~ said maxirnwn value in accordance with an error-detectir~ and error-correctirlg code; (e) storir~ said encoded maximum value in a nonvolatile reaq~write memory means which, even when deenergi~ed, retains said encoded m~ximl~ value; (f) retrievin~
from sai~ nonvolatlle read/write memory means of step (e) sai~ stored er;coded maximum value in the form of a set of data bits; (g) decodir~
said set of data bits in accordance with sai~ error-detecting and error-correctir~ code; (h) detecting whether said decoded set of data bits contains a particular error; (i) detennining, if a particular error has been detect~d, ~hether said particuLar error is a sir~le-bit error, a double-bit errort or a Inultiple-bit error; (j) corre~ting, if said particular error is a single-bit error, said sil~31e-bit error in accordance with said error-detecting an~ error-correctin~ code;
(k) generatin~, if said particular error is a double-bit or mulitple-bit error, an error ir~i~ation; an~ (1) visually displaying said error indication of step (k)c Yet another aspect i5 att~i n~d by a method of monitoring electrical-power demand made upon alternatir~-current mains, con~prising the steps of: (a) rneasuriny electrical enexgy cons~ned from sai~l mains; (b) generating first pulses at a rate substc~rltially pro~ortional to said measured consurrptiorl of electrical energy; (c) generatiny successive reset pulses; (d) establishir~, before said generation of each successive reset p~se, successive demand-rnonitoring intervals;
(e) ~c~ ting said first pulses gellerated durir~ each demand-monitoring interval; (f) calculatiny ~roln said accumulated first pulses a value of electrical-power demand mc~e duriny each of said successive demand-monitoring intervcils; (g) deten~ning a max~nwn value oE said values of electrical-power demand; (h) encoding said maximum value in accordance witll an error-detecting and 1~

12¢:13'~5 -- 5f --error-correcting code; (i) storing said encoded maxirnw,l valu~ in a nonvolatile read/write mernory means, which, even when deenergi2ed, retains said enc~ied maxlrnwll value; (j) resetting to a zero value saicl stored enccded maximum value upon a generation of the next successive reset pulse; and (k) visually displaying saic~ maxim~n value of electrical power dernand.
A further aspect iE attained by a method of rr.~nitoring electrical-power derr~ncl mdde UpOII alternating current rmains, corn~rising the steps of: (a) measuring electrical eneryy conswiled from said mains; (b) generating first pulses at a rate substantially pro~ortlonal to said measured consumption of electrical energy; ~c) generating a succession of reset pulses; (d) ~ hi ng successive demand-monitoring intervals; (e) accumulating said first pulses generated during each demand-monitoring interval, (f) calculating frorn said accumulated first pulses a value of electrical-power demand made during each of sai~ successive demand-monitoring intervals; (g) prior to the generation of the first of said reæt pulses, deterMining a maximwn value of electrical.-power demand; (h) encodiny said rnaximum value of step (g) in accordance with an error-detecting and error-correcting code; (i) storing sai~ encoded maximum value of ste~
(h) in a :Eirst location of a nonvolatile read/write memory means whic~h, even when deenergized, retains said encoded maximuln value;
(j) upon the generation of the first of said reset pulses, transferring said stored maxirr,um value from sai~ first location to a second location of said nonvolatile reacl/write memory means; (k) u~on the transfer of sald store-l maxullur,l value ~rol~l saic~ first location to said second location in accordance witll step (j), resetting to zero said value stored in saià first location; (1) upon the yeneration of each succeedir~ one of said reset pulses, determining a new maxirnum value of electrical-power demand; (m) UpOII determirling said new m~3xirn~lm value, encoding said new max:imum value in accordcmce with said error-detecting and error-corrt~ting code; (n) storin~3 said encoaed new maximum value in said first location of said nonvolatile read/write mernory means; (o) upon the generatiGn of each succeeding reset pulse, generatin3 a sum of values e~ual to the swQmation of said ~ . .

~3~5 5g -m~Yimwn value an~ each said new maximum value for storir.g in sai~
first and second locations of said nonvolatile read/write memory means; (p) upon generating each said sum, repldcing saia value stored in said seeond location with the most recent value oE said swn; and (q) upon repla~ing sald value storea in said secon~ location with the most reeent value of said sum, resetting to zero said value stored in sai~ first loeation.
Yet another aspeet is attained ~y a method o~ monitoring electrical-power de~and macte upon alternating-current mains, eom~rising the steps of: (a) measuring eleetrical energy consumed from said mains; (b) generating first pulses at a rate substantially ~roportiollal to said measured eonsumption of eleetrieal energy; (e) generating a suecession of reset pul æ s; (d) es~ah1i.~h;ng successive demand-monitorir~ intervals; (e) aecumulating said first pulses generated during eaeh deman~-mollitoring interval; (f) caleulating from said ~el~n~-lAted first pulses a ealeulated value of electrieal-power demand made dùring each of saict suecessive demanct-monitoring intervals; (g) prior to the generation of the first of said reset pulses, ar~ at the en~ of the first of said suecessive demand-monitoring intervals, encoding said ealeulated value of electrieal-power demand in accordance witn an error-cteteeting and error-correeting code; (h) storin~ said encoded calculated value in a first and second loeation vf d nonvolatile, reac~write Inemory which, even when deenergizecl, retains said encoded ealculated value; (i) at the end of eaeh suecessive demand-monitoring interval before the generation of the first of said re~set pul.ses, deterlnini~g whether the most recent ealculated value is c~reater than said eneoded ealculatt~
value stored in said first and seeond locations; (j) if the mos-t reeent ealculated value is l~et~r~ined to be greater than said calculated value stored in said first and seeond locations, deterrninating a difference between saict most reeent caleulateu value and said encoded ealeulated value stored in said first loeation;
(k) generating a sum eclual to said difference ancl said eneoded ealeulated value stored in said seeond loeation; (1) replaeing said eneoded ealeulated value stored in said second loeation with said ~3Z~5 generated sum; ~m) replacing said enco~e~ calculated value stored ln said first location with said most recent calculateu value deter~ ned to be greater in step (j); (n) upon the generatioll oL the first of said reset pulse, resetting said encoded calcu:Lated value stored in said first lo~ation to zero; (o) before the generation of each successive reset pulse, determining whether the most recent value of said value of electrical-power d~nan~ calculated is greater than said er~oded calculated value stored in said first location; (p) if said st recent value of electrical-power derr~nd calculate~ is deterinined to be greater than said er~oded calculated value stored in said first location, generating a difference between said most recent value determined to be greater and said encoded calculated value store~l in said first lccation; (q) upon generating said difference, generating a sum of said difference and said encoded calculated value stored in said second location; (r) upon generating sai~ swn, r~ ring said encoded calculated value stored in said second location with said generated sum; (s) UpOII replacing sai~ encode~ calculate~ value store~
in said second location with sald generated sum~ replacing said encoded calculated value store~ in said first lfcatiQn wi-~l sai~ value deterrnined to be greater; and (t~ upon the g~leration of each successive reset pulse, resetting said encoded calculated value stored in said first location to zero.

B~IEF D~S~ ~r:[~N Oh''l~l~ Dl~AhIN~S

Various objects, features and attendant advantages of the present invention will be more fully appreciated as the same becomes better underst.ood from the following detailed description of the present invention when considered in connection with the accor~anyin drawings, in which:
Figure 1 is a functional bloc,c diagram of a preferreu en~odiment of the present invention;

. .

33~
_ 6 ~

Figure 2 is a fun~tional block diagram of a p~eferred hc~im~nt o mic~ ccessor 100;
Figure 3 shows dia~rammatically the relationship of Figures ~ and 3B, S ~igures 3~ and 3B are a schelatic block diagran of the preferred e ~ im~ht shcwn in Figure l;
Figuse 4 shows diagrammatically the relationship of Figures

4~ and 4B;
Figures 4~ and 4B a~e a flcw chart of main routine 400;
Figure 5 is a flow ~hart of ~ISR subroutine 430;
Figure 6 shcws di~J,~ ;c~lly the rela~;on~h;~ of Figures 6~ and 6B, Fi~ures 6A and 6B ase a flow chart of TqM~ subroutine 432;
Figure 7 is a flow chart of EDEP ~b~cuLine 434;
FiguIe 8 is a flow chart of DI9CR su~routine 436;
Figure 9 is a 1OW chart of P~DG subroutine 438;
Figure 10 is a flow chart of tLmekeeping Lnterrupt s~broutine 1000; a~
Figtsre 11 is a flow chart of error-detecting and error-~L.tcLi~ subroutine 1100.

~r~Tr.~n ~K~ C~ CF q9E ~ ~K~U EMEODIME~T

The preferred ~mhn~;r~nt of the s~l~^d-state de~2nd re~ister cf the pre~t invention is shown in functional block-diagram form Ln Figure 1. The present invention, desisnated generally by f~fer~ce numeral 10, is based around a mi~ Loce~ 100, which is of conv~nt;or~l design ar~ preferably is a Fairchild F3870PL
single-chip micL~ ~uL~r ~ade by Fairchild C2mera & InsL.~.~,t Corporation, Mountain View, California, and described in a publication entitled "F3870 Single-Chip ~i~L~eul~Ler -Fairchild Mi~ ter FamLly". It- shculd be noted that ot~er types of nLt~ ~yLC_~5Y~LS can be emDloyed in the present invention.
Mi~L~Lo~s~or 100 Ln the preerred form is an eight-bit, metal-cxide-sPmi~ ~Y~ r processor which c~ execute an instru~tion set of more than 70 n~mm~n~, has 2,~4~ bytes of read-cnly meTory, 64 bytes of s~ratchpad r~d~l~ access m~mory, a progr.~ le bin2ry timer, fcur eight-bit, input/altput. ports, and an Lnternal clock.
~i~L~ucessor 100 and a nonvolatile read/write memory 152 tcgether ccmprise a circuit which defines a series of consecutive S demand-monitoring intervals, calculates or ccmDutes the electrical-pawer demand in~uLred during each demand-monltoring interval, an~ stores ccmputing constants and computed results.
Nonvolatile read/wri~e memory 152 is nonvola~ile in the true sense of ~he word - that is, it retains the data stored in it even if energi2ing electrical power or potential is removed from the memsry's power-su~ply ~nnin~ that is, when it is deenergized).
Nonvolatile read/write memory 152 is preferably a mcdel 2055 512-bit (64 x 8), metal nitride-oxide-silicon, electric~11y alberable, read-cnly nK~n~ry, m~nl-f~rtured by the ~CR Corporation, cf Dayton, Ohio, and described m a data sheet pUhl;ch~ by that cx~x~ny and entitled "~X~R 2055 512 BrT (64 x 8) W~D P13n~U~LE
~CM". Stored data may be read frc~ this device a ~i n i~ Of 1011 times without having ts be refreshed, and data storage is nDnvOlatile for re than lQ years. Althsu~h this device is intended for use a~s a read-mostly ~emory, data can be erased and rewritten as many as 104 times~ It should be noted that other suitable nonvolatile mi3n~ries (not requiring backup potential to retain s~rc~ge) can be emplsyed in the present invention.
Mi~ ro~-~s~, l00 and nonvolatile read/write memory l52 ' ~ca1e via a bidirection21 data bus l50. Data flow bet~een micrcpro-essor l00 and bidirectional data bus l50 via an Lnput/output port of ~i~L - y~U~a~L 100 .
Address, clcck c~nd erase/write-cxxm~an~ sign~ls flow from another input/output pcrt of mucrcprocessor l00 to nonvolatile read/write n~nory l52 via a set of signal lines l36. (Four of the ~n~in~l ~ of this input/output port and of signal lines l36 also present signals to display drivers l36, as is described below.) As m~ntioned abcve, c~ as discussed ln greater detail belcw~
mi~L~yLo~ssor 100 ha, four eight-bit, in~u~/cut?ut ports with eight t~r~in~1~ each ~cne t~nmin~l for each bit). One of these 7~

~ ~3~

input~ou~1?ut ports is used for dat~ transfer betwee~
mlcraprccessor 100 and nonvolatile read/write memory 152, and oniy for that ~ ose. The other ports are emplcyed to perform mc~e than one purpose, and the different data termlnals of a particular port are m many cases used to present or accept signals that are unrelated to those at the remainlny ~nmi~lc of that port. The choice of using a particular port c¢ data ~Prmi n~l cf a port to present or ~çcept a particular signal or signals is arbitrary.
Also c7nnP~tP~ bo I/0 por~ ter~ m als of micrcprccessor 100 are end-of-bi~in~- ~ riod ~9osp) reset switch 102 and a ~ of error-fl~g-clear ~FC) ~rmin~l~ 104. Swi~cb 102 provides a means of generating an end-~f-billing-period pulse which alerts mi~.~y~ccess~r 100 that a billin~ period has ended. Although ~witch 102 is shcwn ~ a r-ml~lly Gperated, n~rm~lly cp2n, n~xnentary-contact ~hJ~l~h~ switch, other switching devices or c7rcuits can be used to generate this pulse.
Error-flag-clear tPr~;n~l~ 104 provide a means of clearing an error ;n~;c~;on or flag which is set Ln nonvolatile read/write n~nory 152 when a data-prcc~sci~ error has occurred and has been de~L~ hen an ersor has been detected the error flag may be cleared by placing a jumper wire on ~armi n~1 104 while the register is unpowered. The register is then pc~er~d up and the jumper re~oved prior to inst~ ti~n and ~ ,t of cperation of solid-state demand r~ister 10~
C~-~.æ L~d to an external-reset pU~ET) hPr~ l of micro-y~essoL 130 vLa a signal line 106 is a pcwer loss/reacquisition level generatDr 108. Power-loss~reaoquisition level generator 108 generates a lcw level when the voltage across a pair of alternating current mains oon~uc LOL S 178 and 180 decreases to a preselected level. ~his pcwer-loss level is applied to the external reset tPr~; n~1 of micrcprocessor 100 via signal line 106 and Lnstructs the mic~yLC~52 JL that a voltage dip or power failure is occurring. ~pcn receipt of the po~er-loss level, mi~.~y~o~es~uL 100 tenminates the demand-monitoring interval in progress. After the voltage across mains conductors 178 and 180 has returned to an æ ceptable level, poher-loss/Leacquisition level generabor 108 generat~s a ~ower reacquisition level which , ~
..f 3~

instructs micro~rocessor 100 to initiate a new demand-monltoring interval. Pcwer-loss/re~cquisition level g~nerator 108 therefore ensures that valid electrical-power dema~d informatlon is o~?uted despite the o~currence of ~ransien~s across the powex mains.
As ~;c~.~cP~ above, solid-sta~e demand register 10 can function in one of several cperatin~ mçaes (~ tive, cumula~ive~ continuous-cumulative, noncumulative and cumulative, or noncu~ulative and continuou~ tive). A pair of dem~nd~register mcde indicators 112 provide a visual jn~ t;~ of whether solid-state demand ~egister 10 is operating in the ~. 1 Ative or a cu~ulative mcde or in ~oth the no~ tive and ~he cumulative madel Demand~reyister m~de indicators 112 receive driving signals frcm tPrmin~l~ of an input/output pc~t of mi~L'~foCe3~UL 100 via a pair of signal lines llo, Dema~d~re~ister m~de indicators 112 are circuits that employ conventional light~e~itting diodes driven by siliccn switching transistors.
Solid-state demand register 10 also incln~ a pulse initiab~r 116. When micrcproce~sor 100 de~Prmin~ that ~he ~ ~.~t:ion of a ~LC~L~ ly alterable pre~elected incre ~ tal amount of ~lectrical e~ergy from the alternating current mains has cL~uLr~d, it sends a signal to F~lse initiator 116 via a signal li~e 114. These pulses appear at a set of pulse-initiator outputs 118, which employ t~e RY~ format e~ployed by the ~nited States electric-utility-neter industry. ~hese pulses can be applied to a data L~L~ef or simular device c~nn~cted to p~lse-initiator outpu~s 118. Dat~ formats other than RYZ can be employed.
There are five computing c~sLanLs which the circuit ccmprising microprocessor 100 and nonvolatile read/write memory 152 empJoy. These are: constant 1 the number of pulses to be seneratcd by pulse initiator 116 when an increnental amount of electrical energy has been c~n~ ~^1 (fro~ 0.1 to 10 pulses per ir~c ~, for ex~mple one meter disk revolution); oonstant 2- the length of the demand :~terval (for example, from 1 to 99 minutes);
oJ.~ t 3 - a disk w,lsk~- which defines hcw many watt-hours (from 0.1 to 99.9 watt-hours, for example) constitute the incremental amcunt of consu~ed elec~rical ~nergy, norm211y defined , ~

~f~32~3~

3s one met~r disk revolution; constant 4--demand-re~ister cperating mcde or modes (1 = ~nnc~nl~tive; 2 - cumulative; 3 =
continuous-cumula~ive; 4 3 l~on~umulative and c~nulative, or 5 -roQ~-m~ tive and continucus~cumulacive); and constant S~-decimal-point pcsitions.
T~ese oomputing constants are programmed or selected by mea~s of a register pro~ra~me~ i24, which can be brousht into ~yr~ ble crmm~nicatlon with input/output port tPrm;~ O~
mioLu~ocessor 100 via a pair of sig~31 lines 120 and 1~2.
Register ~oy~ r 124 in a preferred Fmho~lm~nt ccmprises three bin~ ~G~ed 3e~imal ~hl~h ~e31 s~itches and a parallel--Ln serial-out shift regis~er. ~i~Lc~Lc~e~Jr 100 prcvides clock~ng pulse5 to the p r~1lpl-in seri~l-out shift register of re~ister P~C~L ~r 124 via signal line 122. When the shift reglster receives ~l~r~;rg pulses, it converts three-di~it, parallel, bLnary cod~ c~mal data generat~d by the thu~kwheel swi~c~es Lnbo seri l form~ ~he seri~l data are then transferred to an input/out~ut port t~rmi~1 of mi~L~,ocessor 100 via signal line 120. Mi~L~ ccessor 100 then converts these tx3nD~ti~s constants back into par~l~el binary-coded-decimal form a~d presents tht~n tD
the data inputs t~ n~nvolatile/reat~^write me~ory 152 v-ia bidirectional dat b~s 150 for storage in a designated d~ta-storage lacation. It shalld be observt~d that other dat~
formats c;~n be employed by register ur~, -.r l~4.
Ccmputing collsL~lts and ccmFuted results t~an ~e displ~yed vlsually t~n a ft~lr-digit, s~v~. sc~ment, canmon _a~ c~e, ~ltiple~ed LED display 132O Da~a appearing at t~rmi n~l ~ of another input/output p~rt of mlcrt~prt~cessor 100 are presented to a dis?lay deccder 128 via a set of signal lines 126. me data bits which flow frtm ml~L~yLoce~L 100 to dis~lay decoder 128 via ~e set of signal lines 126 are in binary-coded-decim21 (BCD) form.
Display deccder 1~8, which is preferably a type CD4511 CMDS
ECD-to seven-se~ment d~coder IC, made ~y the Solid-State Divisicn of the ~ Corporation, Somerville, New Jersey, c~nverts the dat3 bits into a fo~m com~at:ible with display 132.
The cathodes of the s~yments o~ each of four di~i~s in display 132 are tied oogether ar~ are connected to each of a set ~ 11 --o dispLay drivers ~38 via an~ther set of signal lines 134. Each signal l~ne of the set 134 is connected to the colle~bor o~ the aFprcDriate one of displ2y drivers 138, which are 5iliccn Darl mgton transistors. The enitters of ~hese Darlington transistors are co~nec~ed ~o ground via arD~her set of signal lines 140~ The bases of ~he ~ Darlington transistors receive drive signals generated within micropro-es~or 100 and pres~lted to input~output-port ~rm;n~l~ of mi~c~ro~essor 100 via another set o~ signal lines 136. m ese are digit-enable signals which allcw dispLay dxivers 138 to ~ctiva~e apprcpriate digits o~ display 132 at aFpropriate times~
Darl;ngbon transistors, which are pre~erably mcdel ME~hl4 devices ~ad~ by the ~3borola Co~poration of Phoenix, Arizonar are used be~ause the input/ouqput port which prcvides ~hem with base drive has lLmited curr~nt-sourcin~ c~r~hi~ity. m e large current gain of suGh Darling~on transisbors ~n9;d~r~hly reduces the amount of ba~e drive required for adequate c~rrent flow ~hro~gh the 5~nlc of display 132. A display contro.ller 142 generates a control signal which is provided to display decoder 128 via anather sisnal line 144O Display oQntroller 142~ which is preferably a mQdel ~L3330Y ~ ~ e~ made by the Sprague Electric Company of Waltham, ~Cc~h~lc2tts~ a ~u~s~sitive device wnich inhibits dis,play decod~r 128 from providiny s~v~ æ ~ t-o~J~ ible signals to the an~des of the segments of display .132 via a set of signal lines 130 when ambient light levels are below a preselected threshold value. Display controller 142 therefore inhibits display 132 from glowing in the dark. This inhibition function minimizes the possibility that solid~state demand register 10 will attract un~anted attention 3~ during periods of darknes3. Should it be desire~ to actuate display 13Z when ambient light levels are belcw the pre æ lected threshold value, the output of a suitable source of light (such as that of an energi~ed fl~hlight) c3n be directed to irradiate display ccntroller 142.
An cpb3electronie pulse ge~erator 148 æ ts in concert with an eddy-current induction motor 166 b~ generate pul~es at a rate proportional to the consuTption o~ electrical energy fron Fcwer S

mai~ corlductors 178 and 180. me pulses aenerated by o~boelectronic pulse generator 148 and eddy-~urrent md~ction motor 166 a~e presented via a signal line 146 t~ an input/cutput port ~Qnmin~l of micLu~Lco~sor 100.
With reference to Figures 1 and 3, eddy-current ind~ction motor 166 c~r~rises an eddy~lrre~t disk 168, a shaft 1-/0 ~ whi~s eddy~current disk 168 is at~ached, a field windi~g 172 ccnnected across pcwer ~aLns U~ldUC~JL 5 178 and 180, and ~n ed2y-current winding 174 placed in series with cne of the mains w-~C~u~S (in this case, ~ hUL 178). Field windin~ 172 sets up a ma~netic field in the vic~ity of eddy current disk 168 which is sUL.1~ y ~/LI~il.JL tiC~ t:o the volta~e across p~er mzLins C~IKjUC~OLS 178 and 180. Ed~urrent windirx3 174 generates a magnetic field which sets up an eddy current in eddy~urr~t disk 16~ rrent flows tbr~h mains ~n~:tors 178 a~d 130 and the c~ a.~r's lcads. An a~ y disk 158a (sha~n in outlirle in Fi~ure 1~ ma~ also be ~unted on shaft 170.
m e anplitude of the ~nduced ed~y current depends cn the amcunt oi: current drawn by the custcmer's load. An. eddy current in eddy-c:urrent disk 168 sets u~ a msgnetic field which interac~s with that p~cd~c~d by field wi~ding 172 to cause rotation of eddy-current disk 168 at a rotaticnal ~elocity prc?ortional to the amount of electrical energy ~eing c~n~ed by the customer's load.
Eddy ~ULL~lt disk 163 or ~IlYiliAry disk 168a have one or re hole or cpenin~s (not shown in detail). These ~n;r~$ make it possihl~ for optoelec~ronic F~Lse generator 148 b~ generate pulses at a rate prcportional bo the w~ ion of electrical enersy without ~eing in ~ hAn;~l contact with eddy-current disk 168 or allYil;Ary disk 168a. Optoelectronic pulse generator 148 i~ c two lisht emitters 302 and 304 (which can be, for examc~e, light-emitting diodes of conventional design) ~unt~d adjacent to e~h other and ne~r one face o~ disk 168 cr 168a. Optoelectronic pulse generator 148 alsc~ inr~ P~ a pair of photodetectors 306 and 3G8 Iwhich can be ~u~ ~ dnsistors, pho~io~P~, or similar 3S ph~us~itive devices of oonventiûnal desiyn~ mcunted adj~cent to each o~her and near the oppcsite ~ æ e o~ eddy-current disk 168 or 16aa .

'.~' 3~

- 13 ~

m e pairs of ligh~ emitt~rs 302 and 304 and phO~Cde~C~OLS
306 arx3 308 are a~igned with the disk so that the photodetectors 306 and 308 are alternately shado~d by disk 168 or 168a and irradiatea by output of the light .enitters 302 and 304.
S Photodete~bors 306 and 308 are irradiated by the ou~put of light.
emitters 302 and 304 wh~n an opening (not shcwn) of diCk 168 or 168a eccupies the ;pace bet~een the c~ps i~ely mounted pairs of lisht emitters an~ ~I.oL~deL~JLs. Phobodetec~ors 306 an~ 308 are shadowed wher~ the sE?ace betwe~ the;l and light emitters 302 and 304 is c~:ç ri~l by a solid region of disk 168 ar 168a.
Optoelectrc:nic pulse generator 148 furt:her ;~1IJr1PC a switching circuit 148 driven by E,I~Lodete~,~Ls 306 ar~ 308.
Switchir~ circuit 148 ge~Rrates an output pulse each time an ~ening in disk 168 cr 168a enters arx~ exits the region betwe~
the light dtters 302 and 304 as~ u.s 306 and 308.
Pl-s:)~el~ L s 306 an~3 308 ar~ switching circuit 148 function in 5uch a =ner that the generation of cutput pulses due to "jitter"
of ed~-current disk 168 is ~uwLessed. "Jittern is a ph~
which can c~cur when ed~y~UL~C:lt disk 168 osciilates abcut one Foint Ln its rotation. These oscilla~;cns wculd othe~wise be mistaken for the rotational passase of a number of ç~pnln~s of disk 158 or 16~ during relatively rapid rotation o eddy-current disk 168. Ihe pulses yenerated by the switching circuit in cpb~electronic pulse generabor 148 are l~ted and are pLo~e~ by - microprccessor 100 to derive values of electric?l-po~er demand.
Referring again to Figure 1, various stages of solid-state demand r~gister 10 require regulated or unregulated direct current voltages of particular amplitudes and polarities. These voltage requirements are satisfied by a power supply 156, which derives regulated and unregulated direct current voltages frcm the v,oltage across alter~ating current voltage mains conductors 178 and 180.
The direct current voltages are provided to the ~ppropriate stages at a number of outputs 158.
Power supply 156 al~o generates a train of pulses which are derive frcm the alternatin3 cur~e~t signal flowing in mains cond~ctors 178 and 180~ This pulse train has a repetition rate ~3~

related bo the alternating current mains frequen~y and is used for t~ming purposes by micrcprocessor 100. The pulse train is appLled to an ~xternal-interrupt Lnput of micrcprocessor 100 via a 5ignal l m e 154. These pulses function as interrupts which direct ~he micrcprccessor to enter and perform an interrupt subrou~ine whicn is described in greater detail belcw.
An end-of-interval keyer 162 generates an end-of-interval pulse when each demand-~onitoring interval ends. End-of-interval keyer 162 generates the end-of-interval pulse when it receives a pulse frc~ 3n~ther input/output pcrt t~nni n~l of mi~L~p~o~ss~r 100 via an~her signal li~e 160. ~he end-of-interv~l pulse apFear across keyed output t~nmt~ 164.
Solid-state demand register 10 c~n also include a ~h~ni~i ener3y-usa~e register 176, which botalizes a~d displays visually the aqcunt of electrical energy (for ex2mple, in kilowatt-hcurs) .~ by the ~ustc~er load. ~rh~ni~l er.ergy-usage register 176 is driven by a shaft 1?0 to which it is coupled (shown by dashed lines). As stated above, sha t 170 is attached to and p~ L-S eddy ~rL~t disk 168 and al~;l;~ry disk 168a.
Eddy-current disk 168, ~ ry disk 168a and shaft 170 thus rotate t~gether. In this manner, shaft 170 provides the tor~ue required to drive ~rh~n;n~l energy-usage register 176.
me architecture of microprooessor 100 is now ~ s~ with r~fer~.ce to Figure 2. While m~LC~O~eàSaLS are well known, hi~hlig~ o~ ~ome signifi~t stages and features of mioLcprooeaa~L 100 are now discussed.
m e heart of micrcpro-essor 100 is an arithmetic logic unit tAL~) 200. Arithmetic logic unit 200 performs the arithn~etic cperations of binary addition, decim21 adjustment, add with carry, and de~ t, as well as the logic cperations of AND, QR, l's L and shift left and right. A general-purpose ~ tor and stat~lc register 204 receives inputs for arithmetic logic u~it 200 and s~ores in its a~Y~ tor section the results o oFerations perfor.med by arithmetic logic unit 200. Arithmetio logic unit 200 and ~n~ tor and status re~ister 204 ~ ~ "~ ate ria a bidirecticnal pcc~essu~ bus 2Q2, which is ~he main data bus of micraprooessor 100, a~d a unidirectional data bus 206.

.

~icropr~essor 100 also ; ~rl ~ a scratchpad 212, -~hich is a 64-word, eight-bit, general-purpose randcm,access memory.
Associated with scratchpad 212 is an indirect scratchDad address register 208, which can hold t~o octal digits. As stated above, read~cnly me~ory 220 stores the cperati~g program of mi~ Lc~esso~ 100 ~ who~e operation is described in great~r detall with respect to Figures 4-11. Read-cnly me~ory 220 can be p~CyL~ with UD to 2,048 eight-bit words. Read-only me~ory 220 is addressed via an adder~increnenter 214, a bus 216, a set of read-cnly me~ory address registers 218, and bidireotional æ O~SS~ ata bus 202.
Mi~ ess~. 100 also inr~ e~ a se~ of four mpu~/cutput ports 242 (in~ut/output por~ 0), 244 (input/ou~put p~rt 1), 246 ~input/output port 4~, an~ 248 (input/output port 5). E2ch of the e is an eight-bit bidirectional data port through which dat~
can flow into and out of mi~L~Lccesa~. 100. Each port h~ eight data lines which ~2n be used individu~lLy as either transistor-transistor-logic-cc~patible inputs or as latched outputs. An output instructian causes the contents of ~c~ tor 204 to be latche~ into the 2ddressed port ~42, 244, 246 or 248.
An input ins~ructian causes the transfer of the contents of t~e port t~ the ar~ tor section of ~c~ 7ator and status register 204. Ports 242, 244, 246, and 248 cnmm~icate with the other st3ges of microproc~aso. 100 via bidirectional processor data bus 202.
A tIner 228 is an eight-bit, binary down counter which is software ~LCjL bl~ bo cperate as an interval timer, a pulse-width measurer, or an event counter. ~imer 228 can pass interrupt pulses applied to an external-interrupt input of an interrupt pulse-width prescale logic stage 232. ~hen an externaL-interrupt pulse is applied to micropro~essor 100, it will be 2ckncwledged and processed at the completion of the first nonprivileged ina~ru_Lion if an interrupt-control bit of the status register-section ~rc~ tor and status register 204 is set~ If the interrupt control bit is not set, the interrupt recuest will continue until either the interrupt-co~trol bit is set a~d mucroprocessor 100 acknowledges the interrupt or until the i~L~ ! Uy~ ~ u~ue~L is cleared~

3--~

An instruction r~ister 236 stc:res program steps retrieved fran rea~Gnly mer~ry 220. Instruction register 236 can ~e reset by a pulse applied to an ex~rnal-reset ~) input of a control/test/clock/E:ower~n logic st2ge 240. Stage 240 cont~ins a

5 clock having a pair o~ t~in~l~ ~1 and xrri2. The clock will oscillate in one of sev~ral ~es, d~nrl;n~ on the connections to tPrm;n~l~ ~1 and ~2~
A quartz crystal can be ~ ~ted across these tPrmin~ to make the clock cscillate at the rrequency d~tPrm; ned by the crystal. Alternati~ely, ~n ind~ctor or a tuned, par~llel inductor/capacitor tuned circuit can be .~ cLed across these ~Prr;r~lc. In this case, the clcck c6cillates at the resona~t fre~uency of the inducbor and the intrinsic inpu~ ca~ æ itance of the clcck or the resonant LL~4~ of the p2rallel in2~ctor/capacitor net~ork camprising the Lnducbor, the LntrLnsic capacit~nce, and the capacitance of the external capacitorO
Another pn~C ih-lity is b~ leave ~prm;nAl X~Ll CFen and to drive tPnnin~l ~,2 with pulses frcm an exter~ clock source. In this case, the effective clock Lr ~ y is that of the ex~er~a1 s~urce.
Finally, tPrmin~l X~L1 can be ~LU~ed and tPrm;n~1 ~
~an be connected to a resistor or a resistor/capacitor network.
In this last case, the c1cck frequency wi1l be ~etPr~in~ cy the time CO~ Y~ of the resisbor/capacitor network formed by the intrinsic capacitance an~ either ~he va1ue of the e~ternal resistor or the va1ues of the ~n~n~nt~ of the extern~l resistor/capacitor network~ The external resistor d~Lo~h is emplcyed in solid-state de~and re~ister 10. In ~his application, the clock C.e~u~y wil1 be approximately 3 Mega~ertz and need not be closely c3ntrolled.
The circuit of a preferred ~m~x~1;m~nt of solid-state demand register 10 is now described wi~l reference to F~gure 3.
The actual pin numbers and functional labels ((RESE~), EX~
r~T, et ce~era) of the ~2rious ~mmi~1q of micrcprccessor 100 and 3~ the other integra~ed circuits in solid-state demand regis~er 10 are sho~n. Ihese can be related, for exam~le, to the input/c~tput ports and the various o~er Lnputs of mic-opLocessjr 100 shown in , ~3~

- ~7 -Figures 1 and 2. The data bermi~als of input/output ports P0, Pl, P~ and P5 are given by pin number and according to the followLng canvention: the significan~e of the bit corresponding to each data tPnnin~l of an ~lpU~/OUt~Ut port is.noted in subscript after S the name of the por~. ~or illustration, P00 denotes the least si~nif;c~r~t-bit data ~Prm;r-~l of inp~lt/out~ut port PO~ P07 den~tes the ~os~-significant-bit data t~rmin~l of ~hat port. As stated abcve, m~ .ccessar 100 fonms with nonvolatile read/write memory 152 a circuit which defines a series of consecutive d~ r~litoring intervals and which calculates the electrical-po~er demand i ~ red during each such int_rval~ The eight da ~ lines of memory 152 ~D~-D7) ~re co M ected bo input/ou~put p~rt Pl of micrcprccessor 100. Address and clock signals an~ read/write~erase ~- ~lc for me~ory 152 are provided by input~cutput port P5 o~ microprocessor 100.
Switch 102 (SWl) is the end-of-billing-period reset switch.
When switch 102 is closed, a negative-going, en~-of-billing-Eeriod pulse is provided to dat~ tPnn;~l 1 of i~put/output port P0. In addition, error-flag-clear ~rmi n~l ~ 104 are c~l~,æ ~d ~o data tPrmin~l 3 of input/output port P0 and to ground. T~min~l~ m4 ~llow the ~res~it inventicn to be reactivated after ar.t uncorrectable error in a computing cons~ant or a computed result has C~ L~d.
Power-loss/reacqltisitio~ level generator 108 contained withLn a dashe~-line box ccmprises two v3ltage ccm~arators US~ and USB
and associated passive ~ ts. Comparators ~5~ and ~53 are o~ e~Led to an external-reset p~ESET, pin ~9) input of micrcprccessor lO0. Com~a~ator USA roonitors the difference Ln volta~es between the p~sitive ur,tregulated output and the +5-volt regulated out~ut of pcwer supply 156.
Ccn~parator ~5B rnonitors the differer~e in the voltages developed across a voltage divider and a resistor~capacitor int~Ldt~r ~ both of Wt.ti*.t are driver.t by the +5-volt regnl ated outpuc of po~ær st~ply 156. ~he operation of c~arators U5P, and ~5 IJ5B ls ~ ~ in greater detail below.
T~e demand-register ~ode indicators 11~ (shown wi`hin a dashed-line box) compri~e two conventional light-emittins~diodes ', ~

D32~
~ lY-CR2 and CR3. Transistors ~1 arld Q2 function as switchable current sinks for CR2 a~d C~3, respectively. Transistor gl recelves base drive via a resistor R10 fr~m data benmir~ll 1 of inputfoutput port P~. When data ~r~;n~l P41 is high, transistor Ql conducts and S light-enitting diode CR2 glows to indicate that display 132 of sDlid-state dem~nd register 10 is cæerating in either the cumulative or continucus-cumulative ~cde. ~ransistor ~2 reseives base drive via a resistor Rll from data ~erm;n~l 2 Of inpu~/outDut port P4. When data ~Prm;n~l P42 is hiqh, transistor Q2 conducts 10 and light-emittir.g dicde CR3 glows bo indicate that di~play 132 of solid-state de~and register 10 is cperating Ln the n~nrl~nl~tive mcde. Resistors Rl~ and R13 furction as current lLmiters foc - light-emitt mg diodes CR2 an~ CR3, resp~ctively.
Pulse m itiator 116 (shown in dashed-line box) receives a triggering pulse generated by mi~-v~roce~L 100 and pr~sented to data t~nni n~l S of input/output Eo~t PO. When data tanninAl po5 is at logic 1, DaLlin~ton transist~r Q10 and switching tr ~sistor Q13 cond w t. The light-emitting diode in opto;cnlator ~18 glows and cau.ses the ~hoL~-L~lsistor withi n optoisolatcr ~18 ~o 2~ ccnduct. This canductor causes transistor ~11 to turn cn and provide base drive for pc~er transistor Q12~ ~ower transistor Q12 can ~hen sink current for an external circuit ~ ~,b~e~ to ~r~in~ Y and K~ Modular bridge re_tifier U19 allcws transistor Q12 to see the proper polarity between collector aDd emitter, regardle~s of the pol~rity or tne voltaqe ~I~Lessed ac~oss tPn~in~l~ Y and K. A transient suppressor SP2 is cor~ Lcd across ~rm;nAlc Y and R to p.o~c~ modular bridge rectifier Ul9, po~er transistor Q~2, switching transistor Ql~., and the phototransistor in optoisolator ~18 from cvervoltages.
Because switching transistor Q13 is conducting at the s~ne tLme as Darlington transistor Q10, switching transistor Q14 is cut off~ The light-emitting diode in optoisolator ~20 is darkened and the ~h~DLL~r~istor in ~20 is cut off. Consequently, switching t~ansistor Q15 is aut of~, as is pcwer transistor Q16. The external circuit connected bet~een b~rminals Z and K is not ener~ized, beca~se no current can flcw through dular bridse rectifier U21 and power tran.sistor Q16. The Z and K cutput `i~ ~
. .

f~2~3~

t ~nni ~1 e are pL~æ~ gains'c ~7oLt2~e transients by ~ther sient suppressor SP3.
Thus, when the load connected betheen terminals Y arx~ X is energized, ~e one connected bet~æen t'P~i n~l c Z and ~ is not~
When data lirle P05 is at logic O, pu~ ee initiato~ :L16 charlge5 states, energizing the circ~it connected between ~rmin;~le Z and R
ar~3 deenergiz~ny the circuit co;~ected between teminals Y and R.
Mi~;r~r~:es~as 100 is prc~Lcl"u,ed to toygle data line P05 at a rat@ of, for example, fr~ 0.1 pulse to 10.0 pulses per revolu~ion 0 or ed~ .,~ILL~It disk 168.
Re~ ister ~ cz, 1 4 has f our pl~3 p ~ns P 2 1, P 2 2, P 3 and P2 4. ~e~e pl~ pirLs mate with jack conductors J2-1 throu3h J2-4 . Jack w -d~ LOL J2-1 pro~ides a ci rcuit-ground connection for r~gister ~L~, - r 124~ Jac}c w-~3u~LoL J2-2 pr~vides a ~:5 camection k~ ~e ~volt regulated C~ Ut of F~ær sup~ly 156.
Jack ~ . J2-3 pr~vides t~ register pLV~Lcul~ller 124 clocking pulses which are generated k~ micr~rc;~:essor 100 and ~Les~lted at data line P06. These pulses ~re 2~lied to register pro~-~Ar 124 to cause its inl:ernal ~hift register to shift out in seri 1 fo~m bLnar~ co~ed de~imal data for ~r~lica~;~n to data ~Qrm;n~l P04 via plug P2-4 and j æ k ~ du~L~ J2-4. As ~i ~lC~ above, r~gis ~ r ~)L~'J~ r 124 all~s the five ccrr~uting ~nskh~cs to be PLCYL ~~' inbo nonvolatile read/write memory 152.
~eri;~ tCI-~qr~llQl conversion of each binary coded decimal digit of the com~uting ~ ~ c is p~rfmrmod by micropro^essor 100 pr ior to application to the data lines of non~olatile read/write nx~nory 152.
Values of computing c~-st~Ls and ccmputed results can be displayed o~ a four-di.git, common-cathcde, seven-segment nul~;plQ~P~ light-emitting dicde display 132, which is mzde up of display u~its U8, UY, U10 and U1l. Values to be displayed - visually are presented in bin~ury-coded-decimal form to binary-coded-to-decimal, sev~l s2~ment deccder 128 via data lLnes P44-P47. Bfr~ce of the oonstr~ction o~ data lines P44-P47, pull-up resistors ~13 are requirP~d. The seven output lLnes Q~ decoder 128 are connected to the anodes of aopropriate segments o~ display digits U8~Ull via current-l~miting resistors .

3~5 - 2~ -U16 and U17. The decimal-poin~ anodes of display units ~8-Ull receive current via switching transistor Q8 and current-liniting resistor U16(7-8). Transistor Q8 receives base drive via resistor ~17 ~hen input/out2ut ~crt tPrm; n~l P40 is at logic O. Resistor ~13tl-a) pr w ides a ~eans for turnLng transistor Q8 off when P40 is at logic 1~
P~h~o ~ ~sitive-integrat~d-cir~uit display c~ntroLler 142 of oon~entio~al design inhibits decoder 128 from su~plyins logi~-l ~ltage leqels to the an~des of display digits ~8-Ull when ambient-light levels are be_~w a preselected threshold Yalue~
Display oo~oller 142 dces so by Cont olling the voltage a~plied to a bl-~n~;n~ P31) input cf decoder 128. The ccmmon cathcdes of ea~h display digit ~8-~11 are tied to the collectors o a set of four Darlington transistors Q3~Q6, ~hich corres,~ond to display drivers 138 shown in Figure lo These Darlingt~n tran~,~stors receive base drive from data ~ar~i n~ p50-P53 of mi~yLcces~u~ 100. ~obe ~hat the a data hPrmi~lq are l~ipl~Y~. They also pr w ide the lower four address bits for n~nvolatile read/write nt~nory 152. Display ~rivers 13B
(Darlington transistors Q3-Q6) receive bas~ drive via resistors ~14. DarlingtDn transistors are employed as display drivers 138 because their hi~h current gain keeps small the a~ount of current which the lower four data lines of input/cutput port PS must source~ The current which flows through appropriate segme~ts of each dis21ay digit U~-~ll flows through the corr~cr~n~;
display-driver transistor to gr~und.
When the unreg~ ted positive voltage decreases to a threshold de~nri nf~ by the ~ction of the voltage divider comprising U13(1-5)/R20 and the cperating characteristics of ccmparator ~S~, the out~ut of ~SA goes to lcgic 0. To prevent normal fluctuations- in the unrequlated positive voltage ~such as those w.hich cccur when o~toelectronic display circuit 132 is activated1, hysteresis is provided by resistor Rl9. When the output of ~6~ goes lcgic 0, it pulls the exte m al reset (RESEr~
tPrmi nAl of micrcprocesgor 100 lcw. Ihis low level instructs the mucrcprocessor to tenmunate the dem2nd-monitoring interval in progress.

~2~3;~85 When the volt~ge difference between t~e pcsitive unre~ulated voltage and the ~-volt ou~put of pcwer supply 158 returns to an acceptable level, the output of ccmparator U5A switches states.
EIswever, the R~ input of micrq?rosessor 100 does nct return to S logic 1 im~ediately, due to the t~me delay in kodu~:&d by comparator U5B and its associated passive ~nm?on~nts. The inverting input of ccmçahator U5B receives ~5-volts regulated via the voltage divider R2~/R23. The noninverting input of ccm~arator ~5Br ~owever, receives voltage fr~m the ~5 volt regulated line via resis~or/capacitor integrabor R24/C3. The output of co~p~rator USB dces r~t go to its high state until capacitor C3 has charged up bo a voltage sligh~ly greater than that fl~-~iche1 to ~he ~ verting i~put of ~ abor U5B by vol~age divider R2~/R23.
h~en capacitor C3 h charge~i Sl~f i ciLr~tl~, the RESE~ in~ut of ni~.uy~x es~r 100 returns to l~gic 1, and the next dem~nd-monib~ring interval can beg~n.
As ~;C~cse~ briefly with res?ect to Figure 1, cptoelectronic p~ gener bor 148 ;t~ a pair of light-emitting diodes 302 an~ 304, whi,-h are i~a~ Led ~n series between ground and rent-limiting resistor R16. Light-e~nitting dicdes 3Q2 and 304 are ~nte~ adjacent to each oth OE and near one face of disk 168 or 168a. M~unted near the cpposi~e face of disk 168 or 168a are a pair of ~ho~r~lsistors 306 and 3080 The emitters of pho~otran-sistors :306 and 308 are grounded, while their oollectc¢s are c~,e~Le~ to the +5-volt line via resis'ors R15 ~n~ R14, respectively. The oollector of phob~LLonsistor 306 is also 3 to resistor R26 a~ to the ~nverting input of ccmparator ~SC. m e collector of pl~ ~ansistor 308 is oonnected to the noninverting input of conparator USC.
Disk 168 or 168a has, for example, 10 cpenings in it (not shown). The pairs of light-e~itting diodes 302 and 304 and of plx~LL~sistors 306 and 308 are mcunted with respect to disk 168 or 168a so that the light from diodes 302 a~d 304 can reach phototransistors 306 and 308 when the space between the light-emitting diodes and the phuLoLL~nsistors is occupied by one of the openin~s prc~Lded ln disk lG8 or 168a. ~hen the space between the llght-enitting diodes and the ~ JLLdnsistors is occupied by a solid portion of disk 158 or 168a, no light fram the dicdes czn reach the phob~transistors. When a pho~transistor 3Q6 or 308 is ~ rmln~t~d~ it conducts, and a sround-voltage level is applied to the input of co~paratDr U5C to which i~s co~lect~r is conne~ted~
When ~he ph~ L~lsistor is shadow~d by a solid portion of disk 168 or 168a, a high~voltage level is applied to the input of camparator U5C b~ which it~ c~l1~ctor is connected~
Resistor R25 is ccnnected between the output ~nd noninvertir.g input o cc~arator U5C to introduse a large amount of l~steresis~, Because of this hysteresis, cn~arator U5C furx tions more like an analog set/reset flip-fl~p than a ~ rator. The flip-flçp behavior of ~C and the pcsitioning of the pairs of light-emitting diodes 302 and 304 and ph~LL~istors 306 and 308 ccntribut to ensure that on~ valid electrical-~nergy ~.~Lion pulses are generated. Jitb~r of ed~y-curr~t disk 168 d oe s not c2use a pulse to appear at the output of compara~or ~5C. The va~id p~lses generated by oomparator USC are ~pplied bo data line P00 of mio~ U~LL~UL 100 .
. ~c~ær su~ply 156 shown in an~ther dashed-line kox provides 2~ unre~ulated and regulated pcsitive and regulated negative v~ltases bo ~L~L iate stages of solid-state demand register lO. Pcwer suFply 156, in berms of providing regulat0d and unregulated voltages, is of ccnventional design and th~lC is not described in detail.
Pc ~ r supply 156 l~o derives from the alte m ating _ULL~t mains 178 and 180 a train of pulses having a frequency related to the frequency of the mains as follows. The alternating current vol~age aF~earing across the 8.4-volt secon~2ry transformer Tl is ~ uL~d by the diode 181 of modular bridge rectifier U2 whose ancde is connected to the lo~r end of the 8.4-volt sPcnn~ry and whose cathode is c~.e~ed to the unregulated Fositive supply.
The half-wave rectified signal which appears across diode 181 is ~pplied to the i~verting input of cc~parator ~D via resistor/
capacitor integrator R27/Cl. The nonin~erting input of comparator ~SD receives a portion of the regulate~ pcsitive voltage developed acro6s capacibor C6 via volta3e divider R4 y R41. ~ysteresis is introduced into comparator USD by resistor R21. ~ecause of th.s ,~ i ~.D~J

3;~

hysteresis, comparator U5D ~unctio~s as a Schmitt trigger~ The output of~camparator ~SD is high un~il the half-wave rectified, direct-curr2nt wavefonm attains a suficiently high amplitude.
The output of cc~parator USD thereupon switches to its lcw state, where it relains until the volta3e acrcss capacitor C1 drcps to a level lcw enough to overcome the hysteresis introduced by resistor R21. This hysteresis preYents comparator U5D from c~erating erratic~lly and proviaes ~mmunity from line transients. The train of pulses which appears at the ou~put of camparator U5D is aFplied to the external-interrupt (~X~ rXT) Lnput of micrcpro~essor 100.
Each time a pulse is a~plied to the ~xternal-Lnterrupt input, mi~yLcc~ss~r 100 enters a ~imekee~ing subroutine di~c~1c-se~ belcw with referen~e to Fi~ure 10.
As ~;~rll~ce~ above, ena-of-interval ke~er 162 (shcwn in a dashed line box) generates an end-of-interval pulse ~hen each d ~ itoring ~n~erval terminates. At the end of each inberval, a narrow pulse a~pears at da~a l m e 2 of input~output port PO d mi.~L~oe~r 1~0. This pulse, which, for example, is negative-going and 400 ml~oce~ in duration, is stret~hed ~y resistor/capacitor integrabor R5/C10. The initial negative-going pulse causes transistor Q17 to cut off. Base cu~rent then flows to switching transistor Q18 via resistor R3. Transistor QL8 then effec~ive:ly grounds the ~unction of resistors R4 and R5, allcwing base current to flow thrc~gh switchLn~ transi~tor Q7. Transistor 2~ Q7's conduction-time is stretched after transistor Q18 cuts off aga m because of the effect of resistor/capacitor network ~4~R5/
C10. When transistor Q7 is conductins, it sources current to the light-emitting diode in optoisolator U22 via current-limiting resistor R6.
When current flows through the light-emitting dio~e in opto-isolator ~22, the light-e~itting dicde irradiates ~he phoLos~si-tive bilateral trigger diode also c~ntained in cptoisoIator U22.
Note that optoisolators c~ntaining other tyFes of light emitters and ~I,o~s~sitive C~ S can be used as cptoisolator ~22.
When the ~hoLo~ ~itive, bilateral trigger di æ e is irradiated, gate current can ~low through triac Q9 if an alternating current a `' ~D ~

-- 2~---voltage is impress æ acro6s keyed ou~put ~PrminAl~ 164 (m~in ~ormin~l~ Tl ~nd T2 o~ ~riac Q~). Thus, a load connected in series between one side of an alternating current volta3e .scurce and one of the keyed output t~rmin~l~ 164 will ~e ~nergi~ed during S the time that transistor Q7 is cond~cting.
Nonvolatile read/write me~ory 15~ stores five ccmputing constants, as d;~ d abcve. Campu~ing oonstant 1 is a t~c-digit binary-coded-decim21 n~mber de~cribing the number of pulses generat~d by pulse initiator 116 for each revolution of edoy-current disk 168. For example, i the value of this ccns~ant is00, ten pulses a~pear at ~le KYZ cutputs 118 of pulse initiator 116 for each revolution of ed~y-current dlsk 168. For values of this wilsL~l between 01 and 99, the number of pulses generated per revolution of eddy-curr~nt disk 168 equals the decimal n~mnber described by the th~ disits with a decimal poin~ insert~d between th~sr; (0.1-9.g).
Computin~ ~ L~-L 2 describes the len~th of the demand Lnterval us m g two binary-coded deci~al digits. The length of ~he demand interval can be pr~J,~ within the range of, for exa~ple, 1-9g minutes.
Ccmputing cJnsL~t 3 is a three-decade, binary-coded-decimal number dlescribing a disk cmnstant asscciated with eddy-current disk 168. Each revolution of disk 168 oorresFcr.tds to the c~
ti~n of ~.t incren~tental amount of electrical energy in watt-hours.
The value of the disk ~n~L~t loaded into nonvola~ile memo~y 152 car~t be/ for example, within the rar.tge of frcn~t 0.1 to 99.g wa~t-hotIrs per revolution.
Computing C~ 4 stored in nonvolatile read/write memory 152 is a single-decade, binary-~oded-decimal ntlmber having a value of frcm 1-5. If the value of this com~uting c~ L~ is 1, soLid-state demand register 10 functicns only in tkte rn~lll ative or block-interv ~ m~de. If the value is ~, solid-state dem2~d reyister 10 functions only ir.t the cumtllative mcde~ If the value is 3, solid-state den2r.td register functions cnly ir.t the continuc~ts-c l~t;ve mode. If the value is 4, solid-st~te demand re~ister functions in both the nonc~ulative and cumulative modes.
Finally, if the value of this constant is 5, solid-state ~and ~D ~3~D~

register 10 functions in the noncumulative and continuous-cumulative mcdes. With respect to ~llsLdll~S 4 and 5, display 132 alternately displays the electrlcal-power demand values calculated for each operating mcde.
S The fifth constant det~nni~P~ the position of the decimal pOLnt of display 132 which is actuated. This ~ns L~lt is a twcrdecade, binary-ccded-decimal number having, for example, a value in ~he range of from 00 thro~gh 44, The most-significant digit det~nm; n~ the position of the ~ctuated decimal ~oint of display 132 r~hen solid-state d ~ d register 10 is o~erating Ln the ~nnr~ ti~e mcde. The least significant digit de~cribes the pcsition of the acblated dec~mal po ~ t of display 132 when ~olid-state demand register 10 is op~rating in eithOE the ~m~ ve or continuous-~m~ ve mode. If a digit is 4, the decimal point of display 132 will be floating in the c~rrP~nrr~;n~ operating ~Dde.
If the value is from O to 3, the decimal point wi1t be fixed at one of t~e four F~ssi hl ~ p~sitions of display 132. A value of 3 means that the decimal point is fi~ed after the least sigaifioant digit. I:f the v~lue is 2, the de~mal point is ~ixed between the next-tarleast sisn; fiC~nt digit and the least significant di~it.
If the value is 1, the d~r;~l point is fixed between the next-to-nxxit sir ifi~t diSit and the next-to-least significant digit.
If the value of this ~a~sL~t is O, the decimal point is fixed between t~e most si~ific~nt digit and the next-tc-most signi-ficant di.git of display 1~2. I the decimal point is fixed at one of the~e pcsitions, solid-state demand r q iste~ 10 will n~t adjust to meet cverflcw c~nditions. Rather, it will loc~ up at the 5rorifi~1 r Yi value, that is, 9.99, 99.99, 999.9 or 9999 kilowatts for block ~nterval demand. The register will roll-over for ~ ~ ;ve and continuous-cumulative oFeration.
~Rgister ~L~yL r 124 ;n~ tlP~ a three-pcsition switch which permits generation of the follcwing three ~
display the current c~ ~LdnL value (for example, constant 1); (2) display the next constant value (for example, constant 2); and (3) load the value set by means of the ~h~ l switches into the location o~ nonvolatile read/write me~ory 152 reserved for the 3;~1S

current constant, and then display the value of the ne~t constant.
Constant 1 is optional, but constants 2-5 are mandatory if solid-state demand register 10 is to operate correctly. If solid-state demand register 10 is operating in the c~mulative or continuous-cumulative mode, pro~ranmlr~ of any of constants 2-S will cause the cumulative or contlm~o~l~-cumulative d~mand value stored in r.~nvolatile read~write memory 152 to be reset to zero. ProgLam-ming of constant 1 will not affect the stored cumulative or continuous-cumulative value.
Display 132 is cycled between displaying data and performir~
a display test in which all displ~y s~ n~ are energized and 8's are displayed. All decimal points of display L32 as well as the two Light-emitting diodes of demand re~ister mode ir~iCAtors 112 are energized. Dis lay 132 will display data for a period-of six seco~ds. This is followed by a two-second "off" time~ then a display test for six seconds, and then another two seconds of "off" timeO This cycle repeats itself as long as power is received from alternating-current mains 178 and 180. In the case of a _ n~tion (noncumulative ar~ cu~~ tlve or nonc~mulative and continuous-cumulative) register, the data corresponding to the second rnode of operation is displayed after the first two-second off time, but before the display test.
The routines according to which the present invention functions are now described.
The main routine 400 of the operating program, which is stored in the read-only memory of microprocessor 100, is shown in flow chart form in Figure 4, which conprises Figures 4A anu 4B.
Main routine 400 starts with an entry step 402, as shown in Figure 4A. Next, scratchpad random-access memory 212 is cleared during operation step 404. After the scratchpad locations have been cleared in accordance with operation step 404, a decision is made at step 406 as to the function which solid-state deman~ register 10 is to perform.
There are two possible functions: solid-state demand register 10 can oe d~lcat~d only to generate a programmed number æ~s ~ 2~ -of pul~es for each revolution of edcy ~ rrent disk 168; or register lO oan function as a true demand-registPr (which can also include prcvisions for generating a pr~gramm~d number of pulses ~or each revolution of eddy-current dis~ 168). ~ecision stey 406 checks the logic level pres2nt at data ~rm;n~l 7 of input/cutDut port P0. If this tPrm; n~l of i~ut~out~ut port PC is at logio l, solid-state demand r~gister 10 unctions as a demand register. If this t~r~;n~l is at logic 0, however, solid-sta~e deman~ regis~er 10 functions only as a pulse initiator and performs no dem~nd-register cperations.
If solid-state demRnd register lO is tD a~t only as a pulse initiatort nonvolatile read/wrib~ memory 15~ is not required. In ~his case, ~he only oonstant which mu~ ~LGCesaOL 100 requires is cu~ Snt 1 (plll5e ratio), whose value can be fixed by means of wire j ~ Prs ~.eoted between the a~prq~riate data tPrni~lc Of input/output pcrt P1 and either ~5 volts or ground.
If a pulse-initiator-cnly decision is made, C~ 1 is loaded into se.~L~ ad 212 by an operation s~Pp 408. Main rautin 400 the~ prcceeda to an cperation step 410. During step 410, the energy ~l~w~icn pulses generate~ by aptoe lectronic pulse generator 148 pr~mpt mi~LvyLc~e~vL lO0 to genera.e and present to data tPrrin~l S of input/output port P0 the appropriate number of pulses for each pulse ~resented to data ~P~min~l O of input/output port P0 by optoe lectsonic pulse generator 148. Main rcutLne 400 continues bo lco~ through o~eration step 410 as lo~g as solid-state demand register 10 is p-CyL~U-l~d to function only as a pulse initiator.
In generating pulses, ma~L~Lc w ~YGL 100 detPrminP~ what logic level is present at data hPrmi n~l of input/output psrt P0.
If, far example, this data ~n~in~ is at logic 1 an~ one pulse is to be generated, micropro-essor lO0 forces this line to logic 0.
If line S Oe port I?0 is at logic 0, and a pulse is to be generatedr ~ er, ~icropro-essor lO0 foroes this line to logic 1. If yet another pulse is to be generated, mi~ ro~es~oL lO0 toggles line 5 of input/output pcrt P0 to its alternate state.
Reerring asa m to Figure 4, if t~nmin~l 7 of input/outpu~
port PO i oonnect~d to +S volts, decision step 406 det~rmi~
th~ soli~-~tate demand register lO is to function as a true ~3~5 demand register. ~oc~rdir~ly, main r~utine 400 prc~eeds to a d~cision step 41~, m which the status is checked of an error ;~l;o~t;r~ cr flag st~red in a designated lo-ation of n~nvolatile read/~rite memory 152.
S If this flag is at logic 1, a storage lccation in nonvolatile read/write me~ory 152 c~ntains erronecus, unoorrectable data. In this czse, an cperation step 414 is ~erfor~ed, where an error .indication (for example, f~hirg de~imal points but dark~ned digits) is generated by display 132.
Main routine 400 loops baGk ~o operation step 414 so that the error ;n~;r~;nn is d~lay~d ccn~;n~ cly and ~o further ~ata-proGPq~ steps are performed. This ~de of ~eration oontinue ~m~il 'che register 10 ~s re~ved fr~ service ar~ the error fl~g ls ~leared by means of error-flag-clear hPr~t;n~l~ 104, as ~ s~d above.
If the error flag is at logic 1, all of the data stored ~n no~Nolatile read/write ~D~ry 152 are valid and the ~aLn rcutine 400 ELu~e~s ~o an operation stPp 418. In cperation step 418, the ccmputing c~s~L~ stored in nonvolatile read~write me~cry 152 are lo de~ into a~pr~riate l~a~;nns of scratchpad 212.
Next, an opera~ion step 420 is performed to refre~h the crmru~ y canstants stored in nonvolatile read/write memory 152.
T~o desis~nated lccaticns of nonvolatile read/write memory 152 are associate~ with each stored ooaputing ccnstant or o..~ubed result.
For purFc~ses of the following discussion cnly, these lccations can be desiqr~ted lo-ation A and location B. As~ociated with locar tions A and B is a pointer fl3g whic~ signifies which lccation is sb~red with c~rrently valid data. S4ppose that location A
contains currently valid data for a particular ccmDuting cons ant.
The flag then points to locatlon A. To refresh these data, the data are written into lo~ation B. When valid data have been written inbo location B, the flag i9 changed to point to lo_ation B. This ~L~oei~Le, which is also followed when data s.ored in nonvolatile read/write ~emory 152 are to be changed, has been set up ~o ensure that valid da'~ are stored in and are retrievable rcm nonvolatile read/~rite memory lS~ even if a power failure oo~ur~ during a data-refresh or data-change cycle. The likelihood of loss of valid data to such an event is ~l~L~LUL~ m;n;m;~

~2~%~3S

~ 29 -Accordingly, operatlon step 420 involves retrieving the computin~-c~l~L~sl~s data stored in the memory locations denoted by ~he valid-data fiags, writing these data into the apprcpriate altern te me~ory l ationsr znd changing the status of the lccatio~-pointing, valid-dat~ fla~s.
Main rcutine 400 then pLO~eedS to an operation step 422 tn which ~he n~ tl;t~ive and cu~ulative electrical-p~wer dem2nd values stored in the apprcpriate locations of nonvolatile read/
~rite ~emory 152 are loaded into s~ldL~IJ~dd 212. ~hen these values have ~een loaded, display 132 is Upddt~ with ~he ccmputed-result da~a stored Ln scratchp2d 21~..
Thus, if solid-s~ate demQnd register 10 is fun~tioning in the ~r~ t;ve mc~e, the ~u~ed cumwlative electric~l-power demand v,tlue stored in scratchpad 212 1S displayed, but the ~ tive electrical-power demand value also stored in scratchpad ~12 is ~t displayed. In ~ollLL~t i solid~state denand register lO i~
functicning in the ~n~mll~t;ve and either the c~ tive or the continucus-cumulative m~deS the two values Are alternatel~
displayed by display 132.
Main l~op 400 then proceeds via ccntinuation la~el 424 to an cperation step 426, as shcwn in Figure 4B, Ln which solld-state demand regLster 10 is prepared for a new demand-~onitoring interv 1. This preparation involves resetting to zero the current electrical-power de~and value stored in scratchpad 212 and loading 2S into s~dLl~dd 712 data describi~y the lengths of the next demand-msnitoriny interv~l. Also, any flags in mic,~Lo_essor 100 which reguire clearing are cleared at this time.
Main routine 400 then proceeds to polling sequence 428, through which a DISR subroutine 430, a ~ME subroutine 432, a DISC~ or display-control subroutine 436, a E~BP or end-of-billins-period subroutine 434, and a PX~G or p~-yL~Ilr~r subro~tine 438 are sequ~ntially perform~d. Each of these subroutines are ncw cnnci~red in detail.
Figure 5 is a 1OW chart of the DISR subroutine 430 of main rcutLne 400, as shown Ln flow-Ghart form in Figure 5.
~riefly, DI5X subroutine 430 increments the value of the pcwer demand made durir~3 the cur~ T~nitorir~3 interval only if a . .

~3~

pulse(s) has been receiv æ frcm the opt~electronic pulse generator 148 since the last time DISR subroutine 430 was passed thro~gh.
~ISK subroutine , --- with ~n entry stage step SC0. Next, a decision is made at a step 5~2 as to whether mi~Lc~rcoessor 100 has received an energy-consumption pulse si x e the last time decision step 502 was ~e_uL~d. If no new energy-consumDtion pulse has been received, DISR subroutine 430 proceeas to a return-to-poll exit step 506, and the next subrcutine of polling sequ~nce 428 ~see Figure 4S) is entere~.
If a new pulse has been received, hcwever, the value of a variable NE~R~3~R, ~hich is stored in scrat~hpad 212, is increm~nted by a value re~t~d ~o one pulse received from optoelectronic pulse generabor 148. NE~PEAg is a Yariable which descri~es the eleckrical-power d~mand being calculated during the current demand-monitoring interval. NE~5~ is incremented in value by n amcunt in kilowatts egual to the in~ l 20unt of pc~er cons ~ tion ~isni~ie~ by generation of c~e energy-usage pulse by c~toelectronic pulse generator 148. NE3E~R is calc~llated by multiplying the pulse by a demand c~lLaLdn~ ~d (which has ~;m~ncio~ of k;lowatts 20 per pulse). Rd is related to a pulse-energy ~ at~LIt Re (which has dim~l~ions of watt hcurs per pulse~ which is equivalent to cnm~utin~ ~ Llnt 3 stored in nonvolatile read/write memory 152.
ColLsL~t Rd can be calculated in accordance with the follcwing f; ~:
~!5 (1) Rd(kW/pulse) = [6 x Re~W-h/pulse)]/ ~D(h) x 1000 ~W/XWn3, where Td is the length of the de~2nd-monitoring interval in minutes.
The in~ ~.L41 amount of pcwer added to NEW~EAK is derived by multiplying the pulse received from optoelectronic pulse genera~or 148 by the cJ,~ nL ~d. After NE~E~E~R h~ been so inc. ~_-ted during cperation step 504, DISR subroutlne is exited via exit st~2 5C6. Then, the next subroutine of polling s~lce 428 is enter~d 5 (see Figure 4B).
TIME subroutine 432 is shown in flow-chart fonm in Figures 6A
and 6B. Briefly, TIME s~brcutine 432 causes a pulse to be ,~ o-~f ~

generated if the demand m~nitoring inter~al is over, prepares reyister 10 for a new interval if the inter~al is over, a~d dP~r~ir~ on the ~cde of register 10, it may update the NEWP~AR, OLDPE~R or CCNlll~lVUL values. OIDPE~K is the highest electrical-po~er demand calculated since the last end-of-billing period pulse was generated and is stored in nonvolatile read/write memGry 152.
~LN'L'l N~ is the oontinucus-cumulative demand value and is stored in nonvolatile read/write memory 152. ~LwllN~u~UL is the sum of the OLDPEAR values stored in non~olatile read/write memory at the generation of ea~h pre~ious ~nd~of-billing-period p~lse and of the highest el~ctri ~ -pc~er de~and calculated sin~e the generation of the last end-of-billing-period pulse.
~$ME ~LL.uLine 432 begins with an entry step 600. It ~hen pL~ee~3 to a decision step 602, which detp~r;n~c whether the current demand-~cnitoring interval has just ended. If the i3terval is still in progress, the subroutine pro^eeas via cr~;mlation label 604 to an exit step 632 ~Figure 6B), by which it returns t~ polling sb~nce 428 ~Figure 4B).
If the demand-ncnitoring interval h~ just ended, however, an operatiorl step 606 i~ ~eL~L~ ere, mi~f~o~ssor lOC is insLLu~te~ to generate an end-of-interval pulse which appears at data ~Pnn;n~1 2 of input/output port PO. Then, a decision step 6C8 is perfo~med. Decision step 608 dehPrm;n~c the status of a lockup f:Lag in mi~uyLoce~3~r 100. This lockup 1ag will have a value of lcgic 1 if ccmputing Wl~k~l'L 5 de~pnn;nps a fixed pcsition for the deci~21 pOillt of display 132 and if OLDPEAR
exceeds ~he capacity of the fixed-decimal-point ~p~hilities of display 132. If the lockup flag is at lcgic 1, the TIME
subroutine 432 jumFs to an cperation step 630, which pre~pares demand register 10 for the next dem3nd-monitoring interval. No further demand-calculating cperations are performea, and then TIME
~u~ Line 432 ~Le~eeds to a return-to-pol1 exit step 532, by which it enters the next subroutine of polling sequence 428 (see Figure 4B).
f the lcckup flag is at logic 0, however, an operation step 61~ is performed. Here, NE~n~E~K (now the demand calculated during the interval which just ended) is ccmpared ~ith the display c~pacity of display 13Z tl~ t~Pt~r~;nP ~ t~hat ~ a~i~y has been ~2~
c 3~ ~

~CPP~Pd by the newly calculated el~ctrical-power demand. The lcckus fl2g is set to logic 0 if the calculated electrical-pcwer demand has no~ oYce4~ the capacit~ of display 132. Note that if computing c~nstant 5 has a val~e which allcws the dec~21 pcint to S float, the icc~up flag will never be set to lcgic 1.
After cDeration step 612 is performed, a decision is made at a step 614 as to whe~her the value of NE~E~X exce~ds that of OLDPEAK. I it dkes not, TIME sLbroutine 432 jumps via label 610 bo s~eration step 630, ~n which the de~ar.d re3ister is prepared for a new demand-monitorLns inter~al, as ~i~C~ Pd above.
If ~he value of NE~ R does exceed that of OLDEEAK, a de~is~on step 616 is made to determine the ~alue of com~utLng CJI~ L~t 4, and thus ~he oEerating mode of solid-state demand r~gister 10. If solid-state demand register 10 is functioning in the ~nn~ tive or the c~mul~tive mcde or in both the nnnr~ tive and ct~miL~tive msdes, TI~E subroutine 432 proceeds via contim~t;r~n label 618 to an cperation st~p 626. On the other h2nd, if solid-state demand register 10 i~ functioning m the continuous ~ ~ tive mcde or in both the ~ tive and cnnt;n~l~le~ mll~;ve modesr TI~E subroutine 432 pLCC~edS via continuation label 620 to an cperation step 622. If TIME
~ubrcutine 432 jumps to cperation step 626, the value of OLDPEAK
a~ stored in s~L~t~ ad 21L2 is set eq~al to that of NEhl~E~K (also stored in scratchpad 212). Then, in an cperation step 628, the updated v~llue of OLDPE~R is written into the appropriate location of r.onvolatile read~write me~ry 152, and he associated pointing 1ag is changed to indicate that ~he valid OLDPE~R value is stored in the l~C~t;~n of nonvolatile read/write memory 152 into which it has just been h~itten. Also, in operation step 628, the value of OLDPEAR as displayed by display 132 is updated. After cperation step 628, an operation ste~ 630 is performed to prepare the demand register for the next dem2nd-monitoring interval. Then, TIM~
subroutine 432 is exited via an exit step 632 and a return is made to polling se~u~ce 428 ~Figure ~B).
If s~lid-state demand register 10 is cperating in the continuous-cumulative mLde or 'ooth the noncumulative and continuous-cu~ulative modes, the aIithmetic operations described ~e ~f~r~
~iL~v~A~

by operation step 622 are performed. Specifically, the Yalue of OLDP~K is subtracted frGm that of ~EWPEAK, and the difference obtained is added to C~Nrl~W ~UL, one of the computed results loaded into scratchpad 212 from nonvolatile read/~rite ~e~ory 15Z
S in ~n cperation step 422.
Note that C~NTIN~UFL~ is the continuous-cumulative, electrical-power demand value: it is the summation of the highest electrical-pcw~r deTand incurred during each of the prior billing pericds, as ~el~ as of the highest electric l-p~wer demand inc~rred since the beginning of the latest billir.g period. When the value of CONTIUCIMUL stored in sc~dtel~d 212 has been so increa~ed, an cFeration step 624 is performed. ~he increased value of cr~lN~ L is writte~ inb~ the appropriate l~cation of nonvolatile read/write memory 152 and ls provided to display 132 vla ~put/cutput port P4 of mi~u~L~c~sso~ 100.
~e~t, operation step 626 is performed, in which the value of OLDPE~R stored in s~Ldt~d 212 is replac~d with ~hat of NEWPEAR.
When this is accomplished, the u~dated v~1ue of OIDPEA~ is written into the apprcpriate lo-ation of non~olatile read/write memory 152 and is provided to display 132 via input/output port P4 by means of cperation step 628. Then, solid-state demand register 1~ is prepared fo~ a new demand-monitoring inten~al, as was done in operation 426 (see Figure 4B~. TI~E subroutine 432 is then exited by means of step 632, and a return is made to polling sequence 428 ~FiguLe 4B).
The EOBP or end-of-billing-period subroutine 434 is shown in flow chart form in Figure 7. Briefly, EOBP subrol~tine 434 pPr~or~c processing and housekeeping which should be performed at the end of a billing period.
~CEP subrout~ne 434 bes ms with an entry step 700. After step 700, a decision is made at a step 702 as to whether an EDBP
flag within mi~ rccessor 100 is at logic 1 or lGgic 0. If the ED~P flag is at logic 1, an end-of-bill;ng-period pulse has been generated a~d decision is made at a step ~04. In step 704, the status of an error flag stored in scratchpad 212 is checked. This ~lag ls at logic 1 if data sto~ed in scratchpad 212 have been detected to be erronecus. If the scratchpad error fl~g is logic '~p,,f _ 34 _ 1, an operation step 726 is perormed which sets the E2~ error flag location to a logic lo Operation step 706 is then pe~formed to generate a fl~ch;~s error indication on display 132.
If the scratchpad error flag is at logic 0, however, a d~i ion at a step 708 i5 made bo determine the value of computing cv~.s~cnt 4 twhich determLnes the operating ~ode of solid-state demand r q isber 10). If tbe value of computing cons~ant 4 i5 1, 3 or 5, the EO~P subroutine 434 jumps to an cperation step 714, in which the value of OLDPE~ stored in s~t~ cd 212 and nonvolatile readJwrite mEm~ry. 152 is reset t~ zero. Then the lo~kup flag in mi.Lu~oces~ur 100 is reset to zero. (Note that this flag is at logic 0 unless the largest computed electrical~
power demand e~ceeds the capacity of display 132.) Next, EoBP
subrou~ine ~34 is exited at a step 718 and ~ain subroutine 4~0 is r tered via update label 416 (Figure 4~).
If the value of c ~ ting ~ L 4 is 2 or 4, an operation step 710 is performed after dP~iqi~n step 708 has been made. In ~his step, the ~alue of C~MWL ~hat is stored ln scratchpad 212 is replaced wi~h the sum of CGM~L and OLDPE~R. C~MaL, the t l1y o~
the summed Feak electric l-power der2nds for each billing period, is generated ~hen solid-state demand register 10 is cFerati~g in the cumulative mode or both the n~rr~ ti~e and cumulative ~odes.
After C~DL has been updated in scratchpad 212, the uDdated value is written into the apprcpriate loration of non~olatile Z5 read~write memory 152 and is presented to display 132 via input/output port 4 by means of an cperation step 712. Then, steps 714, 716 and 718, which were ~i~c--.cs~1 previously, are performed.
lf the E3BP flag is at logic 0, decision step 720 is made as to whether E~BP reset switch 102 is cpen or closed. If the switch is o~en (n~t being depressed), the subroutine is exited via step 724 and a return is made to pollin3 sequence 428. If the switch is clos~d (currently being depressed while decision step 720 is being made), the E~BP flag is set in operation step 722, and then the ~r~LLne is exited through exit step 724.
The DISCR or disk-control s~br~utine 436 is shown in flow-chart form in Figure 8. ~riefly, DISCR subroutine 436 controls the ~4~ 1 activation and de~cti ~ t~on of displa~ 132~

,i! ~
,~ ~

3L~V3~

DISCR subrcutine 436 is e~tered Yia an entry stQy ~00. NeYt~
a decision is made at a step ao~ as to whether a display timer in nlcrcpcocessor 100 has be~n decremented to zero ~y the traLn o~
pulses from power suFply 156 a~plied to the external-interruDt inFut of ~icrcprcce~sor 100. Ir the display tLmer has ~ot been decremented t~ zero, ~SCR subrou~ine 436 is _xited via an ~xit step 812 and a return is made to pol ling SQqUQnCe 423 (see Figure 4B). If the display tiner has been decremented to zero, a de~i5ion is made at a step 804 as to whether dis~lay 132 is on or o ff (activated or deactivated)~
If display 132 is on, an operation step 806 is p~rfnrm~d to darken the display and b~ load Lnto the display timer in mi~,c~oaess~r 100 data bits corrp~rr~ing to a t~ne period of ~wo SDr~n~. When cperation ste@ 806 is cQmpleted, the subroutine is exited via a step 812 and a return is made to polling s~ e 423.
If the displ~y is off a~ the time that d~riqi~ step 804 is made, an cperation step 808 is ~e.ru~ d~ Here, a display buffer in mi~,u~L~ess~, 100 is loaded with a pOLnter which directs mi.;Lu~Lo~ess~L 190 to present b~ Lnput/output port P4 data bits d~scribing the ccmputer result which shculd be displayed. For example, if ~nmrut;n~ o~LanL 5 is 1, the display bufer will be lcaded with a pointer which directs the display of ~onr~ tive power-d~2nd data. If ccm~uting o~nstant 5 is 4 or 5, solid-state demand register 10 has two c~erating mcdes. In this case, the display buffer is alternatel~ loaded with a pointer directLng the display first of non~r~ tive power-de ~ nd data and then of either c~mulative cr continuous-cumulative power-de~and data.
The display buffer is al.so loaded at aF~rcpriate time~s with a pointer directLng the presentation of display-test data to input/output port P4. After the display buffer has been loaded with the apprcpriate pointer, an cperation step B10 is performed to turn on the display and load into the display timer data bits corr~cp~n~in~ to a time period of six secands. Then, the subroutine is exited via a step 812 and a return is made to 35 polling S~ e 428.
DISCR subcoutine 436 æ ts out the following pattern of æ tivatian and deactivatic~ o~ di~play 132. In a single-mKde . .

~2~

demand register, the apprcæriate ccnputed dem~nd i5 displayed for six seccnds. Then display l32 is darkened for two seconds.
Next, a display test is performed in wnich all display sty~ s and decimal points are lit for six secands. This is followed by another two-second dark interval, and ~hen the cycle repeats itse~f. In the case of a cual-mode register, noncumulative data is displ2yed for 5~X se~cnds. The dLsplay is then d~rkened for two seconds. Next, either cumulative ~r continuous-cumulative demand da~a (whicheYer is appropriate) is dis?layed for six seconds and then disp1~y l32 i6 da{kened for two seconds. Then, a six-second display ~est is performed, foll~wed by a two,second dbrk interval. This ~yclP ~hen repeats itself.
The PRDG or ~c~ r subroutine 438 is shown in flow chart foDm Ln ~iyure 9. In brief, PROG subroutine 438 det~"min~
whether regisbsr ~LC~ r 124 is connecte~ to solid-st te demand register 10 ana, if it is, oversees the reading, 102dins, or ~ltering t~e computing oo,~ L~.~s stored m nonvolatile read/wri~e memory 15~.
PF~k- subroutine 438 is entered via an entry step 900. Next, a ~eiCi~ step 902 is made bo determine whether register pLC~ - r 124 is cu-~ L~d .~ the appropriate data lines of input/out~ut port P0. If register pro~ra~mer 124 is not ~ ~le~L~l, P~OG subroutine is exited via step 908 and a return b~
main routine 400 via an uFdate label 416 ~see Figure 4A) so that the stored data can be loaded inbo scrat~hpad 212 and rereshed in nonvolatile read/ ite me~ory 152. If register ~L~JL~ r 124 is c~ L~d to t~rrin~lc 4 and 6 of input/output port P0, an cperation step 904 is ~eL e ~ ere, the ~ generated by register ~LOyL -r 124 are read and executed. These c~rm~n~c were dic~lcsp~ above. Briefly, they allow eit~er the display or ~lteration and display of the cc~putir~ constants currently stored in r~nYolatile read/write r~ory 152.
Whe~ these ~- ....lc have been read and executed, PRCG
s~br~utine 438 proce~ls to a decision step 906 r which de~rmin~
whether all of the nPc~c~ry computing O~laL~ts have stored values. If one or more of the neCpcc~ry ccmputir~ c~,laL~,ts has ~3~

no stored value, PRDG subxoutine 438 loops back to operation step 904 sa that the deficiency can be remedied. ~hen all n~r~ ry ccmputing ~ons~ants have been pLC~L~lUl~d~ PRDG subroutLne 438 prcceeds to decision blcck 910. If any of the constants 2-5 have S been progra~med then P~OG subroutine 438 proceeds to perform o~eration step ~12. Eere the cumulative and ccntinuous-cumulative E~ storage lccaticns are set to zero. PRDG s~broutine 438 i5 then exited via a step 908 and a return is made to maLn rout m e 400 via an update label 416 (see Figure 4A) so that the s~ored data can be loaded in~o ~cratchpad 212 ard refreshed in nonvolatile read/write memory 152.
Ti~keeping ~terrupt stibroutine 1000 is sha,7n in flc~ chart form Ln Figltre 10. ~riefly, interrup~ subroutine 1000 cversees the generation of denand pulses by pulse initiator 116, the ~e~auL~ ~ of ti~e by counters inbernal to miCrG~roceSgOr 100, and the ~llt;plP~ of display 132.
Interrupt ~uJr~uLine 1000 is entered via an entry step 1002 ~3ch tLme an ~lternating current maL~s-derived interrupt pulse is a~plied t~ the external-in~ru4L Lnput of ~iclqQrccessor 100 Ln ~O~OL~2n~e with the interr~pt logic ~ csp~ Ln connection with microproce~sor 100 ~c illustrated in Figure 2. Nex~, a decision step 1004 de~ n~q whether optoelectronic pulse generator 148 has applied an energy ~ Ul~ iOn pulæ to data ~r~i nAl o of input/output port P0. If no energy-consum~tion pulse ha~ been applied, the subroutine jumps to an operation ste~ 1012, in which the time ccunters internal to micrcp~cess~r 100 are clocked to reflect the fact that a time interval equal to cne period of the alte~nating current mains wdvefuLlll (16.7 milliqpe~r~q) has ~1A~S
After the tLme counters have been so prccessed, a decision step 1014 is made as to whether data are being erased fro~ or written into nonvoLatlle read/write memory 152. If an erase/write cycle is in ~L1yL~SS, the interrupt is exited via a step 1018.
When int~rrupt subrou~ine 1000 is exited, the next appropriate step of main routine 400 or the subrout~ne in pro~ress wnen the interrupt pulse was received is ~erformed. If an erase/write cycle is n~t in progress, an operation step 1016 is performed so that data is presen~ed to display 132. Be~au æ cperatiûn steo z~
~ 38 -1016 is within in~errupt subroutine 1000/ dispLay 132 is r~ ip~P~ a~ a fl1c~er-free 60 ~er~z rate. ~fter step 1016 is performed, the interrupt ~ubr~utine is exited via step 1018 and the next a~propriate step ~n main routine 400 or the appropriate other s~broutine i5 performed.
I decision step 1004 de~a"min~ that an energy-cons D tion pulse has been a~pl.ied to ~pr~inAl O of input/output port P0, cperation step 1006 is ~erfor~ed. This involves setting ener~y-consumption-pulse fl~gs Ln microprccessQr lO0 to logic 1 and proceC~ a routine goYerning ~he genera~ion of electrical-pcwer demand pul æs in ~YZ format. These pulses a~pear at the ~YZ
outputs of pulse initiator 1l6. In this routine, the value of cc~puting Wl~ L~lt 1 is evaluat~d and ~YZ output pulses are g~nerated.
After these pulses are generated, a decision 1008 is m2de.
If the nu~ber of RYZ pulses ~quals the value of ccmputi~g ~4.~ L~lt 1, a ~ES decision is reached and the ~u~uLin~ prcce~ds to cperation step lOlO. Shculd an additional ~YZ pulse be needed to equal the value of ccmputing o~ t 1, a IdO decision is 7~ade and an cperat:ion step 1012 is perfomn~d t~ toggle data ~rm;n~l 5 of input/output port P0 one n~re time. When this data 1ine is toggled, the subroutine proceeds to operation 1012.
~ecision step 1014 i5 in~ P~ because, as noted earlier, data ~r~lin~lc 0-3 of i~?ut/outE~ut port P5 provides both digit-enable signals for display drivers 138 as well as the lower four address bits of nonvolatile read/write n~3K~ry 152. If an era~e/
write cy~le is in progress, displa~ 132 is not activated. Display 132 is anly activated wh~n an erase/write cycle is not in pro~ress.
Subroutine lloa, which is followed when data is to be read fram or written into nonvolatile read/write ~emory 152, is shown in flow-chart form in Figure ll. Briefly, subroutioe 1100 sets forth the ~eeduLe ff~ when data are to be written into or read fr~an no~volatile rea~/write memory 152. It should be noted that, to write data into a location of nonvolatile read/write ~emory 152, that lf.-~tif~n must ~irst ~e erased. It takes, for ~xample, 50 millicf~onds to erase a lo~ation of nonvolatile read/
write memory 152, and another 50 ~11;5~n~5 then to write data ~ ~r;~3~

into that memory lccation. Erase and write tines are deri~ed from ti~ekeeping interruot subroutine 1000.
Subroutine 1100 is entered via an entry step 1102. Subroutine 1100 then proceeds to a decision step 1104, in which it is deter-S m m ed whether data are to be read from or written into no~volatile read/write memory I52. If data are to be ~ritten, an cperation stqp 1106 is perforned to enccde the data to ke written into the ei~ht-bit, ~amning-ccde format employed for error-detection and error coLLe_Lion ~ oses.
}O E~mming oodes are means o~ dete~tLng and c~rrecting da~a-bit errors. A ~mming code is generat~d by c~lc~ a parity bit for certain ~ 'oinations of data bits. The code bits ~re aæpended to the data bit~ and are stored in a memory device. When the me~ory device is read, new ccde bits are generated frcm the da~a bits tha~ have been read, a~d the new code bits are compared ~o ~he code bits read frcm the mem~ry device. The result of this cc~eariscn de~rmin~ the action to be taken on the data bits.
In th~ present invention, an ~xr~n~1 eight-bit E~mJning code has b~en develcped and emplcyed. The eight-bit 3ammi~g code can detect ~d co¢rect particular errors. Sp~c;f;c~lly, it can detect and correGt all singIe-bit errors. ~t can also detect all double-bit errors and most rllt;~l~bit errors. It cannot correct doubl~
bit or m~ltibit errors.
Ccde~ bits are ~ ted based on the parity of selected data bits. In the -present inve~tion, or exa~ple, the fcur most sigr~;fic;3nt bits of a given data ~rd ,re the code bits. The four least sirific~nt bits ~re ~e data bits. '~e word format is as follows~ C3 - C2 ~ CO - D3 ~ D2 ~ Dl ~ DO~ where ~ is a code bit and DN is a data bit. 'me data bits involved in pa~lty calculation are as follc~s:
CO is an od~pæity bit for the oanbination D2 ~ Dl ~ DO;
Cl is an odd-parity bit for the c~bination D3 ~ D2 ~ DO;
C2 is an odd-parity bit for the c~nbination D3 ~ D2 ~ Dl; and C3 is an odd~parity bit for the ~nbination D3 ~ Dl ~ W.
In the present invention, parity-bit calculation is performed by con3ulting a table to determine the parity bit aE~?~cpriate for a given groupLng Oe data bits.

'10 -After the data have been 50 enccded, ~hey are writte~ into the appropriate location of nonvolatile read/write ~emory 152 by ~n GperatiOn step 1108. A~fter operation step 1108 is performed, cr if it is det~rmi~ in decision step 1104 that data are not to 5 ~e written in~o nonvola~ile read/write memory 152; an oF~ratiGn step 1110 is perfonmed. ~ere, the da~a are read frcm ~he appropriate location of nonvolatile read/write memory 152.
In the case where data are being wrltten into nonvolatile read~write memory 152, this and ~he follcwing steps constitute a 10 read~fter-write ~nd validity~verification sequence. The data th~t were just written m to nonvolatile read~write memory lS2 will be read anl evaluated bo see if the prcper data have been wri~ten into that Inra~;nn of nonvolatile read/write memory lS2. This makes pn55;hl~ the detection o~ multibit errors that wculd not be 15 de~e~Ltd by the ~amming ccde.
After the data have been read from the apprcpriate l~cati~n o~ Donvolatile read/write memory lS2 in c~eration step lllO, the read data are then deccded using the ~a~mln~-code technique in an cperation step ~112. When cperation step 1~12 has been oo~pleted, 20 a decisioll step lll4 is made as to whether any errors have be~n detecte~. In the case of a write operation, the ~amming ccde bits of the & ta re~rieved from the apprcpriate location of nonvolatile read/write~ mem~ry l52 are de~Pr~in~d. Then, the ~amming ccde bits c~ the corr~c~n~in~ & ta stored in scratchpad 212 are de~prminf~
25 m e t~ sets of code bits are then ccmæaredO If they are identical, n~ bit errsrs have been intro uced by the writing of the data into the aFpropriate lo~ation of nonvolatile read/write memory l52.
If decision step lll4 determines that no errors have bee!n 30 deLec~d, subroutine llO0 is exited via an ex~t step ll22. If, however, de ision'step 1114 determines that an error or errors have been d~ Lad, a dP~i~;o~ step ll16 is made. Decision ste?
lll6 det~r~;n~ whether the deL~Led error or errors are of the single-bit or multibit type.
If the detæted error or errors are of the multibit typet it or t'ney c~t be corrected. Accordingly, an ~eratiorl step 1118 is perfocmed. Operation step 1118 sets the error flag stored in . ~

~w~ w~

scratchpad memory 2l2 to lcgic 1 t~ 5ignal that the nonvolatile read/write memory l52 contains uncorrected or uncorrectable ~rr~necus data. After cperation step ll18 is perfonmed, the routine is ~xited via exit step lll2. If, however, devision step 5 1l~6 deter~ines that a si.~3Ie~bit error or e.rrors have been de~L~d, an operation step ll20 is performed bO correct the si~le-bit error or errors. ~hen ~peration step 1120 is co~pleted, the rout m e is exited via exit step ll22.
Numercus mr~i'ications and variations of the present invention æ e E~cqihlP in light of the abore teachings. It is therefore to be u~derst~od that within the sccpe of the ~ d claims, the invention m2y be praG~iced otherwise than as ~roririr~lly described herein.

~0 ~ . :

Claims (69)

What is claimed is:

1. A register for monitoring electrical-power demand made upon alternating current mains, comprising:
(a) means, responsive to power consumed from said mains, for computing values of electrical-power demand over a succession of demand-monitoring intervals, said computing means including:
(i) sensing means for providing pulses at a rate substantially proportional to consumption of electrical energy in said mains, said pulse rate being electrically programmable;
(ii) means for defining said succession of demand-monitoring intervals;
(iii) means, responsive -to said sensing means and said defining means, for accumulating said pulses generated during each said demand-monitoring interval; and (iv) means, responsive to said accumulating means, for generating said demand monitoring interval values of electrical-power demand; and (b) means, responsive to said computing means, for determining a maximum demand-monitoring interval value of the electrical-power demand; and (c) nonvolatile read/write memory means, responsive to said determining means, for storing said maximum demand-monitoring interval value even when said memory means is deenergized.

2. A register for monitoring electrical-power demand made upon alternating current mains, comprising:
(a) means, responsive to power consumed from said mains, for computing values of electrical-power demand over a succession of demand-monitoring intervals, said computing means including:
(i) sensing means for providing pulses at a rate substantially proportional to consumption of electrical energy in said mains;

(ii) means for defining said succession of demand-monitoring intervals;
(iii) means, responsive to said sensing means and said defining means, for accumulating said pulses generated during each said demand-monitoring interval; and (iv) means, responsive to said accumulating means, for generating said demand-monitoring interval values of electrical-power demand;
(b) means, responsive to said computing means, for determining a maximum demand-monitoring interval value of the electrical-power demand;
(c) pulse initiator means, responsive to said generating means, for providing energy output pulses at a rate related to said computed values of electrical-power demand; and (d) nonvolatile read/write memory means, responsive to said determining means, for storing said maximum demand-monitoring interval value even when said memory means is deenergized.

3. The register as recited in claim 2, further comprising means, responsive to said pulse-initiator means, for electrically programming said rate of energy output pulses.

4. A register for monitoring electrical-power demand made upon alternating current mains, comprising:
(a) means, responsive to power consumed from said mains, for computing values of electrical-power demand over a succession of demand-monitoring intervals;
(b) means, responsive to said computing means, for determining a maximum demand-monitoring interval value of the electrical-power demand;
(c) means, responsive to said demand interval determining means, for encoding said maximum demand-monitoring interval value in accordance with an error-detecting and error-correcting code;

(d) nonvolatile read/write memory means, responsive to said encoding means, for storing said encoded maximum demand-monitoring interval value even when said memory means is deenergized;
(e) means, coupled to said storing means, for decoding said encoded maximum demand-monitoring interval value;
(f) means, responsive to said decoding means, for producing an error indication when said encoded maximum demand-monitoring interval value contains a particular error; and (g) means, responsive to said error indicating means, for disabling said computing means in response to said error indication.

5. The register as recited in claim 4, further comprising means, responsive to said error indicating means, for visually displaying said error indication.

6. A register for monitoring electrical-power demand made upon alternating current mains, comprising:
(a) means, responsive to power consumed from said mains, for computing values of electrical-power demand over a succession of demand-monitoring intervals;
(b) means, responsive to said computing means, for determining a maximum demand monitoring interval value of the electrical-power demand, said maximum demand-monitoring interval value being encoded as a set of digital data bits;
(c) means, responsive to said demand interval determining means, for encoding said maximum demand-monitoring interval value in accordance with an error-detecting and error-correcting code;
(d) nonvolatile read/write memory means, responsive to said encoding means, for storing said encoded maximum demand-monitoring interval value even when said memory means is deenergized; and (e) means, coupled to said storing means, for decoding said encoded maximum demand-monitoring interval value in accordance with said error-detecting and error-correcting code and for detecting any double-bit error contained in said encoded set of digital data bits.

7. The register as recited in claim 4 or 6, wherein said error-detecting code comprises an eight-bit Hamming code.

8. The register as recited in claim 4 or 6, wherein said error-detecting code comprises an eight-bit Hamming code.

9. The register as recited in claim 6, wherein said decoding means detects any single-bit error contained in said encoded set of digital data bits.

10. The register as recited in claim 6, wherein said decoding means corrects any single-bit error contained in said stored set of digital data bits.

11. The register as recited in claim 6, wherein said decoding means detects a particular multiple-bit error contained in said stored set of digital data bits.

12. the register as recited in claim t, further comprising means, responsive to said decoding means, for generating an error indication when said stored set of digital data bits contain said double-bit error or said particular multiple-bit error.

13. The register as recited in claim 12, further comprising disabling means, responsive to said error indicating means, for disabling said computing means in response to said error indication.

14. The register as recited in claim 12, further comprising display means, responsive to said error indicating means, for visually displaying said error indication.

15. A register for monitoring electrical power demand made upon alternating current mains, comprising:
(a) means, responsive to power consumed from said mains, for computing values of electrical-power demand over a succession of demand-monitoring intervals said computing means including:
(i) sensing means for providing pulses at a rate substantially proportional to consumption of electrical energy in said mains (ii) means for defining said succession of demand-monitoring intervals in accordance with the frequency of the alternating-current mains;
(iii) means, responsive to said sensing means and said defining means, for accumulating said pulses generated during each said demand-monitoring interval; and (iv) means, responsive to said accumulating means, for generating said demand-monitoring interval values of electrical-power demand;
(b) means, responsive to said computing means, for determining a maximum demand-monitoring interval value of the electrical-power demand; and (c) nonvolatile read/write memory means, responsive to said determining means, for storing said maximum demand-monitoring interval value even when said memory means is deenergized.

16. The register as recited in anyone of claims 1,2 or 15, further including display means, responsive to said generating means, for visually displaying said maximum demand-monitoring interval value.

17. The resister as recited in anyone of claims 1,2 or 15, further including display means, responsive to said generating means, for visually displaying said maximum demand-monitoring interval value; said display means further including threshold means for causing said maximum demand-monitoring interval value to be displayed only when the level of ambient light adjacent to said threshold means exceeds a preselected threshold value.

18. The register as recited in anyone of claims 1, 2 or 15, further comprising keyer means, responsive to said intervals defining means, for generating and end-of-interval pulse after each demand-monitoring interval.

19. The register as recited in anyone of claims 1, 2 or 15 further including means, responsive to said defining means, for electrically programming the time duration of said duration intervals .

20. A register for monitoring electrical-power demand made upon alternating current mains, comprising:
(a) means, responsive to power consumed from said mains, for computing values of electrical-power demand over a succession of demand-monitoring intervals;
(b) means responsive to said computing means, for determining a maximum demand-monitoring interval value of the electrical-power demand;
(c) reset means for generating successive reset indications;
(d) first means, responsive to said determining means and said reset means, for determining a current maximum demand-monitoring interval value of the electrical-power demand occurring subsequent to the most recent of said successive reset indications;
(e) means, responsive to said first means, for encoding each said current maximum demand-monitoring interval value in accordance with an error-detecting and error-correcting code;
(f) nonvolatile read/write memory means, responsive to said encoding means, for storing said encoded maximum demand-monitoring interval value even when said memory means is deenergized; and (g) addressing means, responsive to said encoding means, for causing said storing means to store only said encoded current maximum demand-monitoring interval value determined since said most recent of said successive reset indications.

21. The register as recited in claim 20, further comprising decoding means, coupled to said storing means, for decoding said most recent value of said encoded current maximum demand-monitoring interval value.

22. The register as recited in claim 21, further comprising means, responsive to said decoding means, for further an error indication when the most recent value of said encoded current maximum demand-monitoring interval value contains a particular error.

23. The register as recited in claim 22, further comprising disabling means, responsive to said error indicating means, for disabling said computing means in response to said error indication.

24. The register as recited in claim 22, further comprising display means, responsive to said error indicating means, for displaying visually said error indication.

25. A register for monitoring electrical-power demand made upon alternating current mains, comprising:
(a) means, responsive to power consumed from said mains, for computing values of electrical-power demand over a succession of demand-monitoring intervals;
(b) means, responsive to said computing means, for determining a maximum demand-monitoring interval value of the electrical-power demand;
(c) reset means for generating successive reset indications;
(d) first means, responsive to said determining means and said reset means, for determining a maximum billing period value of the electrical-power demand occurring between each pair of successive reset indications;
(e) means, responsive to said first means, for calculating a running sum equal to the summation of the maximum billing period values;
(f) encoding means, responsive to said running sum means, for error-detecting said running sum in accordance with an error-detecting and error-correcting code;

(g) nonvolatile read/write memory means, responsive to said encoding means, for storing said encoded running sum even when said memory means is deenergized; and (h) addressing means, responsive to said encoding means, for causing said storing means lo store only the most recent value of said encoded running sum.

26. The register as recited in claim 25, further comprising decoding means, coupled to said storing means, for decoding the most recent value of said decoding running sum.

27. The register as recited in claim 26, further comprising means, responsive to said according means, for producing an error indication when the most recent value of said encoded running sum contains a particular error.

28. The register as recited in claim 27, further comprising disabling means, responsive to said error indicating means, for said computing means in response to said error indication.

29. The register as recited in claim 27, further comprising display means, responsive to said error indicating means, for displaying visually said error indication.

30. The register as recited in claim 25, further comprising a display means, responsive to said running sum means, for displaying the most recent value of said running sum.

31. A register for monitoring electrical-power demand made upon alternating current mains, comprising:
(a) means, responsive to power consumed from said mains, for computing values of electrical-power demand over a succession of demand-monitoring intervals;
(b) means, responsive to said computing means, for determining a maximum demand-monitoring interval value of the electrical-power demand;
(c) reset means for generating successive reset indications;

(d) first means, responsive to said determining means and said reset means, for determining a maximum billing period value of the electrical-power demand occurring between each pair of successive reset indications;
(e) second means, responsive to said determining means and said reset means, for determining a current maximum demand-monitoring interval value of the electrical-power demand occurring subsequent to the most recent of said successive reset indications;
(f) means, responsive to said first and second means, for calculating a running sum equal to the summation of each said maximum billing period values and said current maximum demand-monitoring interval value;
(g) means, responsive to said running sum means, for encoding said running sum in accordance with an error-detecting and error-correcting code;
(h) nonvolatile read/write memory means, responsive to said encoding means, for storing said encoded running sum even when said memory means is deenergized; and (i) addressing means, responsive to said encoding means, for causing said storing means to store only the most recent value of said encoded running sum.

32. The register as recited in claim 31, further comprising means, coupled to said storing means, for decoding the most recent value of said encoded running sum.

33. The register as recited in claim 32, further comprising means, responsive to said decoding means, for producing an error indication when the most recent value of said encoded running sum contains a particular error.

34. The register as recited in claim 33, further comprising means, responsive to said error indicating means, for disabling said computing means in response to said error indication.

35. The register as recited in claim 33, further comprising means, responsive to said error indicating means, for visually displaying said error indication.

36. The register as recited in claim 31, further comprising means, responsive to said running means, for displaying the most recent value of said running sum.

37. The register as recited in claims 20,25 or 31, further comprising means, coupled to said first means, for electrically programming a mode constant for enabling said first means.

38. The register as recited in claims 20, 25 or 31, further comprising means, coupled to said first means, for electrically programming a mode constant for enabling said first means; first encoding means, responsive to said programming means, for encoding said mode constant in accordance with said error-detecting and error-correcting code, and first addressing means, responsive to said first encoding means, for causing said storage means to store said encoded mode constant.

39. The register as recited in claims 20, 25 or 31, further comprising means, coupled to said first means for electrically programming a mode constant for enabling said first means; first encoding means, responsive to said programming means, for encoding said mode constant in accordance with said error-detecting and error-correcting code, first addressing means, responsive to said first encoding means, for causing said storage means to store said encoded mode constant; and first decoding means, coupled to said storing means, for decoding said encoded mode constant.

40. The register as recited in claims 20, 25 or 31, further comprising means, coupled to said first means, for electrically programming a mode constant for enabling said first means; first encoding means, responsive to said programming means, for encoding said mode constant in accordance with said error-detecting and error correcting code, first addressing means, responsive to said first encoding means, for causing said storage means to store said encoded mode constant; first decoding means, coupled to said storing means, for decoding said encoded mode constant; and means, responsive to said decoding means, for producing an error indication when said encoded mode constant contains a particular error.

41. The register as recited in claims 20, 25 or 31, further comprising means, coupled to said first means, for electrically programming a mode constant for enabling said first means; first encoding means, responsive to said programming means, for encoding said mode constant in accordance with said error-detecting and error-correcting code, first addressing means, responsive to said first encoding means, for causing said storage means to store said encoded mode constant; first decoding means, coupled to said storing means, for decoding said encoded mode constant; means, responsive to said decoding means, for producing an error indication when said encoded mode constant contains a particular error; and means, responsive to said error indicating means, for disabling said computing means in response to said error indication.

42. The register as recited in claims 20, 25 or 31, further means, coupled to said first means, for electrically programming a mode constant for enabling said first means; first encoding means, responsive to said programming means, for encoding said mode constant in accordance with said error-detecting and error-correcting code, first addressing means, responsive to said first encoding means, for causing said storage means to store said encoded mode constant; first according means, coupled to said storing means, for decoding said encoded mode constant; means, responsive to said decoding means, for producing an error indication when said encoded mode constant contains a particular error and means, responsive to said error indicating means, for visually displaying said error indication.

43. A register for monitoring power demand upon upon alternating current mains, comprising:
(a) first pulse generating means, responsive to power consumed from said mains, for generating first pulses at a rate substantially proportional to consumption of electrical energy from said mains;
(b) second pulse generating means for generating second pulses at a rate in accordance with the frequency of the alternating-current mains;

(c) microprocessor means, coupled to said first and second pulse-generating means, for defining successive demand-monitoring intervals, for calculating a numerical value indicative of the power demand made during each successive demand-monitoring interval, and for determining a maximum numerical value indicative of the power demand;
(d) pulse-initiator means, coupled to said microprocessor means, for providing energy pulses at a rate proportional to each of said numerical values; and (e) nonvolatile read/write memory means, coupled to said microprocessor means, for storing, even when deenergized, said maximum numerical value.

44. The register as recited in claim 43, further comprising programming means, coupled to said microprocessor means, for programming the time duration of said demand-monitoring intervals and for programming said rate at which said pulse-initiator means provides said energy pulses.

45. A register for monitoring power demand made upon alternating current mains, comprising:
(a) first pulse generating means, responsive to power consumed from said mains, for generating first pulses at a rate substantially proportional to consumption of electrical energy from said mains;
(b) second pulse generating means for generating second pulses at a rate in accordance with the frequency of the alternating-current mains;
(c) microprocessor means, coupled to said first and second pulse-generating means, for defining successive demand-monitoring intervals, for calculating a numerical value indicative of the power demand made during each successive demand-monitoring interval, for determining a maximum numerical value indicative of the power demand of for encoding said maximum numerical value in accordance with an error-detecting and error-correcting code; and (d) nonvolatile read/write memory means, coupled to said microprocessor means, for storing, even when deenergized, said encoded maximum numerical value.

46. The register as recited in claim 43 or 45, wherein said nonvolatile memory means comprises an electrically alterable, read-only memory.

47. The register as recited in claim 43 or 45, further comprising means, coupled to said microprocessor means, for visually displaying said maximum numerical value.

48. The register as recited in claim 43 or 45, further comprising means, coupled to said microprocessor means, for visually displaying said maximum numerical value and further including threshold means for causing said maximum numerical value to be displayed only when the level of ambient light adjacent to said threshold means exceeds a preselected threshold value.

49. The register as recited in claim 43 or 45, wherein said maximum numerical value is stored in said nonvolatile read/write memory means as a set of binary data bits.

50. The register as recited in claim 43 or 45, further comprising keyer means, coupled to said microprocessor means for generating an end-of-interval pulse after each demand-monitoring interval.

51. The register as recited in claim 45, wherein said error-detecting and error-correcting code comprises a Hamming code.

52. The register as recited in claim 51, wherein said Hamming code comprises an eight-bit Hamming code.

53. The register as recited in claim 45 wherein said microprocessor means further comprises means, responsive to said retrieving means, for decoding in accordance with said error-detecting and error-correcting code said stored encoded maximum numerical value retrieved from said nonvolatile read/write memory means.

54. The register as recited in claim 53, wherein said microprocessor means further comprises means, responsive to said decoding means, for detecting a particular error contained in said decoded maximum numerical value.

55. The register as recited in claim 54 wherein said detecting means detects any single-bit error contained in said decoded maximum numerical value.

56. The register as recited in claim 54, wherein said microprocessor means further comprises means, responsive to said detecting means, for correcting any single-bit error contained in said decoded maximum numerical value.

57. The register as recited in claim 54, wherein said detecting means detects any double-bit error contained in said decoded maximum numerical value.

58. The register as recited in claim 54, wherein said detecting means detects a particular multiple-bit error contained in said decoded maximum numerical value.

59. A method of monitoring electrical-power demand made upon alternating current mains, comprising the steps of:
(a) measuring electrical energy consumed from said mains;
(b) computing values of electrical-power demand from said measured electrical energy over a succession of time intervals;
(c) determining a maximum value of electrical-power demand from said computed values;
(d) encoding said maximum value in accordance with an error-detecting and error-correcting code;
(e) storing said encoded maximum value in a nonvolatile read/write memory means which, even when deenergized, retains said encoded maximum value;
(f) retrieving said stored encoded maximum value from said nonvolatile read/write memory means;

(g) decoding in accordance with said error-detecting and error-correcting code said retrieved, stored encoded maximum value to produce a decoded maximum value;
(h) producing an error indication when said decoded maximum value contains a particular error; and (i) preventing the execution of step (b) in response to said error indication of step (h).

60. The method of monitoring as recited in claim 59, wherein step (d) comprises the step of:
(i) encoding said maximum value in accordance with a Hamming error-detecting and error-correcting code.

61. The method of monitoring as recited in claim 60, wherein step (g) comprises the step of:
(ii) decoding in accordance with said Hamming error-detecting and error-correcting code said retrieved stored encoded maximum value to produce a decoded maximum value.

62. The method of monitoring as recited in claim 59, further comprising the step of:
(i) visually displaying said error indication.

63. A method of monitoring electrical-power demand made upon alternating-current mains, comprising the steps of:
(a) measuring electrical energy consumed from said mains;
(b) computing values of electrical power demand from said measured electrical energy over a succession of time intervals;
(c) determining a maximum value of electrical-power demand from said computed values;
(d) encoding said maximum value in accordance with an error-detecting and error-correcting code;
(e) storing said encoded maximum value in a nonvolatile read/write memory means which, even when deenergized, retains said encoded maximum value;

(f) retrieving from said nonvolatile read/write memory means of step (e) said stored encoded maximum value in the form of a set of data bits;
(g) decoding said set of data bits in accordance with said error-detecting and error-correcting code;
(h) detecting whether said decoded set of data bits contains a particular error;
(i) determining, if a particular error has been detected, whether said particular error is a single-bit error, a double-bit error, or a multiple-bit error;
(j) correcting, if said particular error is a single-bit error, said single-bit error in accordance with said error-detecting and error-correcting code;
(k) generating, if said particular error is a double-bit or mulitple-bit error, an error indication; and (l) visually displaying said error indication of step (k).

64. The method as recited in claim 59 or 63, wherein step (b) comprises the steps of:
(i) generating pulses at a rate substantially proportional to said measured consumption of electrical energy;
(ii) defining said successive demand-monitoring intervals;
(iii) accumulating said pulses generated during each said demand-monitoring interval; and (iv) calculating from said accumulated pulses said values of electrical-power demand.

65. The method of monitoring as recited in claim 59 or 63, further comprising the step of:
(f) visually displaying said maximum value.

66. A method of monitoring electrical-power demand made upon alternating-current mains, comprising the steps of:
(a) measuring electrical energy consumed from said mains;
(b) generating first pulses at a rate substantially proportional to said measured consumption of electrical energy;

(c) generating successive reset pulses;
(d) establishing, before said generation of each successive reset pulse, successive demand-monitoring intervals;
(e) accumulating said first pulses generated during each demand-monitoring interval;
(f) calculating from said accumulated first pulses a value of electrical-power demand made during each of said successive demand-monitoring intervals;
(g) determining a maximum value of said values of electrical-power demand;
(h) encoding said maximum value in accordance with an error-detecting and error-correcting code;
(i) storing said encoded maximum value in a nonvolatile read/write memory means, which, even when deenergized, retains said encoded maximum value;
(j) resetting to a zero value said stored encoded maximum value upon a generation of the next successive reset pulse; and (k) visually displaying said maximum value of electrical power demand.

67. A method of monitoring electrical-power demand made upon alternating current mains, comprising the steps of:
(a) measuring electrical energy consumed from said mains;
(b) generating first pulses at a rate substantially proportional to said measured consumption of electrical energy;
(c) generating a succession of reset pulses;
(d) establishing successive demand-monitoring intervals;
(e) accumulating said first pulses generated during each demand-monitoring interval;
(f) calculating from said accumulated first pulses a value of electrical-power demand made during each of said successive demand-monitoring intervals;
(g) prior to the generation of the first of said reset pulses, determining a maximum value of electrical-power demand;
(h) encoding said maximum value of step (g) in accordance with an error-detecting and error-correcting code;

(i) storing said encoded maximum value of step (h) in a first location of a nonvolatile read/write memory means which, even when deenergized, retains said encoded maximum value;
(j) upon the generation of the first of said reset pulses, transferring said stored maximum value from said first location to a second location of said nonvolatile read/write memory means;
(k) upon the transfer of said stored maximum value from said first location to said second location in accordance with step (j), resetting to zero said value stored in said first location;
(l) upon the generation of each succeeding one of said reset pulses, determining a new maximum value of electrical-power demand;
(m) upon determining said new maximum value, encoding said new maximum value in accordance with said error-detecting and error-correcting code;
(n) storing said encoded new maximum value in said first location of said nonvolatile read/write memory means;
(o) upon the generation of each succeeding reset pulse, generating a sum of values equal to the summation of said maximum value and each said new maximum value for storing in said first and second locations of said nonvolatile read/write memory means;
(p) upon generating each said sum, replacing said value stored in said second location with the most recent value of said sum; and (q) upon replacing said value stored in said second locating with the most recent value of said sum, resetting to zero said value stored in said first location.

68. A method of monitoring electrical-power demand made upon alternating-current mains, comprising the steps of:
(a) measuring electrical energy consumed from said mains;
(b) generating first pulses at a rate substantially proportional to said measure consumption of electrical energy;
(c) generating a succession of reset pulses;

(d) establishing successive demand-monitoring intervals;
(e) accumulating said first pulses generated during each demand-monitoring interval;
(f) calculating from said accumulated first pulses a calculated value of electrical-power demand made during each of said successive demand-monitoring intervals;
(g) prior to the generation of the first of said reset pulses, and at the end of tile first of said successive demand-monitoring intervals, encoding said calculated value of electrical-power demand in accordance with an error-detecting and error-correcting code;
(h) storing said encoded calculated value in a first and second location of a nonvolatile, read/write memory which, even when deenergized, retains said encoded calculated value;
(i) at the end of each successive demand-monitoring interval before the generation of the first of said reset pulses, determining whether the most recent calculated value is greater than said encoded calculated value stores in said first and second locations;
(j) if the most recent calculated value is determined to be greater than said calculated value stored in said first and second locations, determining a difference between said most recent calculated value and said encoded calculated value stored in said first location;
(k) generating a sum equal to said difference and said encoded calculated value stored in said second location;
(l) replacing said encoded calculated value stored in said second location with said generated sum;
(m) replacing said encoded calculated value stored in said first location with said most recent calculated value determined to be greater in step (j);
(n) upon the generation of the first of said reset pulse, resetting said encoded calculated value stored in said first location to zero;
(o) before the generation of each successive reset pulse, determining whether the most recent value of said value of electrical-power demand calculated is greater than said encoded calculated value stored in said first location;

(p) if said most recent value of electrical-power demand calculated is determined to be greater than said encoded calculated value stored in said first location, generating a difference between said most recent value determined to be greater and said encoded calculated value stored in said first location;
(q) upon generating said difference, generating a sum of said difference and said encoded calculated value stored in said second location;
(r) upon generating said sum, replacing said encoded calculated value stored in said second location with said generated sum;
(s) upon replacing said encoded calculated value stored in said second location with said generated sum, replacing said encoded calculated value stored in said first location with said value determined to be greater; and (t) upon the generation of each successive reset pulse, resetting said encoded calculated value stored in said first location to zero.

69. The method recited in any one of claims 67 or 68, further comprising the step of visually displaying said maximum value of electrical power demand.