CA1242022A - Recloser control with independent memory - Google Patents
Recloser control with independent memoryInfo
- Publication number
- CA1242022A CA1242022A CA000482569A CA482569A CA1242022A CA 1242022 A CA1242022 A CA 1242022A CA 000482569 A CA000482569 A CA 000482569A CA 482569 A CA482569 A CA 482569A CA 1242022 A CA1242022 A CA 1242022A
- Authority
- CA
- Canada
- Prior art keywords
- recloser
- close
- power
- reset
- trip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/02—Details
- H02H3/06—Details with automatic reconnection
Abstract
ABSTRACT
A microprocessor based recloser control includ-ing a independent memory is disclosed. The independent memory is alterable by processor means and by input and output means independent of the processor means. The independent memory is non-volatile and requires little energy to alter its contents. Events which would other-wise be ignored when the processor means is disabled, be-cause of an insufficiency of power for reliable operation, are recordable in the independent memory.
A microprocessor based recloser control includ-ing a independent memory is disclosed. The independent memory is alterable by processor means and by input and output means independent of the processor means. The independent memory is non-volatile and requires little energy to alter its contents. Events which would other-wise be ignored when the processor means is disabled, be-cause of an insufficiency of power for reliable operation, are recordable in the independent memory.
Description
05 This invention relates to providing an 06 independent memory for microprocessor controlled 07 recloser controls. An example of a microprocessor 08 controlled recloser control is provided by U.S. Patent 09 No. 4,535,409 (Bray).
Generally, in an electric power 11 distribution system, there are a great number of 12 protective devices for interrupting excessive current 13 flows which tend to damage the current conductors or 14 other distribution equipment. An examination of a system would generally disclose an upstream protective 16 device close to the power source capable of 17 interrupting the entire load served by the power 18 source. The upstream device is generally succeeded by 19 a number of downstream devices of successively lesser interrupting capability, each being capable of 21 interrupting the load they protect. It is most 22 desirable to interrupt a fault, excessive current, 23 with the protective device which is closest to the 24 malfunction causing the fault in order to minimize the area of power outage. To this end, a number of 26 protective devices may be placed in series, to conduct 27 current to a load. Then when a fault occurs, only the 28 one closest to the fault should operate to interrupt 29 the fault.
It is also desirable that a protective 31 device respond quicker to faults of greater 32 magnitude than to faults of lesser magnitude.
33 However, it is not desirable that a protective 34 device respond quickly to every current in excess of design limits, since such currents may often ,~,,
Generally, in an electric power 11 distribution system, there are a great number of 12 protective devices for interrupting excessive current 13 flows which tend to damage the current conductors or 14 other distribution equipment. An examination of a system would generally disclose an upstream protective 16 device close to the power source capable of 17 interrupting the entire load served by the power 18 source. The upstream device is generally succeeded by 19 a number of downstream devices of successively lesser interrupting capability, each being capable of 21 interrupting the load they protect. It is most 22 desirable to interrupt a fault, excessive current, 23 with the protective device which is closest to the 24 malfunction causing the fault in order to minimize the area of power outage. To this end, a number of 26 protective devices may be placed in series, to conduct 27 current to a load. Then when a fault occurs, only the 28 one closest to the fault should operate to interrupt 29 the fault.
It is also desirable that a protective 31 device respond quicker to faults of greater 32 magnitude than to faults of lesser magnitude.
33 However, it is not desirable that a protective 34 device respond quickly to every current in excess of design limits, since such currents may often ,~,,
- 2 - P03-12404 be caused by a malfunction of such short duration that no harm to the system will occur. A branch striking a power line due to a gust of wind can cause such a malfunction.
Therefore, most protective devices have time current char-05 acteristics which delay their response to less excessivecurrent and yet accelerate their response, so that they respond more quickly, to faults of greater magnitude.
A graph of the time current characteristic, show-ing the time it takes for the device to respond to a fault of a specific magnitude, often results in a straight line when plotted on a log-log scale. Some care should be taken to coordinate among protective devices in a system so that the time current characteristic of an upstream protective device is always greater, i. e. responds more slowly, than a downstream device. Unless such care is taken, a larger area than necessary will suffer power outages needlessly.
Unfortunately at high magnitudes of fault cur-rent, the time current characteristics of many protective devices tend to merge. At these levels of fault, coor-dination among protective devices can be lost. When coor-dination is lost, several protective devices may respond, or an upstream protective device may respond before a downstream device. To ensure that coordination is not lost under these circumstances, a minimum time delay may be introduced for each of the devices, so that despite merger of their time current characteristics, the device furthest upstream will be the last to open because it has the longest minimum time delay. Due to the complexity of modern power distribution systems and despite precau-tions, it is not always possible or desirable that coor-dinations be preserved.
Reclosers are inserted into power lines to pro-tect a power distribution system. Most faults on power distribution lines are of momentary nature and of suffi-- cient magnitude to blow fuses if allowed to be conducted by them for a sufficient period. when a fuse does blow in
Therefore, most protective devices have time current char-05 acteristics which delay their response to less excessivecurrent and yet accelerate their response, so that they respond more quickly, to faults of greater magnitude.
A graph of the time current characteristic, show-ing the time it takes for the device to respond to a fault of a specific magnitude, often results in a straight line when plotted on a log-log scale. Some care should be taken to coordinate among protective devices in a system so that the time current characteristic of an upstream protective device is always greater, i. e. responds more slowly, than a downstream device. Unless such care is taken, a larger area than necessary will suffer power outages needlessly.
Unfortunately at high magnitudes of fault cur-rent, the time current characteristics of many protective devices tend to merge. At these levels of fault, coor-dination among protective devices can be lost. When coor-dination is lost, several protective devices may respond, or an upstream protective device may respond before a downstream device. To ensure that coordination is not lost under these circumstances, a minimum time delay may be introduced for each of the devices, so that despite merger of their time current characteristics, the device furthest upstream will be the last to open because it has the longest minimum time delay. Due to the complexity of modern power distribution systems and despite precau-tions, it is not always possible or desirable that coor-dinations be preserved.
Reclosers are inserted into power lines to pro-tect a power distribution system. Most faults on power distribution lines are of momentary nature and of suffi-- cient magnitude to blow fuses if allowed to be conducted by them for a sufficient period. when a fuse does blow in
- 3 - P03-12404 a power distribution system, it is necessary to send some-body to change it which is a somewhat expensive proposi-tion. A primary function of a recloser is to save fuses.
In general, this is done by sensing the peak value of the 05 current conducted and interrupting its flow by opening or tripping a recloser before the fuses can blow. After an interval, the recloser closes and restores power to the system where it remains closed until the next fault is sensed. The rate at which a fuse will blow and interrupt current is a function of the thermal heating of the fusi-ble element. The rate of thermal heating is proportional to the power generated by the fault and each fuse has a time current characteristic which describes the time in-terval required to interrupt the fault current. The time interval is generally approximately inversely propor-tional to the value of the root mean square, squared of the fault current. It is desirable to coordinate the re-closer with the fuses to be saved to insure that the re-closer in fact interrupts temporary fault currents before the fuses to be protected are blown. This is generally done by approximating the root mean square value of the fault current by sensing its peak value.
It must also be recognized that ali faults which occur on a power distribution line are not temporary, such as those caused by a branch momentarily falling against the line. Some faults are of a more permanent nature such as those caused by a line falling to the ground. As a con-sequence, reclosers are built so that they will only trip a limited number of times within a short duration before locking open. Were this not done a recloser would cycle until failure and many of the fuses to be protected would blow anyway. At some magnitude of fault current it is de-sirable to have the recloser open immediately to protect the line rather than following a time current character-istic. At intermediate levels, it may be desirable fromthe power distribution standpoint to allow the fault l .{~ l
In general, this is done by sensing the peak value of the 05 current conducted and interrupting its flow by opening or tripping a recloser before the fuses can blow. After an interval, the recloser closes and restores power to the system where it remains closed until the next fault is sensed. The rate at which a fuse will blow and interrupt current is a function of the thermal heating of the fusi-ble element. The rate of thermal heating is proportional to the power generated by the fault and each fuse has a time current characteristic which describes the time in-terval required to interrupt the fault current. The time interval is generally approximately inversely propor-tional to the value of the root mean square, squared of the fault current. It is desirable to coordinate the re-closer with the fuses to be saved to insure that the re-closer in fact interrupts temporary fault currents before the fuses to be protected are blown. This is generally done by approximating the root mean square value of the fault current by sensing its peak value.
It must also be recognized that ali faults which occur on a power distribution line are not temporary, such as those caused by a branch momentarily falling against the line. Some faults are of a more permanent nature such as those caused by a line falling to the ground. As a con-sequence, reclosers are built so that they will only trip a limited number of times within a short duration before locking open. Were this not done a recloser would cycle until failure and many of the fuses to be protected would blow anyway. At some magnitude of fault current it is de-sirable to have the recloser open immediately to protect the line rather than following a time current character-istic. At intermediate levels, it may be desirable fromthe power distribution standpoint to allow the fault l .{~ l
- 4 - P03-12404 current to flow for a limited period to allow the fault to burn itself open or blow the fuse. Many reclosers have alternate time current characteristcs which achieve this goal. Typically a recloser will allow two shots or trip 05 operations to follow a vast time current characteristic and two additional shots along a somewhat slower time cur-rent characteristic before locking open or out.
Microprocessor based recloser controls possess a number of advantages which were lacking in the electronic recloser controls which were their forerunners. Most advantages relate to their flexibility and self-diag-nostic abilities which largely result from their ability to store and use comparatively great amounts of informa-tion in their memory. However since microprocessor based recloser memories are controlled by processing means, the memories cannot be a'tered unless sufficient power is being supplied to the microprocessor to allow it and related devices to function reliably. Power supplies for recloser controls typically include batteries as energy storage means. However the ability to supply power to a microprocessor in a recloser control for extended periods of time when an upstream device has interrupted power to its power supply is limited. As a result, events can occur when the microprocessor is disabled which are not remembered by the microprocessor associated memory.
A particular sequence of events illustrates one drawback to the inability of microprocessor memory to function during periods of extended power outage. A given recloser trips due to a temporary fault condition. As the recloser control is attempting to reclose its battery lacks sufficient reserve to allow the microprocessor to reliably function and the microprocessor is disabled, aborting the reclosing attempt. Power is restored to the system but, the recloser remains open because the control has initialized its state and conformed to the state of the recloser. It is necessary that the control conform to a ,r
Microprocessor based recloser controls possess a number of advantages which were lacking in the electronic recloser controls which were their forerunners. Most advantages relate to their flexibility and self-diag-nostic abilities which largely result from their ability to store and use comparatively great amounts of informa-tion in their memory. However since microprocessor based recloser memories are controlled by processing means, the memories cannot be a'tered unless sufficient power is being supplied to the microprocessor to allow it and related devices to function reliably. Power supplies for recloser controls typically include batteries as energy storage means. However the ability to supply power to a microprocessor in a recloser control for extended periods of time when an upstream device has interrupted power to its power supply is limited. As a result, events can occur when the microprocessor is disabled which are not remembered by the microprocessor associated memory.
A particular sequence of events illustrates one drawback to the inability of microprocessor memory to function during periods of extended power outage. A given recloser trips due to a temporary fault condition. As the recloser control is attempting to reclose its battery lacks sufficient reserve to allow the microprocessor to reliably function and the microprocessor is disabled, aborting the reclosing attempt. Power is restored to the system but, the recloser remains open because the control has initialized its state and conformed to the state of the recloser. It is necessary that the control conform to a ,r
- 5 - P03-12404 the recloser to avoid inconsistent operation of the re-closer. The result is a power outage downstream of the recloser when no fault condtion exists.
An alternative to the outage would be to close 05 the recloser on every occasion that the control is re-supplied power. In the past a similar approach was taken but the prior control as a whole was either functional or non functional and it remembered intervening events. With a microprocessor control it is desirable to only disable the processor means, while retaining basic control func-tions independent of the microprocessor. If during the duration of power outage a secondary overcurrent trip means trips the recloser or the utility desires to change the distribution path by activating a lockout signal, it would not be desirable to close the recloser when power is resupplied to the recloser control.
SUMMARY OF THE INVENTION
The microprocessor based recloser control of my invention includes a memory means which is independent of the processor means of the control, in that it may be additionally altered by input means which are independent of the microprocessor. The independent memory is alter-able with minimal energy to allow its alteration during periods of extended control power outage. When the re-closer control is resupplied power, information in the independent memory is supplied to the processor means to allow the recloser control to appropriately respond to events occurring during a period when the processor means is disabled.
One close binary memory element of the indepen-dent memory is used as a close control bit to close the recloser, if the processor means was attempting to reclose when the processor means was disabled. The close binary element assumes a set state on processor means command, when the control is attempting a reclose if power may be 01 lost to the processor means. The processor means may also 02 command the close binary element to assume a reset state 03 under appropriate conditions. Such conditions include a 04 recloser trip or processor means response to conditions 05 which cause the processor means to issue a trip or lockout 06 command. Regardless of the operability of the processor 07 means, the close binary element will assume a reset state, 08 if the recloser control attempts to trip the recloser or 09 input means attempt to cause a trip or lockout condition.
Thus, in general, according to the present 11 invention there is provided a recloser control comprising 12 an input circuit for sensing current in each of the three 13 phases of a power line and ground, and providing an analog 14 signal for each; a data acquisition circuit including a sample and hold circuit for sampling the analog output of 16 the input circuit and maintaining it for a desired 17 preselected holding period, and an analog to digital 18 converter for converting the analog output of the sample 19 and hold circuit to a digital form. A memory is provided for storing command information in digitized form including 21 normalizing references, time current characteristics, 22 instantaneous trip values, number of operations associated 23 with a given time current characteristics, time intervals 24 for selected measurements and operations, and status information such as digitized current magnitudes; and 26 processing circuitry it provided for generating an 27 equivalent to a mean square value for each digitized 28 normalized input signal, comparing the mean square 29 equivalent values of the inputs with a preselected one of a number of time current characteristics stored in the memory 31 in accordance with other command information stored in the 32 memory, and issuing an operation command which causes the 33 recloser to change its state between close and trip 34 conditions. A power supply selectively supplies power to the other portions of the control from the power line being a9 01 protected, wherein the power supply includes a storage 02 circuit to supply power when the power lines being 03 protected are interrupted; and output circuitry is included 04 for activating a trip circuit in the recloser in accordance 05 with operation commands from the processor circuitry or 06 trip signal from the secondary overcurrent trip circuitry, 07 or close circuit in the recloser in accordance with 08 operational commands from the processor circuitry. Input 09 circuitry is provided for entering command information; and independent memory circuitry is interconnected among the 11 power supply storage circuitry, the processor circuitry and 12 the input circuitry,the independent memory circuitry 13 supplying information to the processor circuitry and being 14 alterable by the processor circuitry when the processor circuitry is supplied sufficient operating power and, being 16 alterable by the input circuitry, although the power supply 17 storage circuitry lacks sufficient power to operate the 18 processor circuitry.
-21 Fig. 1 is a block diagram of a microprocessor 22 based recloser control connected to a recloser which 23 protects a three-phase power distribution line.
24 Fig. 2 is a illustration of a portion of the recloser control relating to operator actuation of the 26 recloser.
27 Fig. 3 is a simplified block diagram of a power 28 supply used in the microprocessor based recloser control.
29 Fig. 4 illustrates a preferred embodiment of the independent memory interconnected with other portions of 31 the microprocessor based recloser control.
32 Fig. 5 is a simplified flowchart illustrating a 33 portion of the program run by a processor means of the 34 microprocessor recloser control when power is initially supplied to it.
36 -6a-01 Fig. 6 is a flowchart of the steps undertaken by 02 the processor means to issue a close signal to the 03 recloser.
04 Fig. 7 is a flowchart of a close retry routine 05 run by the processor means if the recloser control was 06 attempting to close the recloser when the processor means 07 was disabled and power is resupplied to the recloser 08 control.
36 -6b-~L~f~ 3~r~
DETAILED DESCRIPTION OF THE DRAWING
Fig. 1 illustrates a microprocessor based recloser control 10 operatively connected to a recloser 12 05 protecting a three-phase power distribution line. The re-closer control 10 includes an input circuit 14 for sensing current in each of the three phases and ground of the power distribution line and providing an analog signal of the current to data acquisition means 16. Data acquisi-tion means 16 includes a sample and hold circuit 18 whichprogressively samples the analog sisnal for each phase and ground of the input circuit 14 preferably with a multi-plexer 20 which sucessively presents each analog output of the input circuit 14 to the input of the sample and hold circuit 18. The output of the sample and hold circuit 18 is digitized by analog to digital converter 22 and there-after stored in memory means 24. Memory means 24 typi-cally comprises a variety of different kinds of solid state memories. Read only memory 24a is a non-volatile memory programmed at the factory. Read/Write Memory 24b is a volatile memory which is alterable by the micro-processor and provides information to the microprocessor.
On power loss, Read/Write Memory 24b contents are lost.
Read/Write/Save Memory 24c is a non-vola~ile memory which is alterable by the microprocessor and provides informa-tion to the microprocessor. On power loss, its contents are retained for an extended time. Processor means 26 has as a primary function generating an equivalent to a mean square value for each digitized input signal, comparing the mean square equivalent value of the inputs with a preselected one of a number of time current character-istics stored in memory means in accordance with other command information stored in the memory means, and issuing an operational command which causes the recloser to change its state between close and the t,rip conditions.
Processor means 26 additionally regulates how information n~.S~
02 is exchanged between various components of the 03 control. Programmable timers 28 in cooperation with 04 the processor means 26 determine among other things 05 the rate at which signals are multiplexed in 06 multiplexer 20 and sampled in sample and hold circuit 07 18. Power supply 30 is supplied power from the 08 upstream side of recloser 12 through a transformer 09 providing a 110 volts of alternating current. Power supply 30 provides a variety of regulated and 11 unregulated power at different voltages, selectively.
12 Recloser control 10 includes input means 32 and output 13 means 34. Input means 32 provides information to 14 recloser control 10 and includes a keyboard and a display 31 mounted on the recloser control front 16 panel. Output means 34 provides signals to open and 17 close recloser 12. Input means 32 and output means 34 18 are closely associated with interface section 36.
19 Interface section 36 accepts and issues information to and from the utility. Additionally, interface section 21 36 isolates the higher voltage components of the 22 control and higher voltage utility signals from the 23 lower voltage portions of the control, such as 24 processor means 26. Typically, isolation is achieved with optical isolaters or diode protection as 26 appropriate. Recloser control 10 further includes a 27 secondary overcurrent trip circuit 37 which allows the 28 recloser to be tripped when processor means 26 is 29 disabled for lack of power for reliable operation.
Further details of the operation and circuitry of 31 recloser control 10 are disclosed in the 32 aforementioned United States Patent No. 4,535,409.
33 Recloser control 10 additional1y has an 34 independent memory 38, which is alterable by processor means 26 and by input 32 and output 34 means 36 regardless of whether processor means 26 is enabled.
37 Independent memory 38 is alterable with minimal energy 38 supplied by power supply 30.
r f to Fig. 2 is a schematic showing interconnections between recloser control 10 and recloser 12 in greater de-tail. Pistol grip switch 32a is a double pole, double throw switch mounted on the front panel of recloser con-05 trol 10. Pistol grip switch 32a is spring loaded to re-turn to its neutral position and allows an operator to change the state of the recloser 12 at its location. If it is desired to allow only remote actuation of recloser 12, defeat contacts 40, operable from the front panel of recloser control 10, may be opened. The poles in pistol grip switch 32a serve markedly different functions. Pole 42 provides a hard-wire connection to ground for trip coil 44 causing recloser 12 to open when pistol grip 32a is thrown to the trip position. Same interlock contact 46 is located in recloser 12 and is mechanically interlocked to assume the same state as the recloser interrupting con-tacts. Trip coil 44 obtains power from Power Supply 30.
Signal pole 48 provides information to processor means 26 which cause it to issue either a trip or close command. When pole 48 is switched to the trip position it functions through the agency of processor means 26 to issue a trip signal to recloser 12. When pole 48 is thrown to the close position, it causes processor means 26 to ground close coil 50. Opposite interlock contact 52 is mechanically interlocked with the switch mechanism of re-closer 12 to assume a opposite state to the interrupting contacts. Breaker contact 54, also a mechanically actu-ated contact in the recloser, is actuated by a lever bar which forces the main interrupting contacts to an open or tripped position. Non-reclose contact 56 is operable from the front panel of recloser control 10 to prevent re-closing a tripped recloser. Trip monitor lead 58 and close monitor lead 60 provide recloser state information to the remainder of the control 10 through interface sec-tion 36.
f Fig. 3 is a simplified schematic of power supply 30~ It includes transformer 62 which converts the nominal 110 volt alternating current supply to a nominal 24 volts.
Rectifier 64 rectifies to direct current the 24 volt al-05 ternating current supplied. Regulator 66 provides, amongother things, a regulated 24 volt supply and charges energy storage means 68, which is preferably a battery.
Fig. 4 illustrates a preferred embodiment of in-dependent memory 38 and some of its interconnections to input means 32 and output means 34 of recloser control 10.
Independent memory 38 is preferrably assembled with low energy latching relays. Only a single binary close memory element 70(one relay is illustrated. It is well within the skill of the art to use a number ox latching relays to lS -build a multi-element independent memory from the illus-tration. Close memory element 70 includes a sensed pole 72 switchable between a set sensed contact 74 and a reset sensed contact 76. A second or power pole 78 of the double pole double throw latching relay is ganged with sensed pole 72 and is switchable between set power contact 80 and reset power contact 82. Poles 72 and 78 are switched to their set position by energizing set coil 84.
Set coil 84 is connected at its power termination 86 to the B+ supply of power supply 30. Set coil 84 is ener-gized by activating set switch 88 which is connected be-tween a set coil switched termination 90 and ground. Set switch 88 is a portion of interface section 38 and, is preferably an optically isolated switch including a light emitting diode 88a and a photo transistor 88b.
Poles 72 and 78 of closed memory element 70 are urged to their reset contacts by reset coil 92. Reset coil 92 has its power termination 94 connected Jo the set power contact 80. When power pole 78 is in the set posi-tion, power termination 94 is connected to the B+ supply of power supply 30. Reset capacitor 96 is connected be tween power termination 94 and ground. When close memory 02 element 70 is in a set condition reset capacitor 96 is 03 charged with sufficient energy to reset close memory 04 element 70 when reset coil 92 is grounded. Switched 05 termination 98 of reset coil 92 may be grounded through 06 a variety of paths. Processor means 26 can issue a 07 signal to reset switch 100 causing it to complete the 08 path between switched termination 98 and ground. Reset 09 switch 100 operates similarly to set switch 88.
Additional paths to ground are also provided in 11 interface section 36. Input means 32 include trip 12 contacts of pistol grip switch 32a. When pole 48 is 13 thrown to the trip position, close memory element 70 is 14 reset. Similarly, when remote lockout contact 102 is thrown to ground, by the utility, close memory element 16 70 assumes a reset condition. Recloser 12 can receive a 17 trip signal from interface section 36 which includes 18 trip circuitry 104. Trip circuitry 104 is separately 19 shown in Fig. 1 to emphasize that it is operable by secondary overcurrent trip circuit 38. Trip switch 106, 21 here shown as a SCR, is the portion of trip circuitry 22 104 which grounds trip coil 44 through conductor 108.
23 Processor means 26 may set close memory 24 element 70 by activating set switch 88. Similarly, close memory element 70 may be caused to assume a 26 reset state on processor means 26 command by means of 27 reset switch 100. Additionally, it may assume a reset 28 state on a signal furnished by input means 32 or trip 29 switch 106.
Microprocessor base recloser control 10 31 functions to appropriately open and close recloser 12 32 by means of a variety of complex algorithms or steps 33 to insure proper operation under a variety of condi-34 tions. A detail explanation of some of the more subtle algorithms is provided in United States Patent No.
36 4,535,409. Simplified flowcharts illustrating the 37 program steps using independent memory 38 are presented 38 in Figs. 5, 6 and 7 of the drawing in this application.
Fig. 5 is a simplified flowchart of the initial steps the processor means 26 performs when stored energy is sufficient to insure its reliable operation. The power up routine 200 only illustrates those steps necessary to 05 understand how processor means 26 accepts information from close memory element 70. The close memory element 70 is first examined in decision diamond 202. If the close memory element 70 is in set state, the recloser must be tripped and, a control state flag is set to a trip state in block 204. Next a close routine is called in block 205. This close routine is illustrated in Fig. 6.
Ultimately when power up routine is completed, processor means 26 exits from the routine at point 206. If the close memory element 70 is found to be reset in decision 15 _diamond 202, a control state flag is set to a close state in block 208. Thereafter the processor means exits from power up routine 200 at exit block 206.
On the completion of power up routine 200 close routine 108 illustrated in Figl 6 is performed when close memory element 70 is in a set state. Close routine 108 begins with the issuance of a close signal 110. After a suitable delay the state of the recloser and whether a lock out condition exist is made in decision diamond 114.
Decision diamond 114 performs a software check to see whether the control state flag, settable in block 208 of power up routine 200, is set. At this point, decision diamond 114, a lock flag state is also examined to see if it is sex. If the recloser is closed or locked out, the program is immediately terminated in exit step 116. If the recloser is open but not locked out, a determination is made as to whether a close retry routine should be run in decision diamond 118. This provision allows the infor-mation contained in close memory element 70 to be ignored.
Under some conditions it may be desirable to bypass the set close routine such as when the utility orders a remote close signal or the pistol grip switch 32 is operated. If g the set close routine is not to be run, a close signal is issued in block 120. After a suitable period of time, a determination as to whether or not a close occurred is made in close decision diamond 122. If the recloser did 05 not successfully close, a command is issued to lock out the recloser control in lock out block 124. Thereafter, the program is completed in exit point 116. In the event that the close was successful, as determined in close de-cision diamond 122, a sequence position reset timer is started in block 126. After a suitable period of time, the microprocessor recloser control will initialize the sequence position memory when the timer times out. After the sequence timer is started in block 126 the program terminates in exit point 116.
If the close retry routine was not defeated in decision diamond 118, the close retry routine is run in block 128. The close retry routine is further explained in Fig. 7. After it is run in block 128, the program pro-ceeds to close decision diamond 122 and the steps there-after are the same as those following the step of issuing a close in close block 120. As may be readily appreci-ated, close retry block 128 is in fact a branching in-struction which compresses Fig. 7 into close routine 108.
The first step in the close retry routine 130 is to initialized close retry time in block 132. Close retry time is the interval between successive attempts to re-close the recloser 12. This time is programmable to a period between 1 and 60 seconds. After initialization in block 132, a close command is issued in block 134. The duration of a close command also is selectively program-mable to a period between 1 and 100 cycles of the 60 Hertz current. After this interval, the state of recloser 12 is checked in decision diamond 136. If the recloser has closed or is locked out, close memory element 70 is reset in reset block 138 and the program is completed at exit point 140. If it is determined, in decision block 136, that the recloser is open and unlocked the close memory element 70 is set in block 142. Thereafter, in decision diamond 144, the state of the recloser is reexamined. If the recloser is closed, the program skips to reset block 05 138. In the event that the recloser is not closed, a check is made in decision diamond 146 to see whether or not the time for the recloser to close has elapsed. If the recloser has failed to close in time, another attempt to reclose is jade in block 148 after the closed retry time has elapsed. Thereafter, the program branches back to a reexamination of the recloser in decision diamond 144 and proceeds. In the event that the recloser failed to reclose as determined in block 146 an inconsistent state existsO Under that condition the control is locked out in lockout block 150 and the program proceeds to reset the independent memory in block 138.
It should be understood that various modifica-tions, changes and variation may be made in the arrangment operation and details of construction of the elements and processes disclosed herein without departing from the spirit and scope of this invention.
An alternative to the outage would be to close 05 the recloser on every occasion that the control is re-supplied power. In the past a similar approach was taken but the prior control as a whole was either functional or non functional and it remembered intervening events. With a microprocessor control it is desirable to only disable the processor means, while retaining basic control func-tions independent of the microprocessor. If during the duration of power outage a secondary overcurrent trip means trips the recloser or the utility desires to change the distribution path by activating a lockout signal, it would not be desirable to close the recloser when power is resupplied to the recloser control.
SUMMARY OF THE INVENTION
The microprocessor based recloser control of my invention includes a memory means which is independent of the processor means of the control, in that it may be additionally altered by input means which are independent of the microprocessor. The independent memory is alter-able with minimal energy to allow its alteration during periods of extended control power outage. When the re-closer control is resupplied power, information in the independent memory is supplied to the processor means to allow the recloser control to appropriately respond to events occurring during a period when the processor means is disabled.
One close binary memory element of the indepen-dent memory is used as a close control bit to close the recloser, if the processor means was attempting to reclose when the processor means was disabled. The close binary element assumes a set state on processor means command, when the control is attempting a reclose if power may be 01 lost to the processor means. The processor means may also 02 command the close binary element to assume a reset state 03 under appropriate conditions. Such conditions include a 04 recloser trip or processor means response to conditions 05 which cause the processor means to issue a trip or lockout 06 command. Regardless of the operability of the processor 07 means, the close binary element will assume a reset state, 08 if the recloser control attempts to trip the recloser or 09 input means attempt to cause a trip or lockout condition.
Thus, in general, according to the present 11 invention there is provided a recloser control comprising 12 an input circuit for sensing current in each of the three 13 phases of a power line and ground, and providing an analog 14 signal for each; a data acquisition circuit including a sample and hold circuit for sampling the analog output of 16 the input circuit and maintaining it for a desired 17 preselected holding period, and an analog to digital 18 converter for converting the analog output of the sample 19 and hold circuit to a digital form. A memory is provided for storing command information in digitized form including 21 normalizing references, time current characteristics, 22 instantaneous trip values, number of operations associated 23 with a given time current characteristics, time intervals 24 for selected measurements and operations, and status information such as digitized current magnitudes; and 26 processing circuitry it provided for generating an 27 equivalent to a mean square value for each digitized 28 normalized input signal, comparing the mean square 29 equivalent values of the inputs with a preselected one of a number of time current characteristics stored in the memory 31 in accordance with other command information stored in the 32 memory, and issuing an operation command which causes the 33 recloser to change its state between close and trip 34 conditions. A power supply selectively supplies power to the other portions of the control from the power line being a9 01 protected, wherein the power supply includes a storage 02 circuit to supply power when the power lines being 03 protected are interrupted; and output circuitry is included 04 for activating a trip circuit in the recloser in accordance 05 with operation commands from the processor circuitry or 06 trip signal from the secondary overcurrent trip circuitry, 07 or close circuit in the recloser in accordance with 08 operational commands from the processor circuitry. Input 09 circuitry is provided for entering command information; and independent memory circuitry is interconnected among the 11 power supply storage circuitry, the processor circuitry and 12 the input circuitry,the independent memory circuitry 13 supplying information to the processor circuitry and being 14 alterable by the processor circuitry when the processor circuitry is supplied sufficient operating power and, being 16 alterable by the input circuitry, although the power supply 17 storage circuitry lacks sufficient power to operate the 18 processor circuitry.
-21 Fig. 1 is a block diagram of a microprocessor 22 based recloser control connected to a recloser which 23 protects a three-phase power distribution line.
24 Fig. 2 is a illustration of a portion of the recloser control relating to operator actuation of the 26 recloser.
27 Fig. 3 is a simplified block diagram of a power 28 supply used in the microprocessor based recloser control.
29 Fig. 4 illustrates a preferred embodiment of the independent memory interconnected with other portions of 31 the microprocessor based recloser control.
32 Fig. 5 is a simplified flowchart illustrating a 33 portion of the program run by a processor means of the 34 microprocessor recloser control when power is initially supplied to it.
36 -6a-01 Fig. 6 is a flowchart of the steps undertaken by 02 the processor means to issue a close signal to the 03 recloser.
04 Fig. 7 is a flowchart of a close retry routine 05 run by the processor means if the recloser control was 06 attempting to close the recloser when the processor means 07 was disabled and power is resupplied to the recloser 08 control.
36 -6b-~L~f~ 3~r~
DETAILED DESCRIPTION OF THE DRAWING
Fig. 1 illustrates a microprocessor based recloser control 10 operatively connected to a recloser 12 05 protecting a three-phase power distribution line. The re-closer control 10 includes an input circuit 14 for sensing current in each of the three phases and ground of the power distribution line and providing an analog signal of the current to data acquisition means 16. Data acquisi-tion means 16 includes a sample and hold circuit 18 whichprogressively samples the analog sisnal for each phase and ground of the input circuit 14 preferably with a multi-plexer 20 which sucessively presents each analog output of the input circuit 14 to the input of the sample and hold circuit 18. The output of the sample and hold circuit 18 is digitized by analog to digital converter 22 and there-after stored in memory means 24. Memory means 24 typi-cally comprises a variety of different kinds of solid state memories. Read only memory 24a is a non-volatile memory programmed at the factory. Read/Write Memory 24b is a volatile memory which is alterable by the micro-processor and provides information to the microprocessor.
On power loss, Read/Write Memory 24b contents are lost.
Read/Write/Save Memory 24c is a non-vola~ile memory which is alterable by the microprocessor and provides informa-tion to the microprocessor. On power loss, its contents are retained for an extended time. Processor means 26 has as a primary function generating an equivalent to a mean square value for each digitized input signal, comparing the mean square equivalent value of the inputs with a preselected one of a number of time current character-istics stored in memory means in accordance with other command information stored in the memory means, and issuing an operational command which causes the recloser to change its state between close and the t,rip conditions.
Processor means 26 additionally regulates how information n~.S~
02 is exchanged between various components of the 03 control. Programmable timers 28 in cooperation with 04 the processor means 26 determine among other things 05 the rate at which signals are multiplexed in 06 multiplexer 20 and sampled in sample and hold circuit 07 18. Power supply 30 is supplied power from the 08 upstream side of recloser 12 through a transformer 09 providing a 110 volts of alternating current. Power supply 30 provides a variety of regulated and 11 unregulated power at different voltages, selectively.
12 Recloser control 10 includes input means 32 and output 13 means 34. Input means 32 provides information to 14 recloser control 10 and includes a keyboard and a display 31 mounted on the recloser control front 16 panel. Output means 34 provides signals to open and 17 close recloser 12. Input means 32 and output means 34 18 are closely associated with interface section 36.
19 Interface section 36 accepts and issues information to and from the utility. Additionally, interface section 21 36 isolates the higher voltage components of the 22 control and higher voltage utility signals from the 23 lower voltage portions of the control, such as 24 processor means 26. Typically, isolation is achieved with optical isolaters or diode protection as 26 appropriate. Recloser control 10 further includes a 27 secondary overcurrent trip circuit 37 which allows the 28 recloser to be tripped when processor means 26 is 29 disabled for lack of power for reliable operation.
Further details of the operation and circuitry of 31 recloser control 10 are disclosed in the 32 aforementioned United States Patent No. 4,535,409.
33 Recloser control 10 additional1y has an 34 independent memory 38, which is alterable by processor means 26 and by input 32 and output 34 means 36 regardless of whether processor means 26 is enabled.
37 Independent memory 38 is alterable with minimal energy 38 supplied by power supply 30.
r f to Fig. 2 is a schematic showing interconnections between recloser control 10 and recloser 12 in greater de-tail. Pistol grip switch 32a is a double pole, double throw switch mounted on the front panel of recloser con-05 trol 10. Pistol grip switch 32a is spring loaded to re-turn to its neutral position and allows an operator to change the state of the recloser 12 at its location. If it is desired to allow only remote actuation of recloser 12, defeat contacts 40, operable from the front panel of recloser control 10, may be opened. The poles in pistol grip switch 32a serve markedly different functions. Pole 42 provides a hard-wire connection to ground for trip coil 44 causing recloser 12 to open when pistol grip 32a is thrown to the trip position. Same interlock contact 46 is located in recloser 12 and is mechanically interlocked to assume the same state as the recloser interrupting con-tacts. Trip coil 44 obtains power from Power Supply 30.
Signal pole 48 provides information to processor means 26 which cause it to issue either a trip or close command. When pole 48 is switched to the trip position it functions through the agency of processor means 26 to issue a trip signal to recloser 12. When pole 48 is thrown to the close position, it causes processor means 26 to ground close coil 50. Opposite interlock contact 52 is mechanically interlocked with the switch mechanism of re-closer 12 to assume a opposite state to the interrupting contacts. Breaker contact 54, also a mechanically actu-ated contact in the recloser, is actuated by a lever bar which forces the main interrupting contacts to an open or tripped position. Non-reclose contact 56 is operable from the front panel of recloser control 10 to prevent re-closing a tripped recloser. Trip monitor lead 58 and close monitor lead 60 provide recloser state information to the remainder of the control 10 through interface sec-tion 36.
f Fig. 3 is a simplified schematic of power supply 30~ It includes transformer 62 which converts the nominal 110 volt alternating current supply to a nominal 24 volts.
Rectifier 64 rectifies to direct current the 24 volt al-05 ternating current supplied. Regulator 66 provides, amongother things, a regulated 24 volt supply and charges energy storage means 68, which is preferably a battery.
Fig. 4 illustrates a preferred embodiment of in-dependent memory 38 and some of its interconnections to input means 32 and output means 34 of recloser control 10.
Independent memory 38 is preferrably assembled with low energy latching relays. Only a single binary close memory element 70(one relay is illustrated. It is well within the skill of the art to use a number ox latching relays to lS -build a multi-element independent memory from the illus-tration. Close memory element 70 includes a sensed pole 72 switchable between a set sensed contact 74 and a reset sensed contact 76. A second or power pole 78 of the double pole double throw latching relay is ganged with sensed pole 72 and is switchable between set power contact 80 and reset power contact 82. Poles 72 and 78 are switched to their set position by energizing set coil 84.
Set coil 84 is connected at its power termination 86 to the B+ supply of power supply 30. Set coil 84 is ener-gized by activating set switch 88 which is connected be-tween a set coil switched termination 90 and ground. Set switch 88 is a portion of interface section 38 and, is preferably an optically isolated switch including a light emitting diode 88a and a photo transistor 88b.
Poles 72 and 78 of closed memory element 70 are urged to their reset contacts by reset coil 92. Reset coil 92 has its power termination 94 connected Jo the set power contact 80. When power pole 78 is in the set posi-tion, power termination 94 is connected to the B+ supply of power supply 30. Reset capacitor 96 is connected be tween power termination 94 and ground. When close memory 02 element 70 is in a set condition reset capacitor 96 is 03 charged with sufficient energy to reset close memory 04 element 70 when reset coil 92 is grounded. Switched 05 termination 98 of reset coil 92 may be grounded through 06 a variety of paths. Processor means 26 can issue a 07 signal to reset switch 100 causing it to complete the 08 path between switched termination 98 and ground. Reset 09 switch 100 operates similarly to set switch 88.
Additional paths to ground are also provided in 11 interface section 36. Input means 32 include trip 12 contacts of pistol grip switch 32a. When pole 48 is 13 thrown to the trip position, close memory element 70 is 14 reset. Similarly, when remote lockout contact 102 is thrown to ground, by the utility, close memory element 16 70 assumes a reset condition. Recloser 12 can receive a 17 trip signal from interface section 36 which includes 18 trip circuitry 104. Trip circuitry 104 is separately 19 shown in Fig. 1 to emphasize that it is operable by secondary overcurrent trip circuit 38. Trip switch 106, 21 here shown as a SCR, is the portion of trip circuitry 22 104 which grounds trip coil 44 through conductor 108.
23 Processor means 26 may set close memory 24 element 70 by activating set switch 88. Similarly, close memory element 70 may be caused to assume a 26 reset state on processor means 26 command by means of 27 reset switch 100. Additionally, it may assume a reset 28 state on a signal furnished by input means 32 or trip 29 switch 106.
Microprocessor base recloser control 10 31 functions to appropriately open and close recloser 12 32 by means of a variety of complex algorithms or steps 33 to insure proper operation under a variety of condi-34 tions. A detail explanation of some of the more subtle algorithms is provided in United States Patent No.
36 4,535,409. Simplified flowcharts illustrating the 37 program steps using independent memory 38 are presented 38 in Figs. 5, 6 and 7 of the drawing in this application.
Fig. 5 is a simplified flowchart of the initial steps the processor means 26 performs when stored energy is sufficient to insure its reliable operation. The power up routine 200 only illustrates those steps necessary to 05 understand how processor means 26 accepts information from close memory element 70. The close memory element 70 is first examined in decision diamond 202. If the close memory element 70 is in set state, the recloser must be tripped and, a control state flag is set to a trip state in block 204. Next a close routine is called in block 205. This close routine is illustrated in Fig. 6.
Ultimately when power up routine is completed, processor means 26 exits from the routine at point 206. If the close memory element 70 is found to be reset in decision 15 _diamond 202, a control state flag is set to a close state in block 208. Thereafter the processor means exits from power up routine 200 at exit block 206.
On the completion of power up routine 200 close routine 108 illustrated in Figl 6 is performed when close memory element 70 is in a set state. Close routine 108 begins with the issuance of a close signal 110. After a suitable delay the state of the recloser and whether a lock out condition exist is made in decision diamond 114.
Decision diamond 114 performs a software check to see whether the control state flag, settable in block 208 of power up routine 200, is set. At this point, decision diamond 114, a lock flag state is also examined to see if it is sex. If the recloser is closed or locked out, the program is immediately terminated in exit step 116. If the recloser is open but not locked out, a determination is made as to whether a close retry routine should be run in decision diamond 118. This provision allows the infor-mation contained in close memory element 70 to be ignored.
Under some conditions it may be desirable to bypass the set close routine such as when the utility orders a remote close signal or the pistol grip switch 32 is operated. If g the set close routine is not to be run, a close signal is issued in block 120. After a suitable period of time, a determination as to whether or not a close occurred is made in close decision diamond 122. If the recloser did 05 not successfully close, a command is issued to lock out the recloser control in lock out block 124. Thereafter, the program is completed in exit point 116. In the event that the close was successful, as determined in close de-cision diamond 122, a sequence position reset timer is started in block 126. After a suitable period of time, the microprocessor recloser control will initialize the sequence position memory when the timer times out. After the sequence timer is started in block 126 the program terminates in exit point 116.
If the close retry routine was not defeated in decision diamond 118, the close retry routine is run in block 128. The close retry routine is further explained in Fig. 7. After it is run in block 128, the program pro-ceeds to close decision diamond 122 and the steps there-after are the same as those following the step of issuing a close in close block 120. As may be readily appreci-ated, close retry block 128 is in fact a branching in-struction which compresses Fig. 7 into close routine 108.
The first step in the close retry routine 130 is to initialized close retry time in block 132. Close retry time is the interval between successive attempts to re-close the recloser 12. This time is programmable to a period between 1 and 60 seconds. After initialization in block 132, a close command is issued in block 134. The duration of a close command also is selectively program-mable to a period between 1 and 100 cycles of the 60 Hertz current. After this interval, the state of recloser 12 is checked in decision diamond 136. If the recloser has closed or is locked out, close memory element 70 is reset in reset block 138 and the program is completed at exit point 140. If it is determined, in decision block 136, that the recloser is open and unlocked the close memory element 70 is set in block 142. Thereafter, in decision diamond 144, the state of the recloser is reexamined. If the recloser is closed, the program skips to reset block 05 138. In the event that the recloser is not closed, a check is made in decision diamond 146 to see whether or not the time for the recloser to close has elapsed. If the recloser has failed to close in time, another attempt to reclose is jade in block 148 after the closed retry time has elapsed. Thereafter, the program branches back to a reexamination of the recloser in decision diamond 144 and proceeds. In the event that the recloser failed to reclose as determined in block 146 an inconsistent state existsO Under that condition the control is locked out in lockout block 150 and the program proceeds to reset the independent memory in block 138.
It should be understood that various modifica-tions, changes and variation may be made in the arrangment operation and details of construction of the elements and processes disclosed herein without departing from the spirit and scope of this invention.
Claims (8)
1. A recloser control comprising:
an input circuit for sensing current in each of the three phases of a power line and ground, and pro-viding an analog signal for each;
a data acquisition means including a sample and hold circuit for sampling the analog output of the input circuit and maintaining it for a desired preselected holding period, and an analog to digital converter for converting the analog output of the sample and hold cir-cuit to a digital form;
memory means for storing command informa-tion in digitized form including normalizing references, time current characteristics, instantaneous trip values, number of operations associated with a given time current characteristics, time intervals for selected measurements and operations, and status information such as digitized current magnitudes;
processing means for generating an equiva-lent to a mean square value for each digitized normalized input signal, comparing the mean square equivalent values of the inputs with a preselected one of a number of time current characteristics stored in memory means in accor-dance with other command information stored in the memory means, and issuing an operation command which causes the recloser to change its state between close and trip condi-tions;
a power supply for selectively supplying power to the other portions of the control from the power line being protected, said power supply including a stor-age means to supply power when the power lines being pro-tected are interrupted;
output means for activating trip means in the recloser in accordance with operation commands from the processor means or trip signal from the secondary overcurrent trip circuitry, or close means in the recloser in accordance with operational commands from the processor means;
input means for entering command informa-tion; and independent memory means interconnected among said power supply storage means, said processor means and said input means, said independent memory means supplying information to said processor means and being alterable by said processor means when said processor means is supplied sufficient operating power and, being alterable by said input means, although said power supply storage means lacks sufficient power to operate the pro-cessor means.
an input circuit for sensing current in each of the three phases of a power line and ground, and pro-viding an analog signal for each;
a data acquisition means including a sample and hold circuit for sampling the analog output of the input circuit and maintaining it for a desired preselected holding period, and an analog to digital converter for converting the analog output of the sample and hold cir-cuit to a digital form;
memory means for storing command informa-tion in digitized form including normalizing references, time current characteristics, instantaneous trip values, number of operations associated with a given time current characteristics, time intervals for selected measurements and operations, and status information such as digitized current magnitudes;
processing means for generating an equiva-lent to a mean square value for each digitized normalized input signal, comparing the mean square equivalent values of the inputs with a preselected one of a number of time current characteristics stored in memory means in accor-dance with other command information stored in the memory means, and issuing an operation command which causes the recloser to change its state between close and trip condi-tions;
a power supply for selectively supplying power to the other portions of the control from the power line being protected, said power supply including a stor-age means to supply power when the power lines being pro-tected are interrupted;
output means for activating trip means in the recloser in accordance with operation commands from the processor means or trip signal from the secondary overcurrent trip circuitry, or close means in the recloser in accordance with operational commands from the processor means;
input means for entering command informa-tion; and independent memory means interconnected among said power supply storage means, said processor means and said input means, said independent memory means supplying information to said processor means and being alterable by said processor means when said processor means is supplied sufficient operating power and, being alterable by said input means, although said power supply storage means lacks sufficient power to operate the pro-cessor means.
2. A recloser control as claimed in Claim 1 wherein said independent memory means is a single binary close memory element which assumes a set state when said processor means is attempting to close the controlled re-closer and assumes a reset state when the close is com-pleted on processor means command, the single binary element may assume a reset state although the micro-processor is disabled if any input means assumes a trip state.
3. A recloser control as claimed in Claim 1 wherein said independent memory comprises at least one low energy latching relay.
4. A recloser control as claimed in Claim 3 wherein said latching relay includes:
a sensed pole switchable between set and re-set sensed contacts to supply information to said pro-cessor means;
a power pole ganged with said sensed pole connected to one leg of said power supply and switchable with said sensed pole between set and reset power con-tacts;
a set coil connected to the one leg of said power supply at said set coil's power termination contact for switching said poles to engage their set contacts.
a reset coil connected to said set power contact at said reset coil's power termination for switch-ing said poles to engage their reset contacts and, further including;
a reset capacitor connected between said set power contact and an opposite leg of said power supply to supply energy to said reset coil;
a set switch responsive to processor means command connected between said set coil's switched ter-mination and the opposited leg of said power supply for energizing said set coil on issuance of a processor means set command; and a reset switch responsive to processor means command connected between said reset coil's switched termination and the opposite leg of said power supply for energizing said reset coil on issuance of a processor means reset command, the switched termination of said re-set coil also connected to input means switches connected to the opposite leg of said power supply for energizing said reset coil independently of said processor means.
a sensed pole switchable between set and re-set sensed contacts to supply information to said pro-cessor means;
a power pole ganged with said sensed pole connected to one leg of said power supply and switchable with said sensed pole between set and reset power con-tacts;
a set coil connected to the one leg of said power supply at said set coil's power termination contact for switching said poles to engage their set contacts.
a reset coil connected to said set power contact at said reset coil's power termination for switch-ing said poles to engage their reset contacts and, further including;
a reset capacitor connected between said set power contact and an opposite leg of said power supply to supply energy to said reset coil;
a set switch responsive to processor means command connected between said set coil's switched ter-mination and the opposited leg of said power supply for energizing said set coil on issuance of a processor means set command; and a reset switch responsive to processor means command connected between said reset coil's switched termination and the opposite leg of said power supply for energizing said reset coil on issuance of a processor means reset command, the switched termination of said re-set coil also connected to input means switches connected to the opposite leg of said power supply for energizing said reset coil independently of said processor means.
5. A recloser control as claimed in Claim 4 wherein the switched termination of said reset coil is also connected to a trip switch controlling a trip coil of a recloser to insure that said latching relay assumes a reset condition any time a trip operation is initiated, by connecting the switched termination of said reset coil to the opposite leg of said power supply.
6. A recloser control as claimed in Claim 4 wherein said set switch is a phototransistor activated by a light emitting diode; and said reset switch is a photo transistor activated by a light emitting diode.
7. The recloser control claimed in Claim 1 wherein the processor means carries out a predetermined sequence of steps to insure that the recloser will close when the recloser control is repowered after a loss of power, if recloser was attempting to close when power was lost causing a single binary close memory element of said independent memory to assume a set state, said predeter-mined sequence of steps including:
determining whether the close memory element of said independent memory has assumed a set state;
issuing a close command if said single binary element has assumed a set state;
determining whether the recloser failed to close within a predetermined close time; and reissuing a close command if the recloser has failed to close within the predetermined close time
determining whether the close memory element of said independent memory has assumed a set state;
issuing a close command if said single binary element has assumed a set state;
determining whether the recloser failed to close within a predetermined close time; and reissuing a close command if the recloser has failed to close within the predetermined close time
8. The recloser control claimed in Claim 1 wherein said processor means carries out a predetermined sequence of steps in issuing an operation command to change the recloser from a trip condition to a close con-dition including:
initializing a close retry time;
issuing a close signal to said output means;
determining if the recloser is closed or locked out after a predetermined close time;
causing a single binary close memory element of said independent memory to assume a reset state, if said recloser is closed or locked out;
causing the close memory element of said in-dependent memory to assume a set state, if said recloser is open and not locked out;
redetermining if the recloser is closed after a predetermined close time;
causing the close memory element to assume a reset state, if the recloser is closed;
determining if the recloser has failed to close within the predetermined closing time if the re-closer is not closed;
reissuing a close signal to said output means after a predetermined close retry time delay, if the recloser was determined to have failed to close within the predetermined close time and returning to the above step of redetermining if the recloser is closed;
locking out the recloser, if the recloser was determined to have failed to close for a reason uncon-nected with a mere elapse of the close time; and causing the close memory element to assume a reset state.
initializing a close retry time;
issuing a close signal to said output means;
determining if the recloser is closed or locked out after a predetermined close time;
causing a single binary close memory element of said independent memory to assume a reset state, if said recloser is closed or locked out;
causing the close memory element of said in-dependent memory to assume a set state, if said recloser is open and not locked out;
redetermining if the recloser is closed after a predetermined close time;
causing the close memory element to assume a reset state, if the recloser is closed;
determining if the recloser has failed to close within the predetermined closing time if the re-closer is not closed;
reissuing a close signal to said output means after a predetermined close retry time delay, if the recloser was determined to have failed to close within the predetermined close time and returning to the above step of redetermining if the recloser is closed;
locking out the recloser, if the recloser was determined to have failed to close for a reason uncon-nected with a mere elapse of the close time; and causing the close memory element to assume a reset state.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US615,563 | 1984-05-31 | ||
| US06/615,563 US4680706A (en) | 1984-05-31 | 1984-05-31 | Recloser control with independent memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1242022A true CA1242022A (en) | 1988-09-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000482569A Expired CA1242022A (en) | 1984-05-31 | 1985-05-28 | Recloser control with independent memory |
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| US (1) | US4680706A (en) |
| KR (1) | KR850008065A (en) |
| BR (1) | BR8502585A (en) |
| CA (1) | CA1242022A (en) |
| GB (1) | GB2162004B (en) |
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| US6753493B2 (en) * | 2001-06-01 | 2004-06-22 | Hubbell Incorporated | Electrical circuit interrupting device |
| US6901298B1 (en) * | 2002-09-30 | 2005-05-31 | Rockwell Automation Technologies, Inc. | Saving and restoring controller state and context in an open operating system |
| US7746054B2 (en) * | 2007-02-26 | 2010-06-29 | Elster Electricity, Llc | System and method for detecting the presence of an unsafe line condition in a disconnected power meter |
| US20080204953A1 (en) * | 2007-02-26 | 2008-08-28 | Elster Electricity Llc. | System and method for detecting the presence of an unsafe line condition in a disconnected power meter |
| US7772829B2 (en) * | 2008-04-21 | 2010-08-10 | Elster Electricity, Llc | Power meter and method for measuring power consumption |
| US8340931B2 (en) * | 2009-10-05 | 2012-12-25 | Mehta Tech, Inc. | Power grid with comparison of differences in remote phasor changes |
| US9761394B2 (en) | 2013-02-08 | 2017-09-12 | Hubbell Incorporated | Current interrupter for high voltage switches |
| AU2016277616B2 (en) * | 2015-12-23 | 2021-05-27 | Schneider Electric Industries Sas | A method for detecting a fault in a recloser |
| CN115668426A (en) | 2020-03-31 | 2023-01-31 | 豪倍公司 | System and method for operating an electrical switch |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1545169A (en) * | 1977-09-22 | 1979-05-02 | Burroughs Corp | Data processor system including data-save controller for protection against loss of volatile memory information during power failure |
| US4535409A (en) * | 1981-09-18 | 1985-08-13 | Mcgraw-Edison Company | Microprocessor based recloser control |
| US4419619A (en) * | 1981-09-18 | 1983-12-06 | Mcgraw-Edison Company | Microprocessor controlled voltage regulating transformer |
| US4523295A (en) * | 1982-09-07 | 1985-06-11 | Zenith Electronics Corporation | Power loss compensation for programmable memory control system |
| US4564922A (en) * | 1983-10-14 | 1986-01-14 | Pitney Bowes Inc. | Postage meter with power-failure resistant memory |
-
1984
- 1984-05-31 US US06/615,563 patent/US4680706A/en not_active Expired - Fee Related
-
1985
- 1985-05-28 CA CA000482569A patent/CA1242022A/en not_active Expired
- 1985-05-30 BR BR8502585A patent/BR8502585A/en unknown
- 1985-05-30 GB GB08513676A patent/GB2162004B/en not_active Expired
- 1985-05-30 KR KR1019850003744A patent/KR850008065A/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| GB2162004B (en) | 1988-03-02 |
| BR8502585A (en) | 1986-02-04 |
| KR850008065A (en) | 1985-12-11 |
| GB8513676D0 (en) | 1985-07-03 |
| GB2162004A (en) | 1986-01-22 |
| US4680706A (en) | 1987-07-14 |
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| Date | Code | Title | Description |
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| MKEX | Expiry |