CA1246147A

CA1246147A - Electronic circuit for measuring electrical energy

Info

Publication number: CA1246147A
Application number: CA000519229A
Authority: CA
Inventors: Raymond W. Mackenzie
Original assignee: Westinghouse Electric Corp
Current assignee: CBS Corp
Priority date: 1985-10-02
Filing date: 1986-09-26
Publication date: 1988-12-06
Also published as: AU6290186A; JPS6287872A; AU579489B2; ZA867084B; BR8604844A; ES2020186B3; KR870004311A; EP0228155B1; US4663587A; DE3676174D1; EP0228155A1

Abstract

21 50,874 ABSTRACT OF THE INVENTION
A shift register is utilized to provide a 90°
delay in a pulse width modulated current signal, to deter-mine volt-amperes reactive. The shift register is asso-ciated with a clock that provides a preselected frequency that, in combination with the number of stages in the shift register, delays the pulse width modulated current signal by an amount equivalent to one-quarter period of the current waveform in the metered circuit. After delaying the pulse width modulated signal by 90°, the shifted signal is multiplied by a voltage signal that represents the voltage in the metered circuit and the resulting product signal is input to a voltage-to-frequency converter.

Description

1 50,874 ELECTRONIC CIRCUIT FOR MEASURING
ELECTRICAL ENERGY
BACKGROUND AND SUMM~RY OF THE INVENTION
The present invention relates generally to an electronic circuit for measuring AC electrical energy and, more particularly, for measuring volt-amperes reactive S (VAR's).
It is known to those skilled in the art to provide electronic circuits for measuring AC ~lectricaL
energy. In one particular type of electronic circuit, a multiplier circuit is used to produce signals that are responsive to the product of the current and voltage of the metered circuit. A voltage-to-frequency converter can be used to provide an output signal that is responsive to the magnitude of this product.
There are various ways known to those skilled in the art for forming this signal that is representative of the product of current and voltage. U.S. Patent No.
4,242,634, which lssued on December 30, 1980 to Metcalf, discloses an electronic multiplying circuit that is intend-ed for use in an electronic watthour meter. This particu-lar circuit comprises a variable-transconductance multi-plier of the type comprising two emitter-coupled pairs of transistors with the collectors of one pair being cross-coupled with the collectors of the other pair. In order to permit the effective polarity of one of the input signals to the multiplier to be reversed from time to time for drift correction purposes, this input signal is applied to

2~6~
2 50,874 a semiconductor switching circuit which applies it alter-nately to the respective bases of a further emitter-coupled pair of transistors. The collectors of the transistors of this further pair are connected in series with the coupled emitters of respective ones of the emitter-coupled pairs in the variable-transconductance multiplier.
U.S. Patent No. 4,254,376, which issued on March

3, 1981 to Steinmuller, discloses an apparatus for measur-ing the electric power or energy in an AC network. This apparatus comprises a multiplying device that is operated according to the principle of pulse duration-pulse height modulation. Variables that are proportional to the load current and the load voltage are taken directly from the load current and the load voltage respectively.
U.S. Patent No. 4,315,~12, which issued on February 9, 1982 to Gamoh, discloses an electronic watthour meter comprlsiny a pulse width modulation circuit ~or subjecting a voltage signal, which is proportlonaI to the load voltage of a power supply line, to pulse width modula-tion to obtain a pulse width duty cycle signal. A multi-plication circuit comprises a plurality of analog switches that are selectively operated, with the aid of the pulse width duty cycle signal, so that positive and negative DC
voltages that are equal in absolute value are obtained from the product of a voltage signal which is proportional to the consumption current of the power supply line and the pulse width duty cycle signal that is representative of the voltage signal proportional to the load voltage. It further comprises a dual-slope type frequency conversion circuit for convertlng the positive and negative DC volt-ages into a frequency signal.
U.S. Patent No. 4,182,983, which issued on January 8, 1980 to Heinrich et al, discloses an electronic AC electric energy measuring circuit that converts a di/dt analog input signal into a pulse width modulated signal responsive to the amplitude of a current component of an alternating current energy quantity to be measured. The 3 50,874 pulse width modulated (PWM) si~nal is produced by a first modulator circuit including an integrator ci.rcuit deriving bot~ a modulating frequency signal and a current analog signal proportional to the current component. A multiply-ing circuit receives a voltage analog input signal andapplies it to a reference input of a second modulator signal. The modulating control of the second modulator circuit receives the pulse width modulated signal so that the multiplying circuit produces a ~ariable amplitude and pulse width modulated signal having an average value equal to an average power measurement. An analog to frequency converter including a second integrator circuit receives the output of the multiplying circuit to produce an output pulse representative of a quantized amount o electric energy.
U.S. Patent No. 4,463,311, which issued on ~uly 31, 1984 to Kobayashi, discloses an electronic electric energy meter that comprises a delay time setting cir~uit that is connected to one of a voltage transormer and a current transformer that are, in turn, connected to power lines for providing a necessary delay time and a delay circuit. One embodiment of this electronic meter utilizes a shift register to provide a preselected time delay to a pulse width modulated signal. A constant frequency clock is used to control the speed of data through the shift register and various time delays are obtained by outputting the pulse width modulated signal from different stages of the shift register. To increase the time delay, the pulse width modulated signal is caused to be output from later stayes of the shift register and, conversely, to decrease the time delay the pulse width modulated signal is caused to be output from earlier stages of the shift register. By properly selecting the chosen output stage of the shift register, the pulse width modulated current signal can be delayed by an output of time equivalent to 90 phase shift of the signal.

4~
4 50,874 U.S. Patent 4,591,810, which was issued May 27, 1986 to Mackenzie et al and assigned to the assignee of the present application, discloses a pulse width modulator for an electronic kilowatt-hour meter that includes an integrator having its inputs connected to a squarewave clock signal and a sine wave signal proportional to the time derivative of current (di/dt) on a metered circuit. It comprises a plurality of series-connected inverters that are connected to the output of the integr~tor to operate as a comparator which generates a pulse wi~th modulated signal having a duty cycle proportional to metered current.
- It provides a negative feedback path that includes a low pass filter ~hich is connected between the output of the last inverter and an input to the integrator to compensate lS for errors produced by the integrator and inverters.
U.S. Patent No 4,12~,821, wh~ch issued on November 7, 1978 to Pe-tr, discloses an analog-to-frequency converter for developing an output signal of frequency proportional to a measuring current or voltage by the charge quantity compensation method. This type o:E analog-to~frequency converter is suitable for use in an electronic meter for converting an analog quantity, such as a voltage signal representing the product of voltage and current in a metered circuit, to a series of pulses whose frequency is proportional to an input signal.
U.S. Patent ~,596,951, which was issued June 24, 19~6 to Heinrich et al and assigned to the assignee of the present application, discloses an electronic circuit for a solid state electrical energy meter that has a pair o~ mutual inductance current transformers, a pulse width modula~ion circuit, an analog switch and a voltage-to-frequency converter. The pulse width modulation circuit includes an întegrator that has a first operational amplifier with a feedback circuit providing a constant DC gain and a variable gain at the power ~requency.
The pulse width modulation circuit also 50,874 includes a second operational amplifier that is configured as a comparator and connected to the first operational amplifier so that the reference level of the comparator is proportional to the average DC output of the first opera-tional amplifier. It further comprises summing resistorsthat are connected to the input of t:he integrator and are of like value and formed in a common array.
In certain metering applicatlons, it is desirable to measure the volt-amperes reactive (VAR's) to more properly charge the consumer for the amount of electrical energy consumed during a particular billing period. The present invention relates specifically to an electronic circuit that is usable within an electronic electric energy measuring circuit for the purposes of measuring volt-amperes reactive.
The metering apparatus of the present inventioncomprises a current input means for providing a signal that i~ proportional to the time derivative of an alternating current (di/dt) in the metered clrcuit. This current input means can comprise an air core transformer. U.S. Patent No. 4,368,424, which issued on January ll, 1983 to Miller, discloses a transducer which is suitable or t~e purpose of providing a signal that is proportional to the time deriva-tive of an alternating current. An integrating pulse width modulator (PWM) utilizes this time derivative signal, in conjunction with a clock that provides a series of periodic clock pulses, to produce an output signal that is a pulse width modulated waveform whose duty cycle i.s representative of the current magnitude in the metered circuit.
This pulse width modulated signal can be multi-plied by a voltage signal that is representative of the magnitude o the voltage of the metered circuit. A
voltage-to-frequency converter can be used to provide signal pulses representative of the magnitude of the product signal.
In the present invention, a means is provided for delaying the pulse width modulated signal, which is repre-:~L2~
6 50,874 sentative of the current magnitude of the metered circuit,by a predetermined amount of time. In a preferred embodi-ment of the present invention, this delaying means compris-es a shift register that digltally shifts the pulse width

- 5 modulated current signal. In conjunction with the shift register, the present invention utilizes a clock that controls the rate by which the data in the shift register is shifted. This clock provides a series of pulses whose frequency is determined as a function of the power line frequency. The frequency of this clock and the number of stages in the shift register are interrelated and are preselected to cause the pulse width modulated signal to be shifted by a preselected amount which, in the preferred embodiment of the present invention, represents a 90 delay relative to the pulse width modulated signal that is representative o~ the current in the metered circuit.
The present invention also provides a volta~e input means whose output is a si~nal that is proportional to the voltage of the metered circuit. This voltage input means can be a potentiaL transformer whose turns ratio is suitable to reduce the metered voltage to a magnitude suitable for the other components of the electronic meter-ing circuit. The signal from the voltage input means is multiplied by the shifted pulse width modulated signal to provide a signal that is representative of the magnitude of volt-amperes reactive (VAR's). This VAR signal is input to a voltage-to-frequency converter which produces a series of pulses representative of its input signal. In a preferred embodiment of the present invention, this frequency signal is input to a counter that accumulates its pulses to obtain a count representative of VARH's.
BRIEF DESCRIPTION OF THE DRAWING
The present invention will be more fully under-stood from a reading of the de~cription of the preferred embodiment in conjunction with the drawing, in which:
Figure 1 is a schematic block diagram of the present invention;

7 50,~74 Figure 2 represents various exemplary waveforms that occur at selected points in the diagram of Figure l;
Figure 3 represents various other exemplary waveforms that o~cur at selected pOiIlts in the circuit of Figure l; and Figure 4 is a schematic diagram of the clock used in conjunction with the shift register of the present invention.
DESCRIPTIO~ OF THE PREFERRED EMBODIMENT
Figure 1 illustrates a schematic diagram of the present invention. A current input means 10, such as an air core transformer, is connected to a metered electric circuit 12 for purposes of providing a signal that is proportional t.o the time derivative (di/dt) of the AC
current in the metered circult 12. This signal is sent to an inte~rating pulse width modulator (PWM) 1~ which utiliz-es it to modulate a timing signal recelved from a clock 16.
It should be understood that, altho~gh the present invention most particularly relates to the portion of the circuit in Figure 1 that pertains to the measurement of volt-amperes reactive (VAR's), Figure 1 also illustrates the metering circuit for determining watts. The pulse width modulated signal, on line 18, is sent to a shift register 20. This shift register 20 is asso~iated with a clock 22 which provides a series of pulses whose frequency is coordinated with the fre~uency of the metered circuit 12. In a preferred embodiment of the present invention, the ~umber o stages in the shift register 20 is function-ally associated with the frequency signal provided by the clock 22 so that the passage of the pulse width modulated signal through the shift register 20 is delayed by a time period that is equivalent to 90~ Therefore, the digital representation of the pulse width modulated signal that is output from the shift register 20 to the analog multiplier Z4 is delayed, relative to the pulse width modulated signal output by the modulator 1~, by an amount equivalent to ~ 50,874 one-quarter of the period of the metered current in the circuit 12 (i.e. ~/2 radians~.
-In order to achieve this 90 delay, the preferred embodiment of the present invention utilizes a shift 5register 20 that has 22.5 stages and a clock 22 that provides a series of pulses with a frequency of 5,280 Hz when the circuit 12 exhibits of frequency of exactly 60 Hz.
This relationship is expressed in Equation 1.

fclock = (N - ~) x 4 x fcircuit ~1) 10In Equation 1, the frequency, fclock~ provided ~y the clock 22, is equal to the number of stages N of the shift register 20 minus ~2, multiplied by four times the q Y fcircuit in the metered cirCuit 12 The number "4" in Equation l results in a delay equivalent to one ~ourth of ~he ~ull period of the pulse width modulated signal. This is equivalent to a 90 shift, or delay, of the pulse width modulated signal that is output from the pulse width modulator. It should be understood that many different alternative numbers of stages N of the shift register 20 are possible within the scope of the present invention. The specific number of stages N are determina-tive of the required clock frequency fclock for any given cirCuit freqUency fcircuit-The delayed pulse width modulated signal is sent25 to an analog multiplier 24 where it is multiplied by a voltage signal received from a voltage input means 26 that can be a potential transformer. The turns ratio and other physical characteristics of the potential transformer 26 are functionally related to the metered circuit 12 and the particular components chosen to implement the circuit in Figure 1. For example, the turns ratio of a potential transormer used as the voltage input means 26 is chosen to reduce the voltage of the metered circuit 12 to a suitable magnitude for use with the analog multiplier 24.

9 50,874 The output of the analo~ multiplier 24 is a voltage signal that is representative of the product of the voltage of the metered circuit 12 and the phase shifted current received from the shift register 20. This product S signal is then input to a voltage-to-frequency converter 28 that provides a series of pulses whose frequency represents the product signal received from the analog multiplier 24.
This frequency signal is output to a KVARH counter 30 which accumulates the pulses for purposes of monitoring the volt-amperes reactive of the circuit 12.
A reset pulse 32 is provided to the voltage-to-frequency converter 28 in order to provide a fi~ed charge to reset the integrator. The input signal from the multi-plier is used to discharge,the integrating capacitor. When lS discharge is sensed by a level detector, another reset pulse is provided.
Although not a necessary element o the present invention, Figure 1 also illustrates the use of the pulse width modulated signal from the modulator 14 to provide a watt measurement. This use of the pulse width modulated signal is generally similar to the one described above and used for the volt-amperes reactive (VAR's) measurement, but does not utilize a delayed signal. The pulse width modu-lated signaL from the modulator 14 ~s sent to an analog multiplier 34 which multiplies it by a voltage signal received from the voltage input means 26. This multiplica-tion technique is similar to that described above in conjunction with the multiplier 24 and results in a signal that is representative of the product of the metered ' 30 current and metered voltage. This product signal is input to a voltage-to-frequency converter 36 that provides an output signal comprising a plurality of pulses wherein each pulse represents a predetermined quantum of energy consump-tion. This signal is connected to a ~WH counter 38 for purposes of accumulating the pulses from the voltage-to-frequency converter and measuring the energy consumption of the metered circuit 12.

50,87~
In order to more fully describe the present invention, waveforms at preselected portions of the circuit shown in Figure 1 are illustrated in Figures 2 and 3. The present invention will be described in conjunction with Figures 1, 2 and 3. As discussed above, the current input means 10 provides a signal that is proportional to the time derivative (di/dt) of the current in the metered circuit 12. This time derivative signal is integrated within the integrating pulse width modulator 14 to result in a gener-ally sinusoidal waveform as illustrated by curve A inFigure 2. This waveform A is representative of the current waveform of the metered circuit 12. Since waveform A
represents the integral of the time derivative signal received, on line 11, by the pulse width modulator 14, it should be understood that it is phase shifted relative to the time derivativa signal (di/dt).
The cloclt 16 of Figure 1 provides a series of pulses, illustrated by waveform B in Figure 2, of a prese-lected constant frequency. In a preferred embodiment of the present invention, this frequency is chosen to be 683 Hz to provide a signal that is asynchronous with the current signal A, which is nominally 60 Hz. The clock pulses B are integrated to form the triangular signal C
illustrated in Figure 2. Waveform A is used to modulate waveform C to form a pulse width modulated signal that is output, on line 18, from the pulse width modulator 14.
Waveform D in Figure 2 illustrates the combination of these two signals, A and C, and waveform E shows the resulting modulated signal that is output from the pulse width modulator 14. As should be apparent to one skilled in the art, the high and low signals in the pulse width modulated signal E relate to the magnitude of the current waveform A.
For example, as illustrated with waveform E in Figure 2, the width "a" o the high signal is related to the width "b" of the low signal in such a way that the fraction a/(a+b) represents a value that is proportional to the magnitude of the current at that portion of the waveform.

11 50,874 The pulse width modulated signal E i5 input to the shift register 20. As the pulse width modulated signal passes through the shift register 20, it experiences a delay that is equivalent to one-quarter cycle, or ~/2 radians, of the current waveform A. This results in the delayed waveform F
that is sent to the analog multiplier 24. As shown in Figure 2, by arrows 50, waveform F is identical to waveform E, but is shifted by 90 or one-fourth of the period of waveform A.
For purposes of more clearly describing the use of waveforms E and F, they are also shown in Figure 3 in conjunction with other related waveforms. In order to determine the kilowatt-hours used by the metered circuit 12, waveform E is multiplied by the voltage signal G
received from the voltage input means 26. This multiplica-tion results in the product signal H that represents the product of the voltage (waveform G) and pulse wiclth modu-lated signal of the current (wave~orm E). Signal H is input to the voltage-to-frequency converter 36 and a resulting series of pulses are input, on line 37, to the kilowatt-hour counter 38.
The shifted pulse width modulated signal (wave-form F) is also illustrated in Figure 3. It is used by the present invention to be multiplied by the voltage waveform G by the analog multiplier 24. This results in a product signal (waveform I) that represents the product of the voltage (waveform G) and the delayed pulse width modulated current signal (waveform F). This product signal is sent to the voltage-to-frequency converter 28 and a resulting series of pulses is output to the KVARH counter 30 for purposes of accumulating a pulse count that is representa-- tive of the volt-amperes reactive hours (VARH's) of the metered circuit 12.
As described above in conjunction with Figure 1, a clock 22 is used in conjunction with the shift register to provide a precise 90 delay in the pulse width modulated signal received from the modulator 14. Since the ~Z~6~
12 50~874 clock 22 and the shift register 20 are used to precisely delay the pulse width modulated signal ~y an amount that is equivalent to one-quarter cycle o~ the current in the metered circuit 12, the clock 22 must be functionally associated with ~he metered circuit 12 in order to compen-sate for possible changes or variations in the power frequency within the metered circuit 12. Under normal ; conditions, this power fre~uency is 60 Hz, but could vary slightly from this nominal expected frequency. Nominal power line frequencies can be expected to vary between 58 Hz and 62 Hz. According to equation 1, if a shift register with 22.5 stages is used the resulting clock frequency will therefore vary between 5,104 Hz and 5,456 Hz. When a shift register with 22.5 stages is used, as in the preferred embodiment o~ the present invention, these shift regis-ter requencies will remain asynchronous wi-th both -the power l~ne frequency and the pulse width modulated current sigllal frequency. Figure 4 illustrates the components utilized to provide the clock 22.
By using a clock 22 that is capable of providing a variable frequency as a function of the power line frequency, the digital signal representing the pulse width modulating current signal will be shifted through the shift register 20 at different speeds depending on the power line frequency. The present invention uses a shift register with a predetermined number o~ stages. The chosen stages used or inputting and outputting the pulse width modulated current signal to and from the shift register 20 remain constant. Alternative techniques, such as that discloses in U.S. Patent No. 4,463,311 ! utilize a constant cloc~
frequency in conjunction with a shift register in which dîfferent stages of the shift register are selected as a means for providing the required time delay. In that type of system, di~ferent time delays are chosen by selecting different stages of the shift register as the output stage.
When different output stages are selected, the effective time delay caused by the shift register is changed as a 13 50,874 step function and the magnitude of the incremental time delay change is determined by the number of stages in the shift register and the frequency of the clock pulse sued to drive the shift register. The advantage of a meter made in accordance with the present invention is that it utilizes a shift register with a fixed number of stages in conjunction with a variable clock pulse frequency that can be changed continuously within a wide range of frequencies. This characteristic permits the effective time delay of the shift register to be accurately chosen with a high degree of resolution as a function of the power line frequency.
The clock 22 comprises a quad 2-input NAND
Schmitt trigger 60. The Schmitt trigger is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. This type of device is prlmarily used where low power dissipation and high noise immunity is desired. This type of component i5 available in commercial quantikies as type MClgO93~ from the Motorola Corporation. The purpose of the Schmitt trigger is to improve the shape of the signal at VCOntrOl w p a voltage reference. A 120 Hz parabolic waveform is derived from the power supply. This waveform is filtered by an RC network to remove the DC component and higher frequency harmonics, such as noise spikes that may be present on the power line. This filtered waveform is then applied to the Schmitt tr:igger, which provides a 120 Hz squarewave output. The source follower 68 and self-biased circuit 70, as well as the inhibit input, are not directly related to the present invention but are included in Figure 4 for the purposes of completely illustrating the compon-ents of the phase-locked loop 62. The clock 22 incorp-orates a phase-locked loop 62 which is illustrated schemat-ically in Figure 4. The phase-locked loop 62 contains two phase comparators (one phase comparator 64 is illustrated in Figure 4), a voltage-controlled oscillator (VCO) 66, a source follower 6~ and a zener diode ~not illustrated in Figure 4). The self-bias circuit 70 adjusts small voltage ~2~
14 50,874 signals in the linear region of the amplifier. The phase comparator 64, with leading-edge sensing logic, provides a digital error signal PC20Ut. The linear VCO 66 produces an output signal VCOOut whose frequency is determined by the voltage of input VCOin and the capacitor and resistors connected to pins Rl, R2, ClA and ClB. The inhibit input INH, when high, disables the VCO and source follower to minimize standby power consumption. The phase-locked loop 62 is available ln commercial quantities as type ~C14046B
from the Motorola Corporation.
T'ne VCOOut signal is used by the present inven-tion to provide a shift register clock pulse and is al~o used as an input signal to a 12-bit binary counter 80.
PC20Ut is connected to VCOin by means of a suitable filter network comprising resistors RSl and RS2 and capacitors C1 and C2, as illustrated in Figure ~. The binary counter 80 is illustrated schematically in Figure 4 and is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. It is designed with an input wave shaping circuit and twelve stages of ripple-carry binary counter. The device advances the count on the negative-going edge of the clock pulse and can be used in time delay circuits, counter controls and frequency driving circuits. The twelve-bit binary counter is available in commercial quantities as type MC14040B from the Motorola Corporation. Three of the outputs from the 12-bit binary counter 80 are connected as inputs to a 4-input AND gate 82. These outputs are illustrated in Fi~ure 4 as Q3, Q4 and Q6. The output of the AND gate 82 is connected to the reset input of the 12 bit binary counter, by line 84, and the clock input of the binary counter 80 is connected to the VCOOut output of the phase-locked loop 62, by line 86.
The AND gate 82 is available in commercial quantities as type MC14082B from the Motorola Corporation and is con-structed with P-channel and N-channel enhancement mode devices in a single monolithic structure. It is made with complem~ntary MOS technology and its primary use is where 50,874 low power dissipation and high noise immunity are desired.
The clock 22 illustrated in Figure 4 is used to provide a reliable signal with a variable frequency that is related to the frequency of the circuit 12 in such as way so as to cooperate with the number of stages in the shift register 20 to provide a constant 90 delay in the pulse width modula~ed signal received from the modulator 14.
Since real~ or true, power Pr is measured in watts and defined by equation Pr = VI cos ~ (2) and imaginary, or reactive, power Pq is measured in volt-amperes reactive (VAR's) and defined by equation PQ = VI sin ~ (3) where V is the voltage in the metered circuit 12, I i5 the current in the metered circuit 12 and the term cos ~ is dimensionless and known as the power factor, the present invention provides a means for measuring volt-amperes reactive by shifting the pulse width modulated current signal by 90 and multiplying it by the voltage in the metered circuit.
Table I illustrates the component types used to manufacture a prototype of the present invention.

l~ 50,~74 Table I
Reference Numeral Component Type Type CD4006B
24 Type MC14016B
5 34 Type MC14016B
Type MC14093B
62 Type MC14046B
Type MC14040B
82 Type MC14082B

Although a prototype circuit of the present invention has been manufactured using the components described above, it should be understood that the present invention can also be manu~`actured by using one or more semi-custom, or custom, integrated circuit chips to perform the same functions as those described above in conjunction with Figure 1. Similarly, semi-custom or custom integrated circuit chips can be used to provide the clock 22 that is illustrated in Figure 4. Therefore, it should be under-stood that the specification of particular component types as shown in Table I does not limit the scope of the present invention, but merely designate one particular embodiment of the metering circuit that can be produced by using individual circuit components that are commerclally avail-able.
The present invention provides an electronic circuit that can be used to measure volt-amperes reactive of a metered circuit. Furthermore, the present invention can easily be associated with a electronic circuit for measuring real, or true, power. By using a single pulse width modulator, as illustrated in Figure 1, a pulse width modulated current signal can be multiplied by a voltage signal to determine watts and, as a shifted waveform, can

6~
17 50,874 be used to be multiplied by the voltage signal to determine VAR's. Although the present invention has been described in detail relating to a single phase meter, it should be apparent, that by using a multipllcity of pulse width modulators, shift registers, and analog multipliers, a polyphase meter can ba constructed wlthin the scope of the present invention.

Claims

18 50,874 What I claim is:

1. A metering apparatus, comprising:
current input means for providing a signal that is proportional to the time derivative of an alternating current in a circuit;
first clock means for providing a first series of clock pulses, said first series of clock pulses having a generally constant frequency;
integrating means for modulating said series of clock pulses with said signal that is proportional to said time derivative of said current, said integrating means being connected to said current input means and said first clock means, the output of said integrating means being a first pulse width modulated signal;
means for delaying said first pulse modulated signal by a predetermined amount of time, the output of said delaying means being a second pulse width modulated signal;
second clock means for providing a second series of clock pulses, said second clock means having an output connected to said delaying means, said second series of clock pulses having a variable frequency, said second clock means being configured to vary said variable frequency according to a preselected relationship with the frequency of said alternating current in said circuit;
voltage input means for providing a signal that is proportional to the voltage of said circuit;

19 50,874 first multiplier means for providing a signal that is proportional to the product of said second pulse width modulated signal and said signal that is proportional to the voltage of said circuit, said first multiplier means being connected to the output of said delaying means and the output of said voltage input means; and wherein the output of said first multiplier means is proportional to the volt-amperes reactive of said circuit.

2. The apparatus of claim 1, wherein:
said delaying means comprises a shift register.

3. The apparatus of claim 1, wherein:
said predetermined amount of time is equivalent to one-fourth of the period of one cycle of said alternat-ing current.

4. The apparatus of claim 1, wherein:
said second clock means comprises a phase locked loop.

5. The apparatus of claim 1, further comprising:
a first voltage-to-frequency converter connected to said first multiplier means, said first voltage-to-frequency converter providing an output signal comprising a first plurality of pulses, each of said first plurality of pulses from said first voltage-to-frequency converter representing a predetermined quantity of volt-amperes reactance.

6. The apparatus of claim 5, further comprising:
a first counter connected to said first voltage-to-frequency converter, said first counter being configured to accumulate a count of said first plurality of pulses from said first voltage-to-frequency converter.

7. The apparatus of claim 1, further comprising:
second multiplier means for providing a signal that is proportional to the product of said first pulse width modulated signal and said signal that is proportional to the voltage of said circuit, said second multiplier means being connected to the output of said integrating means and the output of said voltage input means; and 50,874 wherein the output of said second multiplier means is proportional to watts of said circuit.

8. The apparatus of claim 7, further comprising:
a second voltage-to-frequency converter connected to said second multiplier means, said second voltage-to-frequency converter providing an output signal comprising a second plurality of pulses, each of said second plurality of pulses from said second voltage-to-frequency converter representing a predetermined quantity of watts.

9. The apparatus of claim 8, further comprising:
a second counter connected to said second voltage-to-frequency converter, said counter being config-ured to accumulate a count of said second plurality of pulses from said second voltage-to-frequency converter.