CA1264832A - Fault detecting intrusion detection device - Google Patents
Fault detecting intrusion detection deviceInfo
- Publication number
- CA1264832A CA1264832A CA000542567A CA542567A CA1264832A CA 1264832 A CA1264832 A CA 1264832A CA 000542567 A CA000542567 A CA 000542567A CA 542567 A CA542567 A CA 542567A CA 1264832 A CA1264832 A CA 1264832A
- Authority
- CA
- Canada
- Prior art keywords
- sensor
- subsystem
- intrusion detection
- counter
- output signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 title claims abstract description 47
- 230000006872 improvement Effects 0.000 claims abstract description 4
- 230000009977 dual effect Effects 0.000 claims description 13
- 230000004044 response Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 241001163743 Perlodes Species 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G08—SIGNALLING
- G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
- G08B29/00—Checking or monitoring of signalling or alarm systems; Prevention or correction of operating errors, e.g. preventing unauthorised operation
- G08B29/18—Prevention or correction of operating errors
- G08B29/183—Single detectors using dual technologies
-
- G—PHYSICS
- G08—SIGNALLING
- G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
- G08B13/00—Burglar, theft or intruder alarms
- G08B13/18—Actuation by interference with heat, light, or radiation of shorter wavelength; Actuation by intruding sources of heat, light, or radiation of shorter wavelength
- G08B13/189—Actuation by interference with heat, light, or radiation of shorter wavelength; Actuation by intruding sources of heat, light, or radiation of shorter wavelength using passive radiation detection systems
- G08B13/19—Actuation by interference with heat, light, or radiation of shorter wavelength; Actuation by intruding sources of heat, light, or radiation of shorter wavelength using passive radiation detection systems using infrared-radiation detection systems
-
- G—PHYSICS
- G08—SIGNALLING
- G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
- G08B13/00—Burglar, theft or intruder alarms
- G08B13/22—Electrical actuation
- G08B13/24—Electrical actuation by interference with electromagnetic field distribution
- G08B13/2491—Intrusion detection systems, i.e. where the body of an intruder causes the interference with the electromagnetic field
- G08B13/2494—Intrusion detection systems, i.e. where the body of an intruder causes the interference with the electromagnetic field by interference with electro-magnetic field distribution combined with other electrical sensor means, e.g. microwave detectors combined with other sensor means
Abstract
Abstract In an improved intrusion detection device system of the dual-sensor type, wherein one sensor is a PIR
sensor and the other is a microwave sensor, the improvement comprises counting the detection of intrusion separately by the microwave sensor and by the passive infrared sensor. Thereafter, the counts by the two separate detectors are compared and an indication is given if the number exceeds a certain user selectable threshold, to indicate fault in one of the two sensor subsystems.
sensor and the other is a microwave sensor, the improvement comprises counting the detection of intrusion separately by the microwave sensor and by the passive infrared sensor. Thereafter, the counts by the two separate detectors are compared and an indication is given if the number exceeds a certain user selectable threshold, to indicate fault in one of the two sensor subsystems.
Description
$3~
Description Fault-Detectin~ Intrusion Detection Device Technical Description The present invention relates to an improved intrusion detection device and, more particularly, to an improved intrusion detection device of the type having two sensors and the ability to detect fault within one of the two sensors.
Backaround Of The Invention Combination intrusion detection devices are well-known in the art. A typical combination is the use of a passive infrared intrusion detection device along with a microwave intrusion detection device. The output of the two sensors are supplied to an AND gate.
If both of the sensors detect the presence of an intruder, then an alarm is triggered.
The combination of the electrical outputs of two independent sensing subsystems with each subsystem responding to different stimuli in a complementary manner significantly reduces the possibility of false alarms. This reduction of false alarms more than offsets the higher costs in the manufacturing of these combination intrusion detection devices.
One drawback of a combination dual sensing device is that if one of the sensors or subsystems fails to operate properly, the integrity of the entire system is lost. This is because once a subsystem or the sensor thereof has failed (assuming that it fails in the open mode; iOe., the failed sensor/subsystem never detects the presence of an intruder), and since the entire system is dependent upon the presence of a signal on both of the sensor subsystems, the failure of one sensor subsystem fails the entire system.
~ b There are many possible causes of failure of a sensor or its subsystem. One possible failure of a sensor or its subsystem is the failure in the electrical circuitry. A second possible source of sensor failure is if the sensor is not installed properly. In order for the entire int:rusion detection system to function properly, both sensor subsystems must be directed at the same volume or space location.
Both sensors must detect the presence of an intruder in the same or proximate location. Thus, there must be ov~rlapping of the area or space of detection of the two sensors. If the two sensor subsystems are not aligned properly and are not directed towards the same space or volume location, the non-overlappin~ field will result in the entire system never producing alarm.
~his is hecause an intruder will always be detected by only a single sensor subsystem. Another source of failure is due to tampering. If a would-be intruder has masked or disabled one sensor subsystem, there again the disablement of that sensor subsystem would have disabled the entire system.
Thus, it is highly desirable in an intrusion detection system of the dual sensor subsystem type to be able to detect any internal electrical malfunction of any one of the sensor subsystems, or to detect any physical tampering of any one of the sensor subsystems, or to detect any masking of the normal fields of use of any of the sensor subsystems or to detect the improper installation which results in substantially different fields of view of each sensor subsystem. Any of these conditions may be termed collectively as a "fault condition".
3~
Summar~ Of The Invention In the present invention, an improvement to an intru6ion detection apparatus is disclosed. The intrusion detection apparatus is of the type having dual sensors with each of the two sensors providing a signal upon the detection of an intrucler. Logic means is further provided to process the two signals from the dual sensors to trigger an alarm in the event the intruder is detected by both of the sensors. The improvement comprises a first storage means for storing the number of signals recorded by one o~ the dual sensors. A second storage means stores the number of signals detected by the second sensor. A logic control -' means receives the output of the first and second storage means and compares the numbers stored therein and outputs a ~ault signal in response to this comparison.
Description Of The Drawin~
Fig. 1 is a schematic block diagram of an improved ~0 intrusion detection system of the present invention.
Fig. 2 is a schematic block diagram of the ~ault detection subsystem of the intrusion detection device of the present in~ention.
Fig. 3 is a detail circuit diagram of the fault detection subsystem of the present invention.
Detailed Descri~tion Of The Drawinqs Referring to Fig. 1, there is shown a block diagram of an improved intrusion detection system 10 of the present invention. The intrusion detection system 10 of the present invention comprises a first sensor 12 subassembly and a second sensor 14 subassembly. The first sensor 12 subassembly is typically a passive infrared radiation detection subsystem. The second 3~2 sensor 14 subassembly is typically a microwave energy detection subsystem. Each of the first sensor 12 subsystem and second sensor 14 subsystem is directed to detect intruders within the same space or volume of space 16. Each of the first sensor 12 subsystem and second sensor ~4 subsystem produces a first output signal 18 and a second output signal 20, respectively, upon the detection of an intruder within the space or volume 16 to which the subsystem is directed. Such a system 10, using the combination of a photoelectric sensor and microwave detector is fully described in U.S. Patent No. 3,725,888.
The first and second output signals 18 and 20, respectively, are supplied to a logic controller 22.
The logic control]er 22 produces an output signal 24 which triggers an alarm 26 in the event an intruder is detected by both the first sensor 12 subsystem and the second sensor 14 subsystem, within a specified period of time.
In the improved intrusion detection device 10 of the present invention, the device 10 also comprises a fault detection subsystam 30. The fault detection subsystem 30 also receives the first and second output signals 18 and 20, respectively.
Referring to Fig. 2, there is shown in block diagram the fault detection subsystem 30. The fault detection subsystem 30 comprises an input signal conditioner 32 to which the first and second output signals 18 and 20, respectively, are supplied. The input signal conditioner 32 processes the input signals, by for example, holding them for a predetermined period of time.
From the input signal conditioner 32, the first and second output signals 18 and 20 are supplied to a rapid event suppressor 340 The rapid event suppressor 34 detects the presence of a rapid series of pulses.
If this occurs, the fault detection subsystem 30 will stop counting the output signal 18 or 20 for a preset perlod of time. From the rapid event suppressor 34, the first and second output signals 18 and 20~
respectively, are supplied to a first and a second counters 36 and 38, respectively. The output of the first and the second event counters 36 and 38 are supplied to a control logic 40. The control logic 40 also receives a user selectable ratio number along input lines 42 which pass through a ratio select logic 44. The output of the control logic 40 is a signal which can indicate fault in one of the two sensor subsystems. That fault signal 46 is supplied to a NOR
gate 48. Other inputs to the NOR Gate 48 are a tamper signal 50 and a microwave supervisory signal 52.
Further, the NOR gate 48 may be disabled by a signal sent along the disabled line 54.
The output of the NOR gate 48 is a signal which is supplied to a relay drive 56 and to an LED drive 58 which informs the user of the fault that is detected.
An oscillator and clock generator 60 supplies the necessary clocking signals to the rapid events suppressor 34 and to the LED drive 58.
Referring to Fig. 3, there is shown in greater detail the various block components of the fault detection subsystem 30 described in Fig. 2. The first sensor output signal 18 is supplied to a NAND gate 62, and to an OR gate 64 and an invertor 66. The output of the NAND gate 62 is supplied to a second AND gate 68/
which i5 then supplied to the ~irst counter 36, which is an eight (8) bit counter. NAND gate 62 is also controlled by the rapid event suppressor 34. In the event a rapid series of pulses is detected by the suppressor 34, NAND gate 62 is turned off thereby ~LZ6~3~
pre~enting first sensor output signal 18 from reaching the first counter 36. Gates 64 and 68 are used for testing purposes.
The second output signal 20 from the microwave detection subsystem 14 is supplied to a one-shot 68 (which comprises a counter 68a and an OR gate 68b), which keeps the signal low for approximately 3.8 seconds after the last microwa~e pulse. ~he output of the one-shot 68 is then passed to a NOR gate 70, to an AND gate 72 and to the second counter 38, which is also an eight bit counter. The function of the NOR gate 70 is similar to the NAND gate 62. AND gates 72 and 73 are also used for testing purposes.
The rapid event suppressor 34 comprises, in part, a long counter 100 and a dual counter 101. The long counter 100 receives timing pulses from the oscillator and clock generator 60. The dual counter 101 receives the first and second output signals 18 and 20 (after passing through gates 62 and 70, respectively).
The long counter 100 resets the dual counter 101 every one (l) minute. In the event the dual counker 101 receives greater than or equal to eight (8) signals (first or second output signals 18 or 20) within a one minute interval, the dual counter 101 (1) causes tha dual counter 101 to be reset; (2) turns off gates 62 and 70 for eight (8) minutes; and ~3) after eight (8) minutes, turns on gates 62 and 70 and resumes normal operation.
The four user selectable ratio signals 42 are supplied to the ratio select lo~ic 44 which comprises a plurality of AND gates, an OR gate and multiplexers 86 and 90l all as shown and connected in Fig. 3. Two of the fGUr user selectable ratio signals 42 are used to disable the appropriate least significant bits tLSB~
from the first and second counters 36 and 38 to obtain ~IL2~ 33~
the conditions of (1) greater than 0; (2) greater than 1; ~3) greater than 3; or (~) greater than 7 as inputs to P~R AND gate 8G and MW AND gate 82O The output of the PIR AND gate 80 and MW AND gate 82 is a determination of the number of signals (18 or 20, respectively) counted by counters 36 and 38 which meets or exceeds the number set by two of the four user selectable input lines 42.
The other two user selectable lines 42 are supplied to multiplexers 86 and so. The multiplexers 86 and 90 select one o~ the four MSB from counters 36 and 38 and supplies that as input to PIR AND gate 85 and MW AND gate 89, and also to gates 88 and 84, respectively. When either the counter 36 or 38 reaches a number of the MSB that is selected by the two user selectable lines 42, that causes a compare event at 92 and 94. In that event, the least significant bits of the counter 36 or 3~ that did not cause the compare e~ent is analyzed to determine if that number meets or exceeds the number set by the other two user selectable lines.
In the event the number of the counts of the least significant bits of the counter that did not cause the compare event, meets or exceeds the user selected thresholdl then a pulse appears at 9~. This indicates "no fault". The no fault pulse 94 resets the first and second counters 36 and 38. However, if the converse occurred, a pulse would appear at 92. This indicates a "fault", i.e., too many signals of the sensor of one type are counted as compared to the signals of the sensor of the other type. The fault pulse 92 is supplied to the NOR gate 48, which then triggers a flip flop 46. The ~ output of the flip flop 96 triggers the relay drive 56 and the LED drive 58.
In the operation of the fault detection subsystem 30, the user first selects the number of events to cause the compara and the minimum for the compare.
During the unarmed stage, the first and second sensors 12 and 14 would be counting the intruders in the space 16. These counts would be collected by the fault detection subsystem 30 and stored in the first and second counters 36 and 3~3, respecti~ely. When the first or second counter 36 or 38 reaches the number set by the user for a compare event, the number of counts stored in the counter that did not cause the compare e~ent is compared to the minimum set by the user. If that number is greater than tha minimum, then "no fault". Otherwise there is a fault in one of the sensor subsystems.
It should be emphasized that the operation of the fault detection subsystem 30 in no way impedes the arming or disarming of the intrusion detection device 10. During the time that the fault detection subsystem 30 is in operation, the intrusion detection device 10 can still be armed.
There are many advantages to the improved intrusion detection system 10 of the present invention.
First and foremost, with the use of a dual sensor intrusion detection system, false alarm is minimized.
Furthermore, with the fault detection 30, it is seen that the failure of one of the sensor subsystems can be easily detected, and an indication be sent to the user of the failure of the intrusion detection device 10.
Thus, the intrusion detection device lO has all of the advantages of both fail-safe, as well as reliability.
Description Fault-Detectin~ Intrusion Detection Device Technical Description The present invention relates to an improved intrusion detection device and, more particularly, to an improved intrusion detection device of the type having two sensors and the ability to detect fault within one of the two sensors.
Backaround Of The Invention Combination intrusion detection devices are well-known in the art. A typical combination is the use of a passive infrared intrusion detection device along with a microwave intrusion detection device. The output of the two sensors are supplied to an AND gate.
If both of the sensors detect the presence of an intruder, then an alarm is triggered.
The combination of the electrical outputs of two independent sensing subsystems with each subsystem responding to different stimuli in a complementary manner significantly reduces the possibility of false alarms. This reduction of false alarms more than offsets the higher costs in the manufacturing of these combination intrusion detection devices.
One drawback of a combination dual sensing device is that if one of the sensors or subsystems fails to operate properly, the integrity of the entire system is lost. This is because once a subsystem or the sensor thereof has failed (assuming that it fails in the open mode; iOe., the failed sensor/subsystem never detects the presence of an intruder), and since the entire system is dependent upon the presence of a signal on both of the sensor subsystems, the failure of one sensor subsystem fails the entire system.
~ b There are many possible causes of failure of a sensor or its subsystem. One possible failure of a sensor or its subsystem is the failure in the electrical circuitry. A second possible source of sensor failure is if the sensor is not installed properly. In order for the entire int:rusion detection system to function properly, both sensor subsystems must be directed at the same volume or space location.
Both sensors must detect the presence of an intruder in the same or proximate location. Thus, there must be ov~rlapping of the area or space of detection of the two sensors. If the two sensor subsystems are not aligned properly and are not directed towards the same space or volume location, the non-overlappin~ field will result in the entire system never producing alarm.
~his is hecause an intruder will always be detected by only a single sensor subsystem. Another source of failure is due to tampering. If a would-be intruder has masked or disabled one sensor subsystem, there again the disablement of that sensor subsystem would have disabled the entire system.
Thus, it is highly desirable in an intrusion detection system of the dual sensor subsystem type to be able to detect any internal electrical malfunction of any one of the sensor subsystems, or to detect any physical tampering of any one of the sensor subsystems, or to detect any masking of the normal fields of use of any of the sensor subsystems or to detect the improper installation which results in substantially different fields of view of each sensor subsystem. Any of these conditions may be termed collectively as a "fault condition".
3~
Summar~ Of The Invention In the present invention, an improvement to an intru6ion detection apparatus is disclosed. The intrusion detection apparatus is of the type having dual sensors with each of the two sensors providing a signal upon the detection of an intrucler. Logic means is further provided to process the two signals from the dual sensors to trigger an alarm in the event the intruder is detected by both of the sensors. The improvement comprises a first storage means for storing the number of signals recorded by one o~ the dual sensors. A second storage means stores the number of signals detected by the second sensor. A logic control -' means receives the output of the first and second storage means and compares the numbers stored therein and outputs a ~ault signal in response to this comparison.
Description Of The Drawin~
Fig. 1 is a schematic block diagram of an improved ~0 intrusion detection system of the present invention.
Fig. 2 is a schematic block diagram of the ~ault detection subsystem of the intrusion detection device of the present in~ention.
Fig. 3 is a detail circuit diagram of the fault detection subsystem of the present invention.
Detailed Descri~tion Of The Drawinqs Referring to Fig. 1, there is shown a block diagram of an improved intrusion detection system 10 of the present invention. The intrusion detection system 10 of the present invention comprises a first sensor 12 subassembly and a second sensor 14 subassembly. The first sensor 12 subassembly is typically a passive infrared radiation detection subsystem. The second 3~2 sensor 14 subassembly is typically a microwave energy detection subsystem. Each of the first sensor 12 subsystem and second sensor 14 subsystem is directed to detect intruders within the same space or volume of space 16. Each of the first sensor 12 subsystem and second sensor ~4 subsystem produces a first output signal 18 and a second output signal 20, respectively, upon the detection of an intruder within the space or volume 16 to which the subsystem is directed. Such a system 10, using the combination of a photoelectric sensor and microwave detector is fully described in U.S. Patent No. 3,725,888.
The first and second output signals 18 and 20, respectively, are supplied to a logic controller 22.
The logic control]er 22 produces an output signal 24 which triggers an alarm 26 in the event an intruder is detected by both the first sensor 12 subsystem and the second sensor 14 subsystem, within a specified period of time.
In the improved intrusion detection device 10 of the present invention, the device 10 also comprises a fault detection subsystam 30. The fault detection subsystem 30 also receives the first and second output signals 18 and 20, respectively.
Referring to Fig. 2, there is shown in block diagram the fault detection subsystem 30. The fault detection subsystem 30 comprises an input signal conditioner 32 to which the first and second output signals 18 and 20, respectively, are supplied. The input signal conditioner 32 processes the input signals, by for example, holding them for a predetermined period of time.
From the input signal conditioner 32, the first and second output signals 18 and 20 are supplied to a rapid event suppressor 340 The rapid event suppressor 34 detects the presence of a rapid series of pulses.
If this occurs, the fault detection subsystem 30 will stop counting the output signal 18 or 20 for a preset perlod of time. From the rapid event suppressor 34, the first and second output signals 18 and 20~
respectively, are supplied to a first and a second counters 36 and 38, respectively. The output of the first and the second event counters 36 and 38 are supplied to a control logic 40. The control logic 40 also receives a user selectable ratio number along input lines 42 which pass through a ratio select logic 44. The output of the control logic 40 is a signal which can indicate fault in one of the two sensor subsystems. That fault signal 46 is supplied to a NOR
gate 48. Other inputs to the NOR Gate 48 are a tamper signal 50 and a microwave supervisory signal 52.
Further, the NOR gate 48 may be disabled by a signal sent along the disabled line 54.
The output of the NOR gate 48 is a signal which is supplied to a relay drive 56 and to an LED drive 58 which informs the user of the fault that is detected.
An oscillator and clock generator 60 supplies the necessary clocking signals to the rapid events suppressor 34 and to the LED drive 58.
Referring to Fig. 3, there is shown in greater detail the various block components of the fault detection subsystem 30 described in Fig. 2. The first sensor output signal 18 is supplied to a NAND gate 62, and to an OR gate 64 and an invertor 66. The output of the NAND gate 62 is supplied to a second AND gate 68/
which i5 then supplied to the ~irst counter 36, which is an eight (8) bit counter. NAND gate 62 is also controlled by the rapid event suppressor 34. In the event a rapid series of pulses is detected by the suppressor 34, NAND gate 62 is turned off thereby ~LZ6~3~
pre~enting first sensor output signal 18 from reaching the first counter 36. Gates 64 and 68 are used for testing purposes.
The second output signal 20 from the microwave detection subsystem 14 is supplied to a one-shot 68 (which comprises a counter 68a and an OR gate 68b), which keeps the signal low for approximately 3.8 seconds after the last microwa~e pulse. ~he output of the one-shot 68 is then passed to a NOR gate 70, to an AND gate 72 and to the second counter 38, which is also an eight bit counter. The function of the NOR gate 70 is similar to the NAND gate 62. AND gates 72 and 73 are also used for testing purposes.
The rapid event suppressor 34 comprises, in part, a long counter 100 and a dual counter 101. The long counter 100 receives timing pulses from the oscillator and clock generator 60. The dual counter 101 receives the first and second output signals 18 and 20 (after passing through gates 62 and 70, respectively).
The long counter 100 resets the dual counter 101 every one (l) minute. In the event the dual counker 101 receives greater than or equal to eight (8) signals (first or second output signals 18 or 20) within a one minute interval, the dual counter 101 (1) causes tha dual counter 101 to be reset; (2) turns off gates 62 and 70 for eight (8) minutes; and ~3) after eight (8) minutes, turns on gates 62 and 70 and resumes normal operation.
The four user selectable ratio signals 42 are supplied to the ratio select lo~ic 44 which comprises a plurality of AND gates, an OR gate and multiplexers 86 and 90l all as shown and connected in Fig. 3. Two of the fGUr user selectable ratio signals 42 are used to disable the appropriate least significant bits tLSB~
from the first and second counters 36 and 38 to obtain ~IL2~ 33~
the conditions of (1) greater than 0; (2) greater than 1; ~3) greater than 3; or (~) greater than 7 as inputs to P~R AND gate 8G and MW AND gate 82O The output of the PIR AND gate 80 and MW AND gate 82 is a determination of the number of signals (18 or 20, respectively) counted by counters 36 and 38 which meets or exceeds the number set by two of the four user selectable input lines 42.
The other two user selectable lines 42 are supplied to multiplexers 86 and so. The multiplexers 86 and 90 select one o~ the four MSB from counters 36 and 38 and supplies that as input to PIR AND gate 85 and MW AND gate 89, and also to gates 88 and 84, respectively. When either the counter 36 or 38 reaches a number of the MSB that is selected by the two user selectable lines 42, that causes a compare event at 92 and 94. In that event, the least significant bits of the counter 36 or 3~ that did not cause the compare e~ent is analyzed to determine if that number meets or exceeds the number set by the other two user selectable lines.
In the event the number of the counts of the least significant bits of the counter that did not cause the compare event, meets or exceeds the user selected thresholdl then a pulse appears at 9~. This indicates "no fault". The no fault pulse 94 resets the first and second counters 36 and 38. However, if the converse occurred, a pulse would appear at 92. This indicates a "fault", i.e., too many signals of the sensor of one type are counted as compared to the signals of the sensor of the other type. The fault pulse 92 is supplied to the NOR gate 48, which then triggers a flip flop 46. The ~ output of the flip flop 96 triggers the relay drive 56 and the LED drive 58.
In the operation of the fault detection subsystem 30, the user first selects the number of events to cause the compara and the minimum for the compare.
During the unarmed stage, the first and second sensors 12 and 14 would be counting the intruders in the space 16. These counts would be collected by the fault detection subsystem 30 and stored in the first and second counters 36 and 3~3, respecti~ely. When the first or second counter 36 or 38 reaches the number set by the user for a compare event, the number of counts stored in the counter that did not cause the compare e~ent is compared to the minimum set by the user. If that number is greater than tha minimum, then "no fault". Otherwise there is a fault in one of the sensor subsystems.
It should be emphasized that the operation of the fault detection subsystem 30 in no way impedes the arming or disarming of the intrusion detection device 10. During the time that the fault detection subsystem 30 is in operation, the intrusion detection device 10 can still be armed.
There are many advantages to the improved intrusion detection system 10 of the present invention.
First and foremost, with the use of a dual sensor intrusion detection system, false alarm is minimized.
Furthermore, with the fault detection 30, it is seen that the failure of one of the sensor subsystems can be easily detected, and an indication be sent to the user of the failure of the intrusion detection device 10.
Thus, the intrusion detection device lO has all of the advantages of both fail-safe, as well as reliability.
Claims (6)
1. In an intrusion detection apparatus of the type having dual sensing means, a first sensing means for generating a first output signal in response to the detection of an intruder, a second sensing means for generating a second output signal in response to the detection of an intruder, and logic means for receiving said first and said second output signals and for generating an alarm in response thereto, wherein the improvement comprising:
first means for storing the number of first output signals received from said first sensing means;
second means for storing the number of second output signals received from said second sensing means; and logic means for comparing the number of first output signals from said first storing means and the number of second output signals from said second storing means and for generating an output signal indicative of fault in said apparatus, in response to said comparison.
first means for storing the number of first output signals received from said first sensing means;
second means for storing the number of second output signals received from said second sensing means; and logic means for comparing the number of first output signals from said first storing means and the number of second output signals from said second storing means and for generating an output signal indicative of fault in said apparatus, in response to said comparison.
2. The apparatus of Claim 1 wherein said logic means further comprises:
user selectable means for selecting a number for comparing the number of second output signals from said second storing means to the number of first output signals from said first storing means.
user selectable means for selecting a number for comparing the number of second output signals from said second storing means to the number of first output signals from said first storing means.
3. The apparatus of Claim 1 wherein said first sensing means is a passive infrared detecting sensing means and said second sensing means is a microwave detecting sensing means.
4. The apparatus of Claim 1 wherein said first storing means is a counter.
5. The apparatus of Claim 1 wherein said second storing means is a counter.
6. The apparatus of Claim 2 wherein the user selectable means further comprises means for selecting the threshold to cause a compare event and means for comparing the output of said first or second counter, which did not cause the compare event, to a user selectable minimum.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/893,399 US4710750A (en) | 1986-08-05 | 1986-08-05 | Fault detecting intrusion detection device |
US893,399 | 1986-08-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
CA1264832A true CA1264832A (en) | 1990-01-23 |
Family
ID=25401505
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA000542567A Expired CA1264832A (en) | 1986-08-05 | 1987-07-21 | Fault detecting intrusion detection device |
Country Status (7)
Country | Link |
---|---|
US (2) | US4710750A (en) |
EP (1) | EP0259015B1 (en) |
JP (1) | JPH0782589B2 (en) |
AU (1) | AU588207B2 (en) |
CA (1) | CA1264832A (en) |
DE (1) | DE3775305D1 (en) |
ES (1) | ES2028089T3 (en) |
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-
1986
- 1986-08-05 US US06/893,399 patent/US4710750A/en not_active Ceased
-
1987
- 1987-07-21 CA CA000542567A patent/CA1264832A/en not_active Expired
- 1987-07-30 AU AU76296/87A patent/AU588207B2/en not_active Expired
- 1987-07-31 JP JP62190546A patent/JPH0782589B2/en not_active Expired - Lifetime
- 1987-08-05 ES ES198787306935T patent/ES2028089T3/en not_active Expired - Lifetime
- 1987-08-05 DE DE8787306935T patent/DE3775305D1/en not_active Expired - Lifetime
- 1987-08-05 EP EP87306935A patent/EP0259015B1/en not_active Expired - Lifetime
-
1989
- 1989-10-30 US US07/429,054 patent/USRE33824E/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS6345697A (en) | 1988-02-26 |
AU7629687A (en) | 1988-02-11 |
ES2028089T3 (en) | 1992-07-01 |
DE3775305D1 (en) | 1992-01-30 |
AU588207B2 (en) | 1989-09-07 |
EP0259015B1 (en) | 1991-12-18 |
EP0259015A2 (en) | 1988-03-09 |
USRE33824E (en) | 1992-02-18 |
JPH0782589B2 (en) | 1995-09-06 |
EP0259015A3 (en) | 1988-07-06 |
US4710750A (en) | 1987-12-01 |
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