CA2113026A1 - Methods and apparatus for intrusion detection having improved immunity to false alarms - Google Patents

Abstract

ABSTRACT
A multisensor intrusion detection system having greatly improved immunity to false alarms is disclosed.
This system employs a first sensor for sensing an intrusion in a volume of space by a first physical phenomenon and a second sensor for detecting an intrusion in the volume of space by a second physical phenomenon different from the first physical phenomenon. The first sensor generates a first signal in response to the detection of an intrusion into the volume of space, and the second sensor generates a second signal in response to a detection of an intrusion. A microcontroller generates an alarm signal upon the occurrence of one first signal and one second signal within a first interval, the occurrence of another first signal within a subsequent second interval and the occurrence of another second signal within a third subsequent interval.

Description

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PATENT

DETECTION HAVING IMPROVED IM~'IIJNITY TO FALSE ALARMS

A portion of the disclosure of this patent document contains material which iY subject to copyright protection. The copyright owner has no objection to the fac~imile reproduction by anyone of the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.

BACKGROUND OF THE INVENTl ON
The present invention relates to an improved method and apparatus for detecting intrusions and more particularly to a method and apparatus that uses a plurality of sensors. The methods and apparatus of the present invention provide for improved immunity to false alarm~.
Intru~ion detection systems having a plurality of detectors to improve immunity to false alarms are well known in the art. For example, an intrusion detection system will typically use a passive infrared sensor directed to detect intrusion in a volume of spac~ by ~ensing infrared radiation, and a microwave detector directed to detect intru~ion in the qame volume of 3pace by sensing the frequency of reflected microwave radiation in comparison to the frequency of incident microwave radiation. When a signal is simultaneou31y generated by both of the sensors, signal processing circuitry gates the signals and generates an alarm signal.
Another example of an intrusion detection 9y9tem employing a plurality of sensors is shown in U.S.
Patent No. 4,853,677 (see al90 U.S. Patent No. 4,928,085). There, a single microphone detects -2 ~ 2 6 PATENT

both the audible sound of breaking glass and the subsonic sound of pressure on the glass being flexed both before and during breakage. Here again, although a single microphone is used, two different types of physical phenomena are detected ~audible sound waves and low frequency pressure waves) to provide a detection system with greater immunity to false alaxm~.
U.S. Patent No. 5,107,249 shows an intrusion 10 detection system having a first sensor and a second ~ensor, with the second sensor bein~ less su~ceptible to the generation of false alarms than the ~irst sensor. Whe~ the second sensor detects an intrusion, the second qensor generates an output signal and this lS output slgnal is held. The held output signal i~
supplied to a logic gate that receives the signal directly from the first sensor. When the first sensor i8 activated within the period of time that the output signal is held, the logic gate generateR
20 an alarm signal. However, this solution i~ less than ideal becau~e random events that trigger the second sensor will cause the system to become a single technology device for the period of time that the output ~ignal i8 heldO Worse yet, during the period 25 of time that the output signal of the econd sensor iq held, the system effec~ively operates as a single technology system that is dependent upon the less reliable technology.
Accordingly, in the present in~ention, an 30 improved intrusion detection system having a plurality of 9en30r9 that i9 more immune to false alarm generation is disclosed.

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SUMM~RY OF THE INVENTION
The present invention is directed tow~rd a method and apparatus for a multiple sensor intrusion detection ~ystem having improved immunity to false alarms.
In one embodiment of the present invention, a first sensor consists of a microwave detector and a second sensor consists of a pas~ive infrared detector. In this embodiment, an alarm sequence requires that both the microwave detector and the pas~ive in~rared detector each, in any order, sense an intrusion within a first interval. Then, within a second subsequent interval, the passive infrared detector must sense an intrusion, and then, within a third interval that is subsequent to the second interval, the microwave detector must sense an intrusion to thereby initiate an alarm. Depending upon the given volume of space and type of intrusion to be detected, the types of sensors used could he different from a pasaive infrared sen~or and a microwave ~en~or. The type of first and second sensors most ef~ecti.ve for a given volume of space will depend upon not only the environmental conditions of the volume of s~ace but also upon the ~5 expected form~ of intrusion into that space (that is, human, other mammal, reptile or robot). For example, to sense an intrusion by a robot in contrast to a warm blooded animal, it may be preferable to use as a first sensor a differential magnetic field sensor and a pa~ive radio frequency signal detector a~ a second qensor.
Another aspect of the present invention includes a backup capability in the event any of the sensors or their associated circuitry become di~abled. In the preferred embodiment of the in~ention, in the 2~9~

PATENT

event either the microwave detector or the passive infrared detector is disa~led, an alarm will still be initiated i$, with respect to the still operative detector, an intrusion i repeatedly sensed within a predetermined in~erval.
~ better understanding of the features and advantage~ of the present invention may be obtained by reference to the detailed description of the invention and the accompanying drawing that sets forth an illus~rative embodiment in which the principles of the invention are used.

DESCRIPTION OF THE DRAWING
Figures l~a), l(b), l(c), l(d), l(e), l(f), l(g), l(h), l(i), and l(j) are a detailed schematic diagram of the preferred embodiment of the improved intru~ion detection system of the pre~ent invention.
Flgure 2 is a detailed schematic diagram of a microwave transceiver that is utilized in conjunction with the intru~lon detection ~yst~m of Figure l.
Figure~ 3(a~ and 3(b~ are detailed charts showing the poYsible states of the intrusion detection system of Figure 1.
Figure 4 is a block diagram illustrating the ralationship of each software module.

DETAILED DESCRIPTION OF THE DR~WING
Referring now to Yigures l(a) through l(i) there is shown a preferred embodiment of an intrusion detection qystem. The sy~tem include~ a microcontroller 12 which i9 available from Motorola und~r the part number MC68HCo5P3. The microcontroller 12 is a 28 pin device that supervises the operation of and the collection of data from the circuits and ensors that are connected ~hereto and ) r.l ~ ~

PATEWT

as is further described herein. In further detail, the microcontroller 12 includes a central processor unit, memory mapped input/output registers, an electrically programmable read only memory and a random access memory. In addition, the microcontroler 12 includes twenty bidirectional input/output ports and one input only port, a synchronous ~erial input/output port, an on-chip oscillator, a timer, and a four channel eight-bit analog-to-digital converter.
A power 6upply of the system 10 ha~ an input 14 that i9 connected to an unregulated 8.5 - 14.2 volt DC power source which is typically external to such systems and located within a control panel ~not ~hown~. Power i9 ~upplied to the input 14 and is filtered by a capacitor 15. Additionally, the power is filtered by a capacitor 16 to attenuate any AC
components, commonly known as "hum," from the supplied power. A suppressor 18 provide~ over-voltage protection and a diode 20 provides reverse voltage protection. Power at the junction of the capacitor 16 and the diode 20 i9 provided to an emitter of a PNP transistor 24. Power from the jllnction of the capacitor 16 and the diode 20 al~o pas~es through a re~ietor 23 and i8 preregulated by a zener diode 25. This preregulated power is provided to the input of a voltage regulator 22. A resistor 26 i8 connected between the emitter and base of the transistor 24. A capacitor 27 is connected in parallel with the zener diode ~5. An output of the regulator 22 serve~ as a reference for a pair of voltage regulatsr circuits. In particular, the output of the regulator 22 i9 fed through a re istor 28 to the invertiny input of an operational amplifier 30. A capacitor 29 is connected between the output 2;~ 3~2~

PATENT

and input of the voltage regulator 22. The output of the ope~ational amplifier 30 drive~ the base of the transi~tor 24 through a diode 32 and a resistor 34.
A collector of the transistor 24 is connected to a voltage output port 36, which in the preferred embodiment of the invention supplies a potential of about 8.1 volt~.
The collector of the tran~istor 24 is also connected to a capacitor 38, which provides further filtering and voltage regulation. In addition, the collector of the transistor 24 is connected to a test point through a resistor 39. The collector of the transistor 24 is also connected to a voltage divider circuit con~isting of a resistor 40, a potentiometer 42 and a re~istor 44. Thi9 voltage d1vider circuit provides a way of adjusting the potential at the non-inverting input of the operational amplifier 30 to thereby ~et voltage at the voltage output port 36. A
capacitor 45 i~ connected between common and the noninverting input of the operational ampli~ier 30.
A capacitor 41 and a capacitor 43 each operate to attenuate any AC components that may be present at the non-inverting and inverting input ports of the operational amplifier 30.
The output of the voltage regulator 22 is also fed through a re~istor 46 to the non-inverting input of an operational amplifier 4a. A capacitor 49 further fil~ers the power provided to the operational ampli~ier 48. The operational amplifier 48 together with a transistor 50 operate as another voltage regulator to provide a po~ential of ~5 volts that is available at an emitter of the transistor 50 and is used throughout the sy~tem 10. In further detail, an output of the operational amplifier 48 is connected through a resi3tor 52 to the junction of the base of 0 2 ~

PATENT

the transistor 50 and a re~lstor s4. A resistor 56, which i~ connected to the junction of the emitter of the tran~istor 50 and the re~i~tor 54, provide~ a eedback path to an inverting input of the operational amplifler 48. A capacitor 57 provides RFI immunity. A capacitor 58 provides further filtering at a voltage output port 60, and a capacitor 62 operates to provide filtering to the power ~ource for the operational amplifier 48.
In the preferred embodiment of the present invention, an amplifier 64, which amplifie~ the PIR
electrical signal, is partially encased within an RFI
shield constructed of tin plated steel materials.
The amplifier circuit 64 includes a double element passive infrared detector 66. A set of lenses (not ~hown), po~itioned in front of the passive infrared detector 66 determines radiation patterns that can be sen~ed by the detector 66. A mirror may also be employed to define radiation patterns that can he sensed by the defector 66. The passive infrared detector 66 ha~ a grounded gate with its drain connected to the output voltage port 36 through a resistor 68. A capacitor 69, which i9 connected between common and the junction of the resistor 68 and the drain of the paqsive infrared detector 66, operate~ to provide filtering of RF slgnal~.
The source of the passive infrared detector 66 is connected through a resistor 70 to a non-inverting input of an operational amplifier 72. The re~istor 68 operateR to block RF from reaching the drain of the pa~i~e infrared detector 66. The resistor 70 similarly operate~ to block RF from the passive infrared detector 66 into the non-inverting input of the operational amplifier 72. A resistor 74 operate~

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as a load resistor for the passive infrared detector 66. A capacitor 76 provides RFI suppression.
An output of the operational amplifier 72 is ~ed through a coupling capacltor 78 and a resistor 80 to an inverting input of an operational amplifier 82. A
capacitor 83 is connected between common and the inverting input of the operational amplifer 72. The values of a resistor a4 and a resistor 92 are selected to set the gain of the operational amplifier 72. Furthermore, a resistor g2 and a capacitor 94 operate with the re~istor 84 and a capacitor 86 ~uch that the operational amplifier 72 functions a~ a band pas~ filter. The values of the resi~tor 84 and the capacitor 86 set the low pass corner frequency. The resistor 92 and the capacitor 94 set the high-pass corner frequency. Similarly the operational amplifier 82 operates as a bandpass filter with the lower or high pass corner set by the capacitor 78 and the re~istor 30 and the upper or low pa~s corner set by resistor 88 and the capacitor 90. In the prefierred embodiment of the invention, the frequency re~pons~ o each of these bandpass filters is very similar.
A capacitor 96 operates to provide filtering of the power qource connected to the operational amplifier 72. A non-inverting input of the operational amplifier 82 is connected to the output of the regulator 22 through a voltage divider network consisting of a resistor 98, a res~stor 100 through a coupling re~i3tor 102. A capacitor 104 provides further filtering from any noise that may be present at the voltage divider network. The resistors 98 and 100 thereby set the DC bia~ point of an output of the operational amplifier 82. In the preferred e~bodiment of the invention the DC bias point ii~ +2.5 2 ~ 2 ~.~

PATENT
g volts that i~ approximately in the middle of an analog-to-digital converter input 106 (~Np) of the microcontroller 12.
A resistor 108 couples the output of the S operational amplifier 82 to the A-to-D converter of the microcontroller 12 through the input port 106.
The resistor 108 also serves to isolate the microcontroller from the power ~upply used to power the operational amplifier 82. A resistor 109 couples lo the input port 106 ~o a teqt point and provides electrostatic discharge protection and short circuit protection.
In operation, when the pas~ive infrared detector 66 ~en~es a human moving through a volume to be sensed, the signal is amplified by the previously described amplifier, and the signal at the output of the operational amplifier 82 is semi-sinu~oidal in form, having a peak amplitude of about ~0.5 to 2.5 volts centered about the bias voltage of 2.5 volts.
A resistor network consisting of a re~istor 110 a resistor 112, a resistor 114 and a resi~tor 116 operate to provide a reference voltage to the non-inverting input of a set of comparators 118, 120 and 122 and to the inverting input of an comparator 124.
The comparator 118 has an inverting input connected to a port 126 (PA0~ of the microcontroller 12. The potential of this port 126 is normally low, but goes high when a passive infrared event i5 detected. When ~ -tha port 126 goes high (~5 volts), the output of the comparator 118 goes low. When the output of ~he : :
comparator 118 goes low, an LED 128 is energized to : :
thereby indicate a detection of pa~9ive infrared radiation. A resistor 129 acts as a current limiting re istor for the LED 128. Similaxly, the inverting 3S input of the comparator 120 i9 connected to an outpu~

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130 (PA1) of the microcontroller 112. When a doppler ~ignal i9 detected by the microwave de~ector and signal conditioning, as further de~cribed herein, the potential of the output port 130 goes high. Thi~
causes the output of the comparator 120 to go low causing an LED 130 to be energized to indicate ~uch an event. A resistor 131 acts ais a current limiting re~istor for the LED 130. In th~e preferred embodiment of the invention the LED 128 emits green light and the LED 130 emits yellow light.
An inverting input of the comparator 122 is connected to an output port 132 (PA2) of the microcontroller 12. As explained further herein, when an intrusion i~ detected according to a predetermined pattern, the microcontroller 12 will cau~e a potential of its output port 132 to go high thereby causing the output of the comparator 122 to go low thereby energizing an alarm LED 134. In the preferred embodiment o the invèntion the alarm LED
134 emits red light. A resistor 135 acts as a current limiting resi~tor for the LED 134.
A command input 136 is connected through a re~istor 138 to a non-inverting input of the comparator 124. A resi~tor 140 insure~ that the non-~5 inverting input of ~he comparator 124 remain in a high ~tate until the command input 136 i3 ~horted to common. A pair of diodes 142 and 144 are normally reverse biased to thereby provide electrostatic discharge protection and over voltage protection.
In operation, when the command input 136 is shorted to common, the non-inverting input of the comparator 124 goes low causing its output to go low thereby forcing an input 146 (PCl) of the microcontroller 12 ~o al~o go low. Such shorting of the command input 136 provide~ a self-test sequence _, . .... .

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for each of the ~ensor circuits of the system 10.
The non-inverting input of the comparator 124 i9 also connected through a capacitor 148 to common. This capacitor 148 acts to attenuate any RF signals pre~ent at said inverting input. A capacitor 150 similarly act as ~ filter for the~ power ~upplied to the comparator 124. A re~i~tor 1.51 provides the pull up for th~ junction of the output of comparator 124 and the microcontroller input 146. A capacitor 153 provides bypas~ filtering at a power input port of the comparator 118.
An output 152 of the microcontroller 12, through a resistor 154, drives a ba3e of a transistor 156. A
resistor 157 couples the collector of a transistor lS 156 to a trouble terminal 158. A suppressor 159, connected between the collector of the transistor 156 and common, suppresse~ unde~ired tran~ient~ to the trouble terminal port 158. In normal operation the transistor 156 is not conductive and may operate in parallel with an external normally open tamper ~witch that 8en~es the removal of an external cover of the system 10.
The trouble terminal port 158 may be externally connected to a terminal 160 of the tamper ~witch 162.
I~ a cover of the ~y tem 10 were removed, the tamper switch 162 which is normally open would clo~e thereby shorting terminal 160 to common. This condition may be displayed by ~n external display within a control panel to indicate problems with the system 10.
Alternatively, if the microcontroller 12 for ~ome reason determined the existence of a problem, the port 152 of the microcontroller 12 would go high causing the port lS8 to be conductive to common.
The trouble terminal lS~ functions as a trouble output, golng low if either a self test error is 2 ~ 2 ~

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detected or if an error is encountered because of a "fault condition." A "fault condition" can occur because of a failure of a sensor or its associated ~ubsy~tem. Another source of failure which would cau~e a fault condition i~ improper alignme~t of ~ensors, since sensors, in a multiple technology system, must detect the presence oE an intrusion in the same ~pa~e or proxlmate location. Yet another source of failure which would cause a fault condition is tampering, typically by a would-be intruder. For example, ~uch a would-be intruder might mask or intentionally disable a sensor subsystem. U.S.
Patent No. 4,710,750. FAULT DETECTING INTRUSION
DETECTION DEVICE, issued December 1, 1987, assigned to the a signee of the present invention, discloses and explain~ the detection of such fault conditions, and said patent is incorporated herein by reference.
Referring now in further detail to the microcontroller 12, a reset port 164 (RESET) i9 connected through a resistor 166 to an RC circuit consisting of a resistor 168 and a capacitor 170.
When the system 10 is first powered , the resi~tor 168 and capacitor 170 ensure that the reset terminal 164 13 held at a sufficiently low potential to hold the microcontroller 12 in reset until power i9 Up.
An external interrupt port 172 ~IRQ) i9 connected to a port 174 (PA7). The port 174 can function as either an input or output port. In the preferred embodiment of t~e invention the port 174 remains as an input. After power up, the por~ ~74 driven by the output of the comparator 176. A port 178 (PA6), a port 180 (PA5) and a port 192 (PA4) are each connected through a resistor 184, 186 and resistor la8, respectively, to common. These ports are not utilized in the preferred embodiment of the 211~(~2~

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invention. However, to prevent excessive current and potential latch up from floating inputs, it i8 preferable ~o terminate such unused ports.
Additionally, in the unlikely event of a potential charge on common, the resistors 184, 186 and 188 provide current limiting.
As previously described, the~ port 152 (PA3) drives up the base of the transistor 156 thereby causing the tran3istor 156 to become conductive.
Also as previously described, the ports 132 ~PA2), 130 (PA1) and 126 ~PA0) drive the inverting inputs of the compa.rators 122, 120 and 118 respectively.
An alarm output 190 (PB5), through a resistor 192, drives the base of a switching transistor 19~.
When the signal at the port 190 goes high, the transistor 194 conducts and thereby causes current to flow from a transistor 196 through a diode 197 and through a field coil 198 of a relay 200, thereby closlng a set of contacts 202 of the relay 200. The relay 200 i9 normally energized (no alarm). When the contacts 202 open, this condition indicates an alarm.
A pair of resistors 204 and 206 and a zener diode 208 operate to set the limit of potential at the base of the tranqistor 196. When the contacts 202 are closed, an alarm signal path i~ provided at a pair of output~ 210 and 212. This ~ignal path may, if desired, be used to energize a siren, horns, lights or any other electrical device that is reasonably expected to gain the attention of an attendant.
A diode 214 operates to limit the voltage developed cross the field coil 198 when the coil 198 is de-energized. A pair of varistors 216 and 218 are each connected to one side of the contacts 202 to 2:~ 3~6 PATE~T

thereby limit transients which may be coupled to the contacts 202.
A port 220 (PB6) is unused and i8 termina~ed to common through a resistor 222. A port 224 (PB7) selectively drives the passive infrared detector 66 through a transistor 226. In further detail, the port 224, through a resistor 228, drive~ the base of the transistor 226. A capacitor 230 provides filtering, while a resistor 232 terminates the port 224 to common on power up. When the base of the transistor 226 is driven high, the transi~tor 226 becomes conductive thereby providing a path to common for the voltage divider ~hat consi~ts of the resistor 68 and a resistor 234 to common.
A ground pin 236 (VSS) of the microcontroller 12 i~ connected to common.
A port 238 ~RH) i9 u~ed to provide a 5 volt reference potential to the analog-to-digital converter within the microcontroller 12. A re istor 240 and a pair of capacitors 242 and 244 provide filtering of the 5 volt reference supply.
The ports 106 (~0~, 246 (ANl), 248 (AN2) and 250 (~N3~ provide the input of a four channel multiplexer contained within the microcontroller 12.
The proces~or 12, through firmware (detailed further herein), ~elect~ to which channel ~he A-to-D
converter of the microcontroller 12 will be connected. In further detail, the port 106 i9 connected to and dedicated to the pa~sive infrared detection module 64. The port 246 i~ connected to and dedicated to the microwave te3t node. Port 24B
is connected to and dedicated to a thermistor test node.
Re~erring again to the port 248, the port 248 i~
connected to the junction cf a resistor 250 a 2 ~

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capacitor 252 and a thermistor 254. Thi~ circuit functions to provide temperature compensation information (for passive infrarecl detection) to the microcontroller 12. In operation the microcontroller i~ programmed to read the input port 248, in response to that reading which i~ indicative of temperature, the microcontroller 12 adjuqts its internal comparator set points for the passive infrared radiation detector 64.
A port 250 of the microcontroller 12 i9 an A-to-D input which read~ the reference voltage from the junction of the resistor 116 and the non-inverting input of the comparator 176. The comparator 176 has it~ inverting input connected through a resistor 256 lS and a resistor 258 to the power supply port 60 and to the output of a comparator 260. The output of the comparator 176 is connected to the junction of a re~istor 261 and a resi~tor 262. The re~i~tor 262 couples the output of the comparator 176 to the ~ -inputs 172 (IRQ) and 174 (PA7) of the microcontroller 12.
In operation the comparator 260 toggles every time a microwave pulse i9 detected. This keeps the inverting input of the comparator 176 below the threshold provided to lts non-inverting input. If the microwave pul~es stop, the invertlng input of the comparator 176 goes high causing the outpu~ of the comparator 176 to go low, thereby indicating a "no microwave" self test error.

A port 264 ~PC2) i~ connected directly to a port 265 (TACP). These ports are used by the microcontroller 12 to determine microwave events. A
port 266 ~PC0), is used as an input port for a user in~oked self test that i9 actuated by shorting with a 21 ~ ~2~

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jumper 267. In contrast to a signal provided at the command input 136, if a stored error code exists, but the error codes are no longer displayed, a user invoked self test will initiate a display of the error codes and provide service per30nnel a recent history of any system faults. In normal operation +5 volts i9 applied to the port 266 through a resistor 268 and a re~istor 269. When the jumper 267 is shorted to common, the port 266 goes low, thereby initiating a self test sequence.
A port 270 (PD5) could be used to di~able an 03cillator oE the microwave tran~mitter as further descri~ed hersin, however, in the preferred embodiment of the invention, the port 270 does not provide this ~unction. The port 272 (TCMP) i~
unused. The port 266 (TCAP) i9 utilized to provide an external interrupt and i9 configured to b~
~egative edge or falling edge triggered. When a falling edge occurs, such an edge interrupts the microcontroller 12 and provides an indication that a microwave event ~a doppler signal) has occurred.
Microwave event processing of the present invention i9 intexrupt driven, and bPcause it is only edge sen~itive it i9 necessary to sense the output of the microwave circuitry through the port 264 (PC2).
A port 276 (OSC1) and a port 278 (OSC2) are connected to a resistor 280 a quartz crystal 282 and a pair of capacitors 284 and 286. The quartz crystal 282 is selected to operate the clock of the microcontrsllPr 12 at a frequency of 4 megahertz. A
port 287 of the microcontroller 12 is connected to the output port 60 the power ~upply. Bypass filtering at the port 287 i9 provided by a capacitor 288.

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The base of a transistor 2as i9 connected through a resistor 290 to the port 270. The collector of the transistor 28 i9 connected to the junction of a capacitor 292 and the input of a Schmidt trigger 294. The Schmidt trigger 29~
utilizes a feedback path consi~ti~g of a resistor 296, a resistor 298 and a diode 300 to provide an oscillation period of 500 microseconds having a pulse width of 10 microseconds.
The signal oscillates at or about 2 kilohertz and the pul,~e ia about 10 micro~econds in duration.
The output of the Schmidt trigger 294 is fed both to the input of a Schmidt trigger 302 and also through a diode 304 and a resistor 306 to the input of a Schmidt trigger 308. The diode 304, the rasistor 306 and a capacitor 310 operate to delay the transition of the output of the Schmidt trigger 294 to the Schmidt trigger 30~. The output of the Schmidt trigger 302 is ed to the input of each a Schmidt triggex 312 a Schmidt trigger 314 and a Schmidt trigger 316. A diode 317 a resi~tor 318, a capacitor 319 operate to delay the edges of the si.gnal at the output of the Schmidt trigger 302. This con~iguration i9 related to achieving proper sampling waveforms of the detector with respect to the tranRmitter .
The output of the Schmidt triggers 312, 314 and 316 are paralleled into a capacitor 320, a resistor 321 and a capacitor 322~ A junction of the capacitor 320 and the reqistor 321 is fed to the base of a transistor 324. The collector of the translstor 3~4 provides a substantially square pulse to a Gunn diode (a~ explained further herein with reference to Figure 2) through a terminal 326.

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With reerence now to Figure 2, a microwave tran~ceiver 500 i~ shown. The microwave transceiver include~ a Gunn diode 502, which when provided with ~C power oscillat~s with a nominal power output of 8 milliwatt. The transceiver also include~ a Schottky mixer diode 504 which i9 mounted inside a waveguide/antenna 506. The transcei~er 500 al~o includes a resistor 508.
Re~erring now to both Figuxes 1 and 2, in operation the collector of tran~i~tor 324 provides a relatively square pulse to the Gunn diode 502. The Gunn diode 502 thereby generates microwave frequency signal in a range be~ween 9 to 11 gigahertz, depending upon the ampli~ude of the pulse. The microwave frequency signal i8 propagated by the antenna 506. Reflected microwave energy is collected by the antenna 506 and provided to the 5chottky mixer diode 504. The mixer diode 504 mixes tha microwa~e ~ignal from the Gunn diode 502 with the re1ected ~ignal to produce a signal with a certain pha~e. As a per~on moves within the senqed volume of ~pace the phase changes thereby creating the doppler ~ignal.
Thi3 ~ignal is provided to the inverting input of the comparator 260 and to a ~ampling field effect transistor 330. Tha non-inverting input of the comparator 260 i~ connected to a voltage divider network consisting of a re~i~tor 332, a re~istor 334 and a capacitor 336. This voltage divider network ~e~ the threshold of the compara~or 260. The capacitor 336 i9 a bypass capacitor.
The output of an operational amplifier 360 provide~ a relatively low frequency signal repre~entative of doppler shift resul~ing from movement of an object within a space which is -2~ ~ 3~2~

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monitored. The doppler signal has a frequency gen~rally he~ween 5 and 70 Her~z.
Referring again to Figure 1, the output of the Schmidt trigger 294 iR fed to the input of the Schmidt trigger 309 through the shaping network consi~tirlg of the diode 304 the resistor 306 and the capacitor 310. The output o~ the Schmidt trigger 30a is fed to the gate of a ~ampling field effect tran~istor 330.
In operation the sampling field effect tran~i~tor 330 sample~ the pulse from the Schottky mixer diode 504 only during the period that the pulse is fed to the sampling field effect transistor from the Schmidt trigger 308. Stated differently, the ~ampling field effect transi~tor ~30 begins sampling at the leading edge of the pulse from the Schmidt trigger 308 and stops ~ampling at the falling edge of the pul~e from the Schmidt trigger 308.
The output of the sampling field effect transistor 330 is fed through a filter consisting of a capacitor 338, a capacitor 340 and a capacitor 342 to the non-inverting input of an operational ampll~ier 344. A capacito~ 346, a resi~tor 348, a re~istor 350 and a capacitor 352 together enable the op~rational amplifier 344 to function as a bandpass ~llter. A resistor 354 provide~ a bias to the non-inverting input of the operational amplifier 344 while a resi~tor 356 and a potentiometer 358 provide a bias to the output of the operational amplifier 344.
The center arm of the potentiometer 358 iq connected ~o the non-inverting input of an operational amplifier 360 through a resistor 362. A
capacitor 364 i9 connected between the non-inverting input of the operational amplifier 360 and common.

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Power is provided to the operational amplifier 360 from the power output port 36, and such power is filtered with a bypass capacitor 365.
A re~istor 366, a capacitor 368, a resistor 370 and a capacitor 372 operate to enable the operational amplifler 360 to function a a bandpa~s filter. The output of the operational amplifier 360 i~ fed to a pair of back-to-back diodes 374 and 376 and also to the inverti.ng input of an operational amplifier 378 through a resistor 380. A reRistor 382 sets the gain of the operational ampllfier 378. The output of the operational amplifier 378 is fed to a pair of back-to-back diode~ 384 and 386. The~e diodes 384 and 386 conduct during the negativP portion of a wav~orm.
Similarly, the diodes 374 and 376 conduct during the negative part of a waveform ~uch that as diode 374 pull~ low i~ turn~ oEf diode 376. At this point a ~-palr of time constants ~et by a capacitor 388 and a capacitor 390, in conjunction with a resistor 418, a re3istor 420 and a resistor 422, begin to decay, and cross ov~r a point at which comparator 396 flips and provides a low output. The arrang~ment of the tranqistor 398 and the comparator~ 396 and a comparator 406 provides a hysterisis effect. In operation, when the output of the comparator 396 goes low, thi~ causes the output of the comparator 406 to go low.
This turn~ on the transi tor 398 which causes the non-inventing input of the comparator 396 to go high, which in turn causes the output of the comparator 396 to return to high.
A resistor 400 operates ~o et a bias point for the diode~R 374 and 376 and contributes to a time constant with a capacitor 416. Only a continuing doppler signal will cause the potential of non-2 ~l ~ 3 ~

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inverting input of the comparator 396 to begin to decay again. Hence, any noise will not cause false microwave events because the hysteresis opens the threshold back up. A resistor 402 couples the junction of the diodes 374 and 376 to a test point 404.
The operational amplifier 378 forms part of an absolute value circuit, providing fullwave rectification to the negative peak detecting floating threshold circuit connected to the comparator 396.
The comparator 396 provides a pulse out of the microcontroller 12 and provides immunity to noise.
As the signal provided to the inverting input of the comparator 396 decay~, the output of the comparator 396 flips and goes low and i8 then tran~lated by a comparator 406 whose output is fed to input 266 of the microcontroller 12. Additionally, an operational amplifier 408 ~amples the slgnal at the inverting input of the comparator 396 and pro~ides an output operative to determine whether the ~ignal at the inverting input of the comparator 396 i5 within a certain tolerance. This within tolerance confirmation signal i~ provided to the input port 246 of the microcontroller 12.
Referring again to the comparator 406, the output of the comparator 406 i9 provided to a feedback path consisting of a resistor 410, a filter capacitor 412, and ~he transistor 398. The collector of the transistor 398 i~ connected to the non-inverting input of the comparator 396. A capacitor 414 provides bypass filtering at the emitter of the transistor 398. The capacitor 416 operates ~ogether with the resistor 400 to provide filtering of signals from the output of the operational amplifiers 378 and 3S 360. The resistor 418 couples the diode 376 to both -~3~

PATENT

the inverting input of the operational amplifier 396 and, through a voltage divider consisting of the re~istor 420 and a resistor 422, to the non-in~erting input of the comparator 408. A resistor 424 i2 u~ed to balance the bias current of the operational amplifier 408. A bypas6 capacitor 426 provides filtering of power supplied to the operational amplifier 408. A resistor 428 couple~
the output of the operational amplifier 40B to the port 246 of the microcontroller 12.
A voltage divider consisting of a resistor 430 and a resi~tor 432 ~et~ the bia~ at the inverting input of the comparator 406. A capacitor 434 provides filt~ring at the inverting input of the comparator 406. A capacitor 440 together with the resi~tors 436 and 438 provide an RC delay. A
capacitor 442 provides bypass filtering at the power input port of the comparator 406. A resistor 444 operate~ a a pull up resistor at the output of the comparator 406. A resistor 446 provide~ a positive feedback hysteresis to the non-invertin~ input of the comparator 406. Stated differently, ~he resistor 446, a0 a function of the output of the comparator 406, shift~ the bias point of non-inverting input of the comparator 406.
Referring now to Fig. 3A there is ~hown a state diagram that vlsually illustrates an alarm processing sequence of the preferred embodiment of the invention. In particular, when the pa~sive infrared circuitry sanse~ an intrusion within a given volume of space this intrusion is called a "pa~ive infrared event." Similarly when the microwave circuitry of the sy~tem lO ~enses an intrusion within a given volume, this is called a "microwave event." In the O
preferred embodiment of the invention, the ~ystem lo ~1:1 302~

PATENT

is initially in state 0. If either a microwave event or a passive infrared event occurs and is followed by the other event separated by a time period greater than 4 seconds, the system lo remains in state 0.
When a microwave event or a passive infrared event occurs, and i8 followed by the other event wi~hin a period of less than 4 seconds, th~3 system 10 enter~
state 1.
While in ~tate 1, if there i8 no occurrence of a pa~sive infrared event of the same polarity within 15 seconds o~ the commencement of state l, the system 10 returns to state 0. If a passive infrared event occurs withi.n 15 seconds while the system 1o is in state 1, the system 10 advances to state 2. While in state 2, if no microwave event occurs within 4 seconds of the commencement of state 2, the ~ystem lO
returns to state 0. However, if a microwave event occurs within 4 seconds of the commencement of state 2, then an alarm signal i generated. In the preferr2d embodiment of the invention, the alarm signal has a duration of 5 seconds after which the system 10 reverts to state 0. Whenever the system 10 i~ in state 0, the entire alarm processing sequence can be repeated.
In summary, an alarm 19 generated only by the occurrence o~ the following sequence of event~:
1. Either a microwave event or a passive infrared event occurs and is followed by the other event within four seconds; and 2. Thareafter, a passive infrared event of the ~ame polarity occurs within fifteen seconds; and 3. Thereafter, a microwave event occurs within four 3econds.

-PATEN?

Thus a total of four detection events (two paasive infrared eventq and two microwave even~s) within prescribed time periods must occur before an alarm signal i9 generated. The requirement of numerous events being detected before an alarm signal is generated can be seen with reference to the condition if one of the sensors and its circuit malfunctions.
Referring now to Figure 3B, in the event either 10 the pa~sive infrared portion of the sy~tem 10 or the microwave portion of the system 10 malfunctions, the system 10 enters a qingle technology mode that i8 illu~rated by Figure 3B. While in thi~ mode the system 10 relies upon the sensing technology that is 15 still operational. Initially, the system 10 is in state 0. If the operational technology detects the occurrence of an event, the system 10 move from state 0 to state 1. Such an initial detection need not occur within any predetermined period. If the 20 operational technology doe~ not then detect an event within 4 ~econd~ of ~he commencemen~ of state 1, the ~ystem 10 reverts to state 0. If however, the operational technology detects an event within 4 seconds of the ~ommencement of state 1, the ~y~tem 10 25 generate~ an alarm signal. The alarm signal has a duration of 5 ~econds, after which the ~ystem 10 returns to state 0. At that point the syqtem 10 reverts to qtate 0, and i9 ready to repeat this alarm proce~Ring sequence.
As can be seen, in the event one of the sensor sub~y~tems malfunctions, the remaining operative sub~y~tem would not trigger an alarm signal based upon the detection of a single event. The remaining operational sen~or ~enerates an alarm qignal if two 35 detection~ occur within a predetermined time period.

2~3~

PATENT

Although in the preferred embodiment of the invention thi~ predetermined time period is also four seconds as is the f irst time period used when both sensor ~ystems are operativ~, the predetermined time period for thi~ back-up mode ~f operation may be a different length, for example, seven ~econds. In addition, different length predetermined time periods may be utilized when both the pal3sive infrared and microwave portions of the sy~tem 10 are operative.
Figure 4 illustrates various module~ of the computer program utilized in the preferred embodiment of the invention and how each of the modules relate to the others. "variables" are stored in R~M within the microntroller 12 and are available to these modules. "Vector~" contains addre~es of interrupt routines and the start addres~ of the program (Init) which is initiated on a Reset. As detailed in the source code listing below, the alarm algorithm is contained within the background (BCKGND) module.
INIT refers to initialization, BAS~LN refer~ to the baseline subroutine and AVER refer~ to the av~raging subroutine .
The ollowing i~ a source code listing of the computer program for the microcontroller 12 in accordance with the preferred embodimen.t of ~he invention:
Copyright ~1993 C&K System~, Inc.
,~,****~**.~,*****",*****~************~********~***~******
* Thi~ module containq all port register and RAM *
* equate3 also it oontain3 the look up table for *
* the LED code~ *
*
**~*~***~***b~b**~**~****~*~*******~**~*,~*~****~*
VARS:
XDEP POR~A,PORT13,PORTC,PORll~,DDRA,DDRB
XDEF DDRC,DD~,5CR,TCR,PRo~,ADSCR,ADDR,MOR,COP
XDEF TESTYP,LEDS,FL~H,TES~&M,ANSWLO,~NSWHI

2 1 3 3 t) r ~ ~

_A~

XDEF AVEHIGH,AVELOW,AVECNTH,AVECNTLI,INTERH,INTERL
XDEF INTCNT,STPTLO,STPTHI,TSTAT,TTIME,UPIRl,UPIR2 XDEF LPIRl ,LPIR2,PPNUM,AVECNT,FLSHTM,TSRTCNTH,TCNTL
XDEF ATCNTH,ATCNTL,ICR~,ICRL,OCRH,OCRL,XESCTL,RESC~H
XDEF UWAVE,ALRMCT,STATE,STIML,STIMH,POLAR,POST~S
XDEF ATIMER,NEGTHS,PIRCNT,UWAVNF,UWAVC,PIRHIC,PIRLOC
XDEF STACNT,STA2C,ERCODE,FAILl,STIMM,RES8,PIRBCT
XDEF TMPTIM,TTIML,TTIM~,NEGINF,DELTIM,DELTA,TROU~3 XDEF TRBSTA
PORTA EQU $0000 PORT~ EQU $0001 ~.
PORTC EQU $0002 PORTD EQU $0003 DDRA EQU $0004 DDR}3 EQU $0005 DDRC EQU $0006 DDRD EQU $0007 SCR EQU $000A
TCR EQU $0012 TSR EQU $0013 IC~H EQU $0014 ICRL EQU $0015 OC~H EQU $0016 OCRL EQU $4017 TCNTH EQU $001 a TCN~L EQU $0019 ATCNT~ EQU $00lA
ATCN~L EQU $001~3 PRO5 EQU $001C
ADDR EQU $001D
ADSCR EQU $001E
MO~ EQU $0900 COP EQU $1FF0 TESTYP EQU $0080 ~ SelE Test Typ¢~ B7 1 , PU/UI, 0 ~ 0~ Going B6 1 ~ Toggle A Relay, 0 Don't B5 1 ~ Di~play On Going ST Code ~ ~3 1 , Temp Comp Failure t ~2 l On Going Failure PS
~ B1 1 , Single Te~ uWave ~ B0 1 ~ Single Tec PIR
LEDS EQU $0081 FLASH EQ~ $0082 I Toggle byte with LED3 : ~ :
TTIME EQU $0003 ~ Time Var for Pu Self Te~t PLSHrM EQU $0084 ~ Toggle Rate of LED~
.

2 ~

ATIME~ EQU $0085 ~ Alarm Timer Flag ~ BO ~ uWave Timer * Bl = PI~ Upper Timer * B2 PIR Lower Timer ~ ~3 - State 1 Timer B4 ~ Stat~ 2 Timer ~ ~7 ~ Alarm Timer STAT~ EQU $0d86 ~ B7 , l Alarm~ B6 1 RES
B5 , On Going ST Time 0 ~ ~4 ~ Pending alarm State 2 B3 , Pending alarm State l B2 , Out of thre3hold Bl 1 ~ Trouble uWave ~ BO 1 Trouble PIR
TSTAT EQU $00~7 ~ Te3t Statu3 Byte B7Q1 Fail B5 , 1 PIR Set Point Fail B4 - 1 Temp Comp Fail * B2 = 1 STPu~,B3 - 1 STPPIR
~ BO , 1 STBuW, ~1 , 1 ST~PIR
ERCODE EQU $008~ * Eigh~ bit error code * $20 - $2~ addre~3 to LED/1a3h * codes FAIL1 EQU $00~9 * SUqPECT MODE SAME AS ABOVE
~ 7 , Power Supply, 6 - uWave Ba~e ~ 5 , uWave Pls, ~ ~ PIR PLS
* 3 ~ PIR BASE 2 = Temp Comp ~ 1 ~ u~ave INP O ~ PIR INFORM
AVEHIG~ EQU $008A ~ High byte o~ running average AV~LOW EQU ~0082 * Low byte of running average AVECNr~ EQU $ooac ~ High byte of average counter AVECNTL EQU $ooaD ~ Low byte o~ average counter INTER ~ BQU ~008E * Intermediate ave high byte INTER EQU $008F * Intermediate ave low byte INTCNT EQU $0090 ~ I~term~diate counter ST~TLO EQU soosl ~ Lower compari~on value for ba3eline STFT~I ~QU $0092 ~ Upper comparl~on val~ for ba~eline UPIR1 EQU $0093 ~ Up~e~ PIR Set Point Copy 1 UPIR2 EQU $0094 ~ Upper PIR Set Point Copy 2 LPIR1 EQU $0095 ~ Lowe~ PI~ Set Poi~t Copy ~
LPIR2 EQU $0096 ~ Lower PIR 5et Poin~ Copy 2 PPNUM EQU $0097 AVECNT EQU $009 ~ESTNM EQU $0099 ~ ~old~ number of average~
ANSWLO EQU S009~ ~ Low byte of total ave ANSWHI ~QU $009B ~ High byte of total ave U~AVE EQU $oogc ~ uWave Alar~ Status RESCTL EQU $009D ~ RES counter low byte RESCTH EQU $009~ ~ RES co~nter high byte 0 2 ~

PATEMT

ALRMCT EQU $oo9F ~ Alarm tiMer counter STIM~ EQU $00A0 * Low byt~ self test tim~r STIMM EQU $00A1 ~ Medium byte sel test timer STIM~ EQU $00A2 * High byte: aelf test timer POLAR EQU $00A3 ~ Polarity variable PIR signal * F7 ~ Positiv~ pola~ity * F6 ~ Negative polarity t F1 ~ Po3iti~e C)ut o~ Threshold * P0 ~ Negative Out of Thre~hold POSTHS EQU $00A4 ~ Po3itive Thre3hold Counter for PIR
NEGT~S EQU $00A5 * Negative Thr~shold Counter ~or PIR
~ Informer PIRCNT EQU $00A6 ~ PIR Informer Counter UWAVNF EQU $00A7 * uWAVE In~ormer counter UWAVC EQU $ooA~ * Timer for uWave Alarm PIRHIC EQU $00A9 * Timer for PIR Upper T Crossing PIRLOC EQU $ooAA b Timer for PIR Lower T Crossing STA~NT ` ~QU $ooAB * 15 sec timer for state CouAter STA2C EQU $ooAC * 4 ~econd tlmer state 2 TMPTIM ~QU $ooAD f TEMP COMP time var TTIML EQU $ooAE ~ Low byte of temy comp timer TTIMH EQU $ooAF ~ High byte of temp comp timer RES8 EQU $o0Bo * Byte zero of eight RES timers * Do not u3e any bytes between * B0-B7 in~lusive NE~INF EQU $00~8 ~ Negative Thr~hold Counter DELTIM EQU $00B9 * Delta timer for RES
DELTA EQU $00BA ~ D~lta Timer Flag PIRBCT EQ~ $008B ~ PIR Baseln co~nter up to 8 TROt~3 EQU $00LC * TROU~LE PULSE WID~H COUNTER
TR~STA EQU $00BD ~ TROU~LE ST~TUS
* B7 , DRIVE TROU~LE 8 SEC
~ B6 - DRIVE TROUBLE 4 SEC
*No longer toggle trouble made it 0 ORG $0020 FCB $87 ~ ROM LED CODE AT $20 lERCODE) ~CB $07 * ROM FLASH CODE AT $21 FCB $~7 ~ R~M LED CODE AT $22 (ERCODE) PCB $04 * RAM FLA5H CODE AT $23 FCB $84 * P~R SUPPLY LED CODE AT $24 (ERCODE) FCB $04 * PWR SUPP~Y FLASH CODE AT $25 FCB $86 * uW~VE LAS~LINE LED CODE AT $26 (ERCODE) FCB $og * uW~VE BASELINE FLASH CODE AT $27 FCB $86 * uWAVE PULSE LED CODE AT $28 (ERCODE) FCB $06 ~ uNAVE PULSE FLASH CODE AT ~29 ~ :
FCB $85 r PIR PULSE LED CODE AT $2A (ERCODE~ :
FCB $05 ~ PIR PULSE FLASH CODE ~T $2 FCB $85 ~ PIR 8ASELINE LED CODE AT ~2C (ERCODE) FCB $04 ~ PIR ~ASELINE FLAS~ CODE AT S2D ~.
FCB $a3 ~ TMP CMP LED CODE AT $2E (ERCODE) . .-FCB $03 * TMF CMP FLASH CODE AT $2F
FCB $a7 * DUAL TECH FAIL1~3X LED CODE AT ~30 (ERCODE~ ~ :

21 :L 3 0 ~

PATENT

FCB $03 ~ DUAL TECH F~ILURE FLASH CODE AT $31 end *~**~b*~b~f*~*~*~**~**~***b~b~**~b~**~***~ b~b~
~ Real Time Interrupt Routine perform~ all timing related * u~er inter~aces. Fla~hes LED3, Counts down aelf test * duration. Peforms alarm timing etc. *
* Also serv~s a~ the Microwave (Input Capture) Interrupt vector 5ince it i9 shared, routin~ must poll the ~tatu~
~ register to determine who int~rrupted 1~ ., *~*~b~bb~**~b~*~*~**~*~*~b~*~ *~**~b~b~*~b XREF BSCT:TESTYP,FLS~TM,LEDS,FLASH,PORTA
XREF BSCT:TTIME,TSR,TCR,TCNTL,PORT8,OCRL,OCRH
XREP BSCT:ICRL,ICRH,UWAVE,ALRMCT,STA2C
XREF ~SCT:RESCTL,RESCTH,gTIML,STIMH,TSTAT
XREF BSCT:UWAVC,PIRHIC,PIRLOC,STACNT,ATIMER,FAIL1 XREF BSCT:DELTA,POLAR,D~LTIM,STATE,STIMM
XREF BSCT:TMPTIM,TTIML,TTIMH,TROUB
XREF PSCT:COP
XDEF TIMER
TIMER:
~RCLR 7,TCP,TOVL * Input Capture not enabled BRCLR 7,TSP,TOVL * Input Capture didn't interrupt LDA ICRL ~ Read low byte ~lear Elag BSET 7,VWAVE ~ Indicate uWave occured BSBT 7,DEETA f Start Delta Timer if nec BSET 1,PORTA ~ Dr~ve LED
BCLR 7,TCR * Di~able IC until acknoledged ~ By background routine TOVL: BRSET 5,TSR,CTIM2 JMP RETURN ~ No Real Time Interrup~
CTIME: LDA TSR * Temporary Clear 5tatu~
LDA TCNT~ * Read lower byte clear I Flag CLRA
STA COP
*~ *~**~*~*~*~**~***~*~**~*~ *NEW TROVBLE~*~*~*~
BRSET 7,TESTYP,C~TYPE DON'T PULSE IF PU OR UI
TST TROUB * Check t~ouble BEQ CHTYPE
DEC TROUB * DECREMENT TBOUBLE COUNTER
LN~ CHTYPE
BCLR 3,POBTA ~ TROVBLE PULSE TIMED OUT
**~*~*~*~*~*b*~b~*~*b~bb~*~*~*b~ ~bbb*~*~*
CHTYPE: LDA TESTYP b Chec~ to ~ea if PU or UI ST
AND #$EO * HIGHEST PBIORITY
~NE DISPhAY ~ No Single Tec either ~DA #$03 AND STATE

-2 ~. 3 ~

BEQ SKIPDP * No Trouble no Display INC FLSHTM ~ Else use a different Flash Rate LDA FLSHTM
CMP #$06 * Slower Flash Rate BCS SKIPDP
CLR FLSHTM
BPA NOROM
SKIPDP: BRSET 3,TESTYP,DISPLAY * lowe~t prlorlty T Comp error BRA CXALRM
DISPLAY: INC FLSHTM
LDA FLSHTM
CMF #$01 * Fla~h time ~l/2 perlod)~
~CS CK~UR * 5 time~ .142 sec CLR FLSHTM * Rezero BRCLR 6,TÆSTYP,NOROM * If not ROM Test leave LDA PORTB * ~larm ~elay alone EOR #$20 * Else toggle it STA PORTB
NOROM:
LDA LEDS
EO~ F1~S~ ~ Flash those LEDs that Flash STA LEDS * Do not toggle T relay *~ r*~*~**~*~*~*~***~****~lt*****~*~***~*~**~
~RCLR 3,PORTA,NTROUB
. ADD ~$08 ~*~***~ ***~ r*~*h~**~**~*~ 1r*~rh*~*~ *~ tb**~t NTQOUB: STA FORTA
CKDUR: LDA TTIME
LEQ CXALRM
D~C TTIME
CRALRM: BRCLR 7,TESTYP,CTIMS
JMP RETURN * If PU ST leave alone :~
CTIMS: BRCLR 7,A~IM~R,CKDEL ~ Check if in alarm DEC ALRMCT ~ Decrement alarm counter ~NE CKDE1 ~SET 5,PORTB ~ CLEAR Alarm Relay BCLR 7,ATIMER
DCLR 7,STATE
TST TESTYP ~ Don't clear LEDs if flashing code BNE CKDEL
CL~ PORTA * Clear LEDs CKDEL: B~SET 6,STATE,CKRES ~ RES don't inc counter ~RCLR 7,DELTA,CKRES ~ no dalta timer continue LRSET O,DELTA,DELTOG ~ when ~et advance counter BSET 0,DELT~ ~ ~et up to inc it next time aRA CKRES ~ don~t increment counter thi3 time DELTOG: ~CLR 0,DELl'A ~ set up 80 next time dosn't inc it INC DELTIM ~ increment the counter this time 2~ 1 302~

PATENT

BNE CKRES * continue to next timer COM DELTIM ~ ~eep at FF about 70 seconds CKRES: ~RCLR 6,STATE,STATIM ~ Ch~ck ~E RES i~ active INC RESCTL ~ I~ 90 increment counter BNE STATIM
INC RESCTH ~ Propogate up LDA #$0E * 8.5 minutes CMP RESCTH * Chec~ if RES is Up BCC ST~TIM
BCLR 6,9TATE * If 30 clear RES Flag CLR RESCTH
STATIM: ~RCLR 4,ATIMER,STAlTM ~ See if in State 2 CKSlTO: CFX #$28 ~ Compare 2 time out period ~CS STAlTM
~CLR 4,ATIME~ ~ If longer clear counter STAlTM: LDX #$07 ~RCLR 3,ATIMEP,UWTIME
LDA #$72 * 15 Second Timer INC STA~NT
CKSTMl: CMF STACNT
PCC UWTIMæ * 15 Seconds not up ~CLR 3,ATIMER ~ Timed out no alarm CLR POLAR ~ Clear reference to Polarity CLR ST~CN~
UWTIME: LDA #$1E * 4 Second tim~r BRCLR 0,ATIMER,PIRTM ~ No uWave Timing Required INC UWAVC
CPX UWAVC
LCC CKWVC
TST TESTYP * Lon't keep ~learing if BNE CKWVC ~ fla~hing another code BCLR l,PORTA ~ Clear uWave LED
C~WVC: CMP ~WAVC * Compare to 4 second~
~CC PIRTM * If less check PIR
LCLR 0,ATIM~R ~ If longer clear counter CLR UWAVC
* 4 Second ~ounter i~ Accum PIRTM: BRCL~ l,A~IM~R,CKLWCT * Check to see i~ High Counter INC PI~HIC * Incremen Hi~h T Counter byte CMP PIRHIC * Compare to 4 9econd timer in A
BCC CKLWCT
~CLR 1,ATIMæR ~ Clear alarm timer CLR PI~IC ~ Reset counter BRSET 3'ATIMEP,CKLWCT ~ Don't clear Po9 Pol if ~tate 1 ~CLR '7,POLAR * i9 Rtill active else Cl~ar PPF
BCLRl,POLAR
CXLWCT: ~RCLR 2,AT:rMER,S~LFTM ~ No Low Count~r leave lNC PIRLOC

2 1 ~

PATENT

CMF PIRLOC
LCC SELFTM ~ Has not timed out ~CLR 2,ATIMER ~ Clear alarm timer CLR PIRLOC ~ Reset aounter BRSET 3,ATIMER,SELFTM ~ Don't clear Neg Pol if State BCLR 6,PO~AR ~ i3 still actlve else clear it BCLR 0,POLAR
SELFTM: LDA ATIMER
AND #$06 BEQ STIMER
LDA PIRHIC ~ ?ake average of counts ADD PIRLOC ~ Clear 1~ they are greater LSRA * than 8 CMF ~$04 BCS STIMER
TST TESTYP ~ Don't keep clearing LEDs if BNE STIMER * flashing another code BCLR 0,PORTA
STIMER: BRSET 5,9TATE,TMPIT ~ Self Test ~till pending INC STIML ~ Increment lower byte ~NE TMPIT ~ NO ROLLOVFR NO POSSI~3ILITY OP TEST
INC STIMM ~ PROPAGATE ROLLOEVER
~EQ HIBY'~ ~ IF Z~RO MOVE UP
TST FAILl ~ Te~ if in short ~t mode B~Q TMPIT ~ no go check temp timer LDA #$1A ~ yeq see if 15 m.in ST timer is up CMP STIMM
BCC TMPIT ~ not up go check t~mp comp BRA SET5 ~ set ~t i~ 1900 for ahort lnterval HIBYTE: INC STIMH ~ INCREMENT HIGH BYTE
LDA #$09 ~ ~heck high byt~ long timer A0000 -CMP STIMH :~.
LCC TMPIT ~ not done, check temp comp SET5: BSET S,ST~TE ~ Set ST 5tate tclear~ count9 ~ for trouble invoked 9~) CLR STIMM ~ CLEAR BYTES FOR N~XT
CLR STIMH ~ LSB ALREADY CLEARED
TMPIT: BRSET 7'TMPTIM,RETUPN ~ temp comp variable already 9et INC TTIML ~ INCREMENT LOW BYTE OF TEMP TIMER
L~E RETURN ~ NO ROLLOVER
INC TTIMH
LDA ~$3S ~ USE $3600 AS COUNTER 30.19 MIN
CMF TTIMH
BCC RETURN
PSET 7,TMYTIM ~ SET TIME FOR TEMP COMP VAR
CLR TTIMH ~ TTIML ALREADY ZERO
R~TURN: RT~ ~ Return ~rom Interrupt end 2~ 02~

P~

*~** ~ *~*~*~r*~ b~*~ h*~ * ~ *l~tt ~ Initialization Routine, init3 regs, vars, ports * Per~orm first part of Power Up Self Test * ROM, RAM tests ~ Routine entered only by Power Up, User ~nvoke or ~ Command Input Self Test *
*
~**~*f*~*~***~ *1t*~ *~**~*~ ~*~*~ *

XR~F BSCT:DDRC,DDRD,SCR,DDRA,DDRB,PoRTA,PoRT8,PoRrrD
XREF BSCT:FLSHTM,TTIME,TCR,ADSCR,TESTYP,LEDS,FLASH
XREF BSCT:TSTAT,STPT~I,STPT~O,PPNUM,PORTC,TSR,ATIMER
XREF BSCT:ADDR,TE9TNM,AN9WLO,ANSWHI,UPIRl,UPIR2 XREF BSCT:LPIRl,LPIR2,STATE,OCRL,ICR
XREF PSCT:CHKPWR,COP
XREF BSCT:DELAY,I.EDRIV
XDEP INIT

OR~ $0100 ~ Port D5 output low INIT: ~SET 5,DDRD ~ enables uWave Osc.
BCLR 5,PORTD
CLRA
STA COP
CLR SCR * Di3able SCR
CL~ FLSHTM ~ Init Fla3h period CLR ATIMER
CLR STATE * Init State LDA #$0F * Set 3-0 to output~
STA DDRA * Set 7-4 is input BSET 3,PORTA ~ DRIVB TROUBLB FOR TEST DURATION
LDA #$A0 STA DDRB ~ B7~B5 Out B6 in, Rest Don't Care LDA #$C0 * Po~er Up Self Tes~
STA TESTY ~ Toggle Alarm Relay for 5 Seconds LDA #$15 ~ Store ROM te~t time duration STA TIME ~ Test Time Var decremented in LDA #$20 ~ Timer Module, read here STA TCR ~ Di~able Input Capture, * Disable Output Compare * Enable Timex OYerflow ~ Falling ~dge on TCAP
~ Low Output on TCMP
LDA #$23 STA ADSCR * A/D on, chan 3 selected ~p. 9 . ) ROMTS:
CLR PORT8 ~ Drive alarm (5 seconds) LDX #$20 ~ Keep IRQ di2abled externally JSR LEDRIV ~ ~$20 is also address to ROM codes) * Store di3play codP in LEDs 2~ 13~2~

PATENT
~34-CLRX
3SR DELAY * LET MICROWAVE POWER UP
JSR DELAY
CLI ~ Allow Timer Ov2r~1Ow interrupts ROM2: CLRX ~ Start at beginning of ROM
CLRA ~ 8ecause there is only an a bit STA COP
ROMl ~OR $0100,X ~ ind~x reg, can only te~t 256 EOR $0200,X ~ saves having eight loops EOR $0300,X ~ final result i8 the same EOR $~400,X ~ check~um held ln last byte EOR $0500,X ~ of ROM
EOR $0600,X
EOR $0700,X
EOR $0800,X
INCX
~NE ROMl TSTA No CHKSUM is being performed ~ BN~ ROM2 If fails repeat TSTA
BN~ ROM2 STA COP * Hit Dog CAN' T VSE BCLR ONLY
RMTIM: LDA TTIME * Check to see if time is up PNB ROM2 ~ Still in ~elf test BCLR 6,TESTY ~ Clear alarm toggle flag ~SET 5,PORTB ~ clear alarm ~ Dri~e LEDs and Trouble R~MTST: LDX #$22 * Put in Fla~h Code for RAM
JSR LEDRIV * $22 i~ address t~ RAM LED codes LDA #$15 STA TTIM~
TRAM: LDX #$~8 ~ Leave LED, FLAS~ ~tc var~ alone ~::
TRAMl: LDA #$AA * Altexnating bits STA ,X
CMP ,X :~
~NE RAMTST
COMA ~ Other alternatlng bits STA ,X
CMP , X
~NE RAMTST
CLRA
s~rA ,X ~ Init bytes to ~ero STA COP * Hit Dog INX
BNE TRAMl ~ATIM:
LDA TIM~
rRAM
~ Go to ongoing portion of ST
~ load right aft~r init with ~ linker 2:~30~

PATE

XREF BSCT:LEDS,PORTA,FLASH
XDEF LEDRIV
* Commonly u~ed LED Rout1ne, Xreg point~ to lookup table * display codes ~or LEDs and FLASHing OR~ $0040 * ROM CRUCH DO NOT ADD TO THIS ROUTINE
~ IT IS l5 BYTES AND WILL NOT FIT HERE
* IF ADDED TOIIIIIIIIIIII
LEDRIV: LDA ,X ~ get the led code ST~ LEDS * store it in LED var ****~********~I***~ ***A~*~**~**~*******~******~**********
LRCLR 3,PORTA,DRVIT
ADD #$08 ~ m~lntAin troubl~ atat~
*~********~***********~**~*~b~*~*~*~*~*~**~ ****~***~*~
lS DRVIT: STA PORTA * drive the LEDs INX b get the flash code hDA ,X
STA FLASH ~ 3tore it in the FLAS~ var RTS
~ND

~*L'~*~*************~******~**~****~***~O*~ **~
This routlne is the core ~f Self Test Fir~t it per~orms the Power Supply Test * Ne~t it looka at the Microwave baseline *
25 * Next it look3 at ~or the ~icrowave receive pu199 *
Next lt performs a ran~ient test on the PIR Amp * Ne~t it measure~ ths PIR ba~eline *
Finally it Temp~ratur~ Compensat~s th~ PIR *
* Al~rm thre3hold ~ *
~*~*~*~*~*~:i*****~**~***~****~*~***~lt*~*~ ***~*

X~EP ~9CT:PORTA, PORTB, DDRA, TMPTIM, PI R8CT
XREF ~SCT:FLS~TM,TTIME,TCR,~DSCR,TESTYP,LEDS,FLAS~
XREY BSCT:TSTAT,STPT~I, STPTLO, PPNUM, PORTC,TSR
XREF BSCT:ADDR,TESTNM,ANSWLO,ANSW~I,UPIRl,UPIR2 XREF B5CT:~PIRl,LPIR2,STATE,OCRL,ICRL,FAILl,ERCODE
XREF BSCT:TRBSTA,TROU~
XREF PSCT:BASELN,~CXGND,COP,INIT,STINVK
XREF BscT:DELAy~LEDaIv XDEF CHKPWR,RESTOR,TMPCMP
CHKP~R: LDA #$23 STA ADSCR * A/D on, chan 3 sele~ted (p.~.~
LRCLR 7,TESTYP,PWRSP * If on go~ng leave LEDS alone ~:113~

PATENT

BRA PSLED ~ El3e drive LED3 PSFAIL:
BRSET 7,TESTYP,PSEPR ~ If fail PU ST drive LED3 :
BRSET 7,FAILl,PSTRBL ~ 2nd error d~p LEDs keep testing ~S~T 7,FAIL1 ~ 1st time Go into suspect mode BRA CHKWAV ~ do rest of On Going Test *****~**~ *~*~*~*~**~**~rf*~*~*~***~*~clt~*~**~***
PSTRBL: BFSET 2,TESTYP,PSERR * ONLY PULSE TROUBLE ONCE
~ BUT LOOP ON E~ROR
BSET 6,TROUB ~ DRIVE TROURLE FATAL ERRO~ . -BSET 3,PORTA .:
**~*~*l~*~**~*lll~*~*~ ~/r~*****lt*bb*lr*~**b* h*-lr~lr PSEPR: ~SET 2,TESTY * Indicate ha3 failed twice LDA ~$24 STA ERCODE * Store PS error clear others PS~ED: LDX #$24 JSR LEDRIV * Don't Rave if already have it Put out proper code Disable ext * interrrupt PWRSP: LDA #$8C ~ 2.75 Volts ~:
STA STPTHI * Store upper Setpoint (PS) - .
LDA #$73 * 2.25 volt8 STA STPTLO ~ Store lower Setpoint ~PS) :~:
LDA #02 * Default to On Going STA TESTMM * Call PS Routine only twice BCLR 7,TSTAT ~ Default to test pas3 JSR BASELN
BRSET 7,TSTAT,PSFAIL * ~ail Loop BRCLR 2,TESTYP,CLRPSl ~ If had failed restart self test JMP INIT ~ else continu2 ~FATAL Error) CLRPS1: ~CLR 7,FAILl ~ Else clear fail once error C~KWAV:
~RCLR 7,TESTYP,WAVSP ~ Leave LED~ alone if On Going ~ Put out proper code on LEDs UWFAIL: LDX #$26 ~ Put out toggle ~SR LEDRIV ~ Disable irq if pu ~ Toggle only one LED
WAVSP: LDA #$21 ST~ ADSCR * Select uWave A~D in LDA #$7~ ~ Upper Setpoint i~ 2.46 V
STA STPTHI ~ Baseline below 3.75 Volts?
LDA #$56 ~ Lower Setpoint i3 1.6~ V
ST~ STPTLO
BCLR 7,TSTAT * Default to pas~ed test LDA #02 ~ Default to On Going STA TESTNM ~ Call it only twice JSR i3ASELN ~ go average - 2~31~2~

PATENT

~RCLR 7,TSTAT,UWVSUP * Check to see if pass or fail ~ Go to next test if pa3s CMP STPTHI ~ Result is in accum BCC UWHFAL ~ High is an instant failure ~ must be low check lf comparitor BRCLR 2,PORTC,UWVSUP ~ low than ignor el~e indicate err uhnlFAL: BRSET 7,TESTYP,WAVSP ~ Loop if PU Self Te~t BRSET 6,FAIL1,UWlERR ~ ALREADY HAD ONE ERROR NOW
BSET 6,FAII,l ~ ~IRST TIME ERROR
URA SUPWAV ~ GO TO NEXT TEST
UWlERR: LDX ~$26 STX ERCODE ~ STORE UWAVE ERROR CLEAR OTHERS
BSET 0,TESTYP ~ ~et single tec bit PIR
BSET 0,TSTAT
~ Put out proper code on LED3 NOUWTB: BRA SUPWAV ~ and drive new LED code UWVSUP: UCLR 6,EAIL1 ~ PASSED C~EAR SUSPECT MODE
BCLR 0,TSTAT ~ Clear ST PIR BIT
BRSET 2,TSTAT,NOWAV ~ If P uWa~e error ~kip el~a BCLR 0,TESTYP ~ Clear Single Tec uWave NOWAV:
JSR RESTOR ~ Clear LEDs iP no other errors SUPWAV: BRCLR 7,TESTYP,SLOOP * Leav~ LFD~ alone if On Going ~ Put out proper code LDX #$2~ ~ Toqgle two LEDs & T Relay JSR LEDRIV
DOOVER: ~SR DFLAY ~ SETTBE OUT USE X HIT DOG
LDA #515 ~ START TEST TIMER
STA TTIME
SLOOP: BRCLR 7,PORTA,SUPTR~
LCLR 5,FAILl BCLR 2,TST~T ~ CL~AR uWave Pul~e error BRS~T 0,TSTAT,CKTTYP ~ IF Don't H~V~ ANOTHER UWAVE
BCLR 0,TESTYP * CLXAR STPIR ELSE LEAVE ALONE
CKTTYP, BRCLR 7,TESTYP,CXSTAT ~ On going get out JSR STINVK ~ check command i~put ~ STINVX
LDA TTIME ~ PU do t~ll time up ~N~ SLOOP
8RA CRST~T
SUPTR~: LXSET 7,TBSTYP,DOOV~R ~ PU RESET 5T TIM~
BRCLR 5,FAILl,CXSTAT
BSLT 0, TESTYP . ~ set to ~i~gle tec PIR bi~
BSET 2,TSTAT
PULUWR: LDX #$2~ ~ set error code STX ERCODE
CKSTAT: JSR RESTOR ~ Clear L~D3 if no other error RPSTAT: LDA #$20 STA ADSCR ~ Salect PIR A/D 1 2 ~

PATENT
-~8-BRCLR 7,TESTYP,HITIT * Leave BEDs alone if On Going LDA ~$15 STA TIME * Set Up U~er Interface Time LDX ~S2A ~ Dr~ve LEDs ~SR LEDRIV
HITIT: ~SET 7,PORTB * Drive amplifier CLR PPNUM ~ Fir~t Pa~3 at PPIR
~EADPL: BDX #$32 ~ X with 50 ~9R DELAY * (about a 40 mSea Delay) 0 CONTPP: CLR ANSWLO
CLR ~NSWHl LDX #04 LOWSAP: BCLR 7,ADSCR ~ Start conv~rsion README: BRCLR 7,ADSCR,README
LDA ADDR * Read A/D clear flag ADD A~7SWLO
STA ANSWLO ~ Add to previou~ byte CLRA
ADC ANSWHI ~ Propagate carry 2 0 STA ~;JSWHl DECX 't Add four 3ample3 BNE README
LDA ANSWLO
LSR ANSWHI * divide by four RORA
LSR ANSWHl RORA
BRCLR 7,PPNUM,PLOW * I~ low o~e go to it CMF #$4D ~ c 1.509 Volt3 BCC PFAIL
BCLR 4,FAIL1 * ~lear any old failure BRCLR 3,TSTAT,NOCLR
BC~R 3,TSTAT * CLEAR PIR Pulse error BRCLR 1,TSTAT,CKCODE ~ I~ had ba~eline erro~ leave ~CLR 1,TESTYP ~ ST bit alone else clear it CXCODE:
JSR RESTOR ~ Clear LEDs if no other errors NOCLR: BRCLR 7,TESTYP,PIRBAS ~ ON GOING Don't Wait LRA WAIT ~ PU Wait then Go Check Baseline PLOW:
CMP #$B2 * ~3 49 !3CC TLOW * Pas~ed go toggle low PPAIL: BCLR 7,PORTB * if l~t half clear t~y again if ~econd ~ already cleared bu~ don't care JSR DELAY
BR9ET 7,TESTYP,HITIT * PU GO BACX
BRSET 4,FAILl,DECLR * ALREADY HAD A FAILURE
BSET 4,FAILl ~ INDICATE FAILURE
BRA WAIT
DECLR:
BSET 3,TSTAT ~ set failure bit NOPPTB: BSET 1 ,TESTYP ~ Set Single Tec uWave BCLR 7,PORTB ~ return to low ~13~

PATENT

LDX #$2A ~ STORE ERROR CODE
STX ERCODE
CL~X ~ Delay 200 mili second~
JSR DELAY
BR~ PIRBAS b On Going go read baselin TLOW: CLRX * set up approx 400 milisec delay ~SR DELAY ~ plu8 the 40 mSec delay above JSR DELAY
JSR DELAY
~CLR 7,FORTB b Drive Port ~ bit 7 low BSET 7,PFNUM ~ Second Pass through PPIR Loop BRA READPL ~ Toggle Port High WAIT: ~SR STINVK * KICK DOG
LDA TTIME b Wait some time befor continuing BNE WAIT
PIR~AS:
CL~X ~ Delay 400 mSeconds JSR DELAY
JSR DELAY
BRCI,R 7,TESTYP,PIRSP ~ Leave LED~ alone if on Going LDX #$2C * Toggle only one LED ~ T Relay JSR LEDRIV
PIRSP: LDA #$03 STA PIR~CT
AAGAI~: LDA #$8C ~ Upper Setpolnt i 2.75V
STA STPT~I
LDA #$73 STA STPTLO ~ Lower Setpoint is 2.25 V
BCLR 7, TSTAT
LD~ #02 ~ Default to On Going STA TESTNM * Call it only twice JSR BASELN * go average ~RCLR 7,TSTAT,ENDPIR ~ Check to Ree if paRs or fail * Go to end of PI~ if pass DEC PIRBCT
BNE AAGAIN
BRS~T 3,FAILl,BFAIL * FAILED BEFOR~ D~CLARE ERROR
~R9ET 7,TESTYP,PIRSP ~ PU C0NTINUE TESTING
BSET 3,FAILl BRA TMPCMP
~FAIL: BSET l,TESTYP * Set si~gle tec uWave bit BSET 1,TSTAT ~ Indicate type of failure NOPBTB: LDX #$2C ~ STORE THE ERROR CODE
STX ERCODE
LR~ TMPCMP * Don't Resto~e ~ince in failure SNDPIR: BCLR 1 ,TSTAT * CLEAR PIR Ba~eline error BCLR 3,FAlLl ~ CLEAR FAILURE ERROR
~RSET 3,TST~T,C~LEDS ~ If PIR Baseline er~or BCLR 1,TESTY~ ~ leave STuWAVE alone elae clear it CKLEDS:
JSR RESTOR ~ Clear LED~ if no other errors 2~:~3~2~

PATENT

TMPCMP: LDA #$22 STA ADSCR ~ Select Temp Comp A~D in DRCI.R 7,TESTYP,TMPSP ~ Leave LED~ alo~e i~ On Goi~g BRSET 7,TMFTIM,TMPSP ~ leave LEDs a~one if Temp Comp LDX #$2E ~ Put out prop-~r code Toggle uWave & PIR LEDs ~ T Relay ~SR BEDRIV ~ Drive LEDs TMF5P: LDA #$E1 ~ Upper boundry i~ 4.3 V
STA STPTHI
LDA #$2A
STA STPTLO * Lower ~oundry is .85 V
BCLR 7,TSTAT
LDA #02 * Default to On Going STA T~5TNM ~ Call it only twice ~SR BASELN * go average BRCLR 7,TST~T,TMPPAS ~ Check to see if pass or fail ~ Within bounds go compensate BRgET 7,TESTYP,TMPSP * Loop for PU ST
8RSET 2,FAILl,TMFAIL * Alraady had a ~allure 2 0 i3SET 2, FAlLl ~ S8T SUSPECT MODE
BRA NOTL~D * USE DEFAULT SET YOINTS
TMFAlL: BSET 3,TESTYP ~ Indicate on LEDs error BSET 4,TSTAT
LDA TESTYP ~ Low priority error don't AND #$03 ~ drive if other errors exist BN3 NOTLED ~ El~e * Indicate Trouble LDX #$2E ~ Save previous status STX ERCODE
NOTLED: LDA #$99 ~ Default to 3.0V
~DX #$66 ~ Default to 2.0V
BRA DONETC ~ Store ~ monitor TMPPAS: BCLR 2,FAIL1 ~ Passed clear any suspect mode T~MPIT: ~3CLR 4, TSTAT
BRCLR 3,TESTYP,CONTMP
BCLR 3,T~STYP ~ Clear Temp Comp Error JSR R~STOR * Clear LED~ if no other errors CONTMP: CMP #$8C ~ Check to see if c 8C
BCC HIG~ER ~ ~ 8C BRANCH
CMP #$7C
BCC C~KNXT * ~ 7C 8RAWCH
CMP #$73 ~CS LOWEST * < 73 BRANCH
LDA #$9B * 3.05 V
LDX #$63 ~ 1.95 V 73 cDATA c7C (22-2~ Deg C) ~RA DONETC
LOWEST: LDA #$9E ~ 3.1 V c73 (c22 D~g C) LDX #$61 ~ 1.9 BRA DONETC
CHKNXT: CMP #~84 ~CC MIDDL~ ~ ~ 84 BRANCH
LDA #$99 ~ 3.0 V 7C cDATA c84 (24 to 27 C) . ~ . :

2~1302~

hDX #$66 ~ 2.0 V
~RA DONETC ~ Go write the ~etpoint~
MIDDLE: LDA #$96 * 2.94 V 94 ~DATA ~8C l27 to 29 C~
hDX #$68 ~ 2.04 V
BRA DONFTC ~ Go write the setpoint3 HlGHER: CMP #$9C
BCC MORE~I * ~ 9C BRANCH
CMP #$95 8CS NTSO~I * ~ 95 BR~NCH
LDA #$3E ~ 2.7~ V 95 cDATA ~9C (34 to 37 C) LDX #$71 ~ 2.216 V
BRA DON~TC
SOHI: LDA #$~F ~ 2.804 V 8C ~DATA ~95 ~29 to 34 C) LDX #$70 ~ 2.196 V
lS BRA DONETC
MOREHI: CMP ~$AB
BCC HlGH5T
LDA #$94 ~ 2.9 V 9C ~DATA ~AB ~37 to ~0 C) LDX #$6B ~ 2.l V
BRA DONETC ~ Go write the setpoints HIGHST: LDA ~$96 ~ 2.95 ~ AB (~40 Degree~ C) LDX #$69 * 2.156 DONETC: STA UPIRl . ~ Upper Setpoint l STA UPIR2 ~ Upper Setpoint 2 CMP UPIRl BEQ OXl RFAIL: JMP INIT
OKl: CMP UPIR2 BNE RFAIL
STX LPIRl * Lower Se~point l STX LPIR2 ~ Lower Setpoint 2 CPX LPIRl BNE RFAIL

BNE RFAIL
BCLR 7,TESTYP ~ Clear PU ST St~tu~
LDA #$20 STA ADSCR ~ Select PIR A/D in LDA TESTYP
BEQ GOMON * No error restore AND #$03 CMP #$03 * Dual Tec F~ilure ~E LEDERR ~ Not dual error but have error * ~NE GOMON ~ No continue LDX #$30 ~ P~r IN ERROR CODE
STX ERCOnE
LEDER~:
B~9ET 7,TR~STA,NOSTTB
BSET 7,TRBSTA
BSET 6,TROUB

O ~

BSET 3,PORTA
NOSTTB: LDX ERCODE
JSR LEDRIV
BSET 5, TESTYP * HAVE ERROR DRIVE ST DIPLAY
CPX #$31 * had incre~ented ln subro~tine BNE GOMON * GPt out of st ie ~ingle tec JMP CHKPWR * Loop on S~lf Test GOMON: JSR RESTOR * ClearY LEDs iP no problem BCLR 5,STATE ~ Done with On Going BCLR 7,TMPTIM ~ Clear Temp Co~p Var LDA TSR
LDA ICRL
LDA #$Al STA TCR * Enable Input Capture ***b***~*~**~*****~**~********~*~**b~***~***b**~bb***~*
TST TROUB * DON'T CLEAR IF PULSING FOR
BNE TO8KGN * ANOTHER TEST
BCLR 3,PORTA b CLEAR TROUi3LE DONE WIT~ TEST
*~*******~*~*~****~*~***~**~*b*~*~*~*~*~ b*b*****~**~*~
TOaRGN: JMP BC~GND
RESTOR: LDA TESTYP
AND #$0F
BNE KEEP
BCLR 5,TESTYP ~ CLE~R LED DISPLAY
~*~ *
9CLR 7,TRBSTA ~ CLEAR TRO~BLE PULSE LATCH
*~b**~**~*~*~*~******~*~*b~ *~******~**~*~4*~*~
BRSET l,STATE,R~EP ~ If trouble kePp LED~
LRSET 0,STATE,KEEP
~**~ b*~*~*~**~**~****~*~***~ **~******~****~
CLR LEDS
LDA #$08 ~ PRESERVE TROUBLE STATE
AND POR$A
STA PORTA
CLR FLASH
KEEP: RTS
END

~*~********11~*~*~ ****~ ***********~***~-h*~'*******~***
* As~umes A/D i~ Set Up, Csmparison Values ar~ 3et up *
* Number of Reps i-q Set Up, LED code3 are set up ~la3h * U~ed in con~unction wlth the Averaging routlne to *
* sample a sel~ test node via the A/D many times and take *
* the average of the result. Thi8 re~ult is then *
* compared and a pasY or fail flag pa~s~d on to ChXpwr *
~**~*~*~**~*~****~*******~**********~*t~****~*~***~**
XREF ~SCT:AN';WLO,ANSWHI,TESTYP,FLSHTM,LFDS

~` 2~ 30~

PATENT

XREF BSCT:TESTNM,AVELoW,TSTAT,STPTLo,STPTHI
XREF PSCT:AVER
XDEF BASELN
BAS~LN:
CLR ANSWLo ~ Initialize an~wer var~
CLR ANSW~I
BRCLR 7,TESTYP,ONGO ~ Chec~ Test Type * On ~oiDg Test (no LEDs) LDA #$04 ~ PU Test, run AV~R 4 time~
STA TESTNM
ONGO:
JSR AVER ~ Read A/D and average ~DA AVELOW * Get rqsult ADD ANSWLO ~ Add it to final avsrage STA ANSWLO
CLRA
ADC ANSWHI ~ Propagate the c~rry STA ANSWHI
DEC T~.gTNM b Check to seo if need to BNE ONGO ~ go run the average routine again LSR ANSWHI * Else divide hy two ROR ANSWLO
BRCLR 7,TESTYP,COMPAR * Check to see if PU or On Going LSR ANSWHI * I~ PU divide by 4 ~OR ANSWLO
COMPA~:
LDA ANSWLO * Get the average result CMP STPT~I * Compare it with High Setpoint ~CS CHKLSP * If OK go check lower Setpoint SPFAIL
~SET 7,TSTAT ~ Indicate test failure BRA OVER
C}~KLSP
CMP STPTLO * Compare it with lower setpoint BCS SPFAI~ ~ had a lower failuxe ~CLR 7,TSTAT ~ indicate pas~ed test OV~R R~S ~ return from ~ubroutine end ~*~**~*~*****~*~***~**b***~*~***~ *~*t*A~**~*~
* Averaging Routine * Used ln Power Supply, ~icrowave, PI~ (and Thermister) *
bas~ lin2 averaging. Require~ that the A/D mux already be pointing at the c~rrect channel, Returns the average~ ~
* valu~ as an 8 bit number in memory locatlon AVELOW *
* 256 values are summed and averaged. These 256 averages are summed and averaged them3elves to yield a total of ~ i 65536 su~mations and a divide by 65536. The routine ~ . -* takes approx. 1.37 second3. It i9 called four times for *
~ eaah baseline ave~rage on power up and user invoked, it i9 ~ called only once for the P.S. te~t in "On Going" and -~ 2~ 3~2~

PATENI' twice for the uWave and PIR baseline te~ts in "On Going". *
*~r~*******l~***~t*f~ *~tlr~i~*~*Jr~*~*Jrh*t~**~r~*~*b*~*~*
XREF BSCT:ADSCR,AVELOW,AVEHIGH,AVEC ~ ,INTERL,INTRRH
XREF BSCT:PORTD,ADDR
XREF PSCT:STINVX
XDEF AVER
~VER: ~CLR 7,ADSCR ~ Start A/r CL~ AVELOW * Inlt Vars CLR AVEHIGH

CLR INTERL
CLR INTERH
SAMSUM: CLRX b Zero intermediate counter STATUS: ~SR STINVR ~ ~ead User Invoke Self Test b and Command Input, kick dog BRCLR 7,ADSCR,STATUS ~ Raad Conversion Complete Flag BCLR 7,ADSC~ * Re-Start the A/D
LDA ADDR * Read A/D
ADD INTERL * Add it to intermediate ~low byte) STA IN~ERH * Store it back C~RA
ADC INTERL A Add carry to high intermediate byte STA INTER~
INCX
PNE STATUS * ADD 256 COUNTS
A~ERl: L9B INTER ~ Devide by 256 (shifT right 8 times) ROR INTERL * High byte then low byte INCX
CPX #8 ~LO AVERl ADD AVBLOW ~ Take this average add it to outer loop STA AVELOW ~ average CLRA
ADC AVEHI~H * Propagate carry up to high byte ST~ AVE~IGH
INC AVECNT
BNE SAMSUM ~ Check if 256 summations have occured DEVIDE: LSR AVEHIGH * If 80 divide by 256 ROR AVELOW
DECX
BNE DEVIDE
RT~
END

b*~bbb~b~tr*~ rb**~rlr*~* ~:*b~l~lr~r*trl~ r*lr*~*~*lrb~r * This Backgrou~d Routine contains the core of *
* of the alarm ~ignal proce~ing and the INFORMER

2~1 ~392'~

PATENT

* This routine works with the Real Time Interrupt *
* routine ~Timer) a~d the IRQ interrupt routine lt to determine timing, microwaves, microwave t * supervision. Both Dual Tec and Single Tec alarm ~ procejsing are performed in thi~ routine * *
*t~t~tt A t~ *f **~ * Ir~ ~*ttitt~* ~* ~*t~*~ ~t~ttt~* ** ~*~******~**~ ~**~ ~*~lr~* lr* ~1~
XREF PSCT: COP,C'HKPWR,INIT,RESTOR,5MPCMP,STINVK
XREF LSCT:5TATB,PORTD,TESTYP,ADSCR,AD~R,ALRMCT
XREF BSCT:PIRCNT,NEGTHS,ATIMER,1EDS,FLA~H,POSTHS
XREF ~SCT:PORTA,UWAVNF,LPIRl,LPIR2,UPIRl,UPIR2 XREF BSCT:TCR,UWAVE,ICRL,TSR,PORT~,PIRHIC,STA2C
XREF ~SCT:UWAVC,PIRLOC,STACNT,TSTAT,POLAR,TMPTIM
XREF BSCT:NEGINF,DELTIM,FAILl,DELTA,RES8,RESCTH
XREF BSCT:STIMM,STIMH,TROUB,TRBSTA
XREF ~SCT:DELAY
XDEF ~CKGND
BCKGND: JSR STINVK * check st kick dog BRCLR 7,TMPTIM,CKSTPY lt Time to Temp Comp JMP TMPCMP * Yes go do it.
CKSTPY: BRCLR O,TESTYP,CONTIN
JMP STPIR * Check ~ Si~gle Tec PIR
CONTIN: LDA TSR ~ Make sure clear Plag LDA ICRL * Before enable int else LDA #$AO * it will inter~upt 9TA TCR tt Enabl~ Input Capture BRCLR l,TESTYP,RDPIR ~ Check if aingle Tec uWave JMP UWAVl * Go proce~s 3i~gle Tec Alarms RDPIR: JSR RDATOD * read A/D twice return average JSR PIRCB~ tt Per~orm PIR Alarm Cor~parison BRCLR 3,STATE,GTPIRIN
JMP STATEl GTPIRN: TST NEGINF * See if negative threshold BEQ CKUWA * If zero alone JSR PIRINF * El~e check PIR informer CKUWA: BRSET 7,UWAVE,PRCSUW
JMP CXST ~ LONG JUMP NO UWAVE
PRCSUW: BSET O,ATIMER ~ PROCESS UWAVE
CLR UWAVE * Clear flag LDA ATIMER * See ifa PIR i9 occurring too AND #So6 BEQ CXUWST * No continue with informer BS~T 3,STATE * Had a uWave and PIR - State l JMP STATEl CKUWST: BRCLR O,STATE,CLPIRN
BCLR 0, STATE
CLR FhASH * clear fla~h codes CLR LEDS
ltt~*t**tttt*t~**~*tr*~*t~*~trtrt*~rlr*b**~***~r~*t~**t~*~*****~tr*t~t~t~tr~*~*
BCLR 6, TRB5TA ~ CLEAR IUFORMER TROUB LATCH
*~*lt*t~t~tt*ttr~ ~tl*tt**~trlt***~r***tt~rt~***trt~11r~1r*t~r***t***~ t*~tt:lr 2 ~ ~l 3 02 '~

CLPIRN: CLR PIRCNT ~ Had ~ uWave clear PI~
CLR NE~INF
~CLR l,FAILl LDA #$86 AND ATIMER
~N~ NOLDS * leave LEDs alone if in alarm TST TESTYP * Or if self test error fiNE NOLDS
LDA #$02 AND PORTA
STA PORTA
NOLDS: ~RSET 6,5TATE,CNTWAV * R~S don't inc informer LDA UWAVNF * get informer AND #$07 * subtract eight TAX * transfer to index reg LDA DELTIM * Get timer STA R~SB,X * store it in array CLR DELTIM * Rezero it INC UWAVNF * increment uWave informer LDX #$07 * check if had 3 u9e X for index too CPX UWAVNF * leave if not else ~CC CNTWAV * add up last a delta times CL~A
ADDTIM: ADD R~S3,X
BC5 ~WAV16 * if kime ~ 70 ~ec leave RESADD: DEX ~ Add all eight BPL ADDTIM
8SET 6, STATE ~ no carry hence ~ 70 3et RES
UWAV16: LDA #$0F
3 a CMP UWAVNF
BCC CNTWAV
STA UWAVNF * Keep count at 16 **~*~***********~**~**~***~**~*~*~**~****~**t****~***~**~*
BSET 1,STATE * Trouble uWave * comment out for GTEM
~******~****b~******~**~*********~*~*******~******~*****~***~*
JSR CLERCT ~ Clear other countera BCLR 3,TESTYP * Clear low priority temp comp BCLR 4, TSTAT * error if existq LDA #$06 * Put out error Code STA FLASH
STA LEDS
~****~i*~*~**~****~*~********~*~*~****~****~******~*b******
~RSET 6,TRBSTA,NOUWTR
~SET 6'TRBSTA * S~T FLAa FOR DRIVI~G TROUBLE
BS~T 5"~ROUB * Drive Trouble ~SET 3,PORTA * for 4 seconds **~*~***~ ****~ **f*~ **~****~ ****~ *'~ *****~'*~ ****~

NOUWTR: BRSET 0,FAILl,CNTWAV ~ Already in 3hort st mode BSET 5,STATE ~ do a self test BSE~ 0,FAIL1 b put in short ~elf test mode CLR STIMM * clear signi~lcant st counters 2~.~302~

-~7-CLR STEMH
CNTWAV:
LDA TSR ~ Clear any ~lag LDA ICRL
BSET 7,TCR * Re-snable IC Irlt~rrupt CXST: JSR STINVK ~ Check for ST or CI
*~*~**~**tDon't ST if pending~*~***~*~**~*~
LDA STATE ~ DON'T ST or temp comp if AND #$90 * pending alarm BNE GOTOAD
.8RCLR 7,TMPTIM,ONGOTM * time to tmp comp~
JMP TMPCMP ~ ye~
ONGOTM: BRCLR 5,STATE,GOTOAD ~ No Self Te~t Continue BCLR 7,TC% ~ DISABLE IC
lS ~MP CHKPWR
GOTOhD: JMP BCKGND ~ long ~ump to rdpir ~**~****~*~**~*~*SINGLE TEC PIR~***~*~*~***~***~***~*~
STPIR: CLR POLAR ~ Clear reference to polarity CLR POST~S b First threshold crossing moves C1R NEGTHS ~ unit into state l ~CLR 7,TCR ~ Disable uWave interrupt~
JSR STENVK ~ Kick Dog during wait period LDA #$86 * let the timers time out AND ATIMER
BNE STPIR ~ Don't continue until they have STST: JSR STINVK ~ Check if ST or CI active BRCLR 5,STATE,CSTPIR * No On Going continue ST PIR
~MP CHKPWR ~ ST int ~ tmp in single tec don't tc :
CSTPI~: JSR RDATOD ~ read A/D .
~SR PIRCHK * go compare LDA ATIMER
AND #$06 * no alarm stay in state un~il self test ~EQ STST
- ~ had an alarm go on t~ state l now *~**~**~*~***~*****b*~ ****~*~**~***~***~***~*
STAT~l. BCLR 7,TCR * Disable uWave interrupts ~ for the duration of S~ate l CLR PIRCNT ~ clear PIR INEORMER
CLR NEGINF
BSET 3,ATIMER
STAlAD: BRSET l,PORTA,CKSlPI ~ If uWave LE~ is out BCLR 0,ATIMER * clear rest of timer CLR UWAVC
CKSlPI: BRS2T 0,PORTA,CKSTST ~ If PIR LED is out BCLR l,ATIM~ * Clear rest of timer BCLR 2,ATIMER ~ else wait until LED i8 out CLR PIRHIC
CLR PIRLOC
CKSTST: JSR STINVR
BRSET 3,ATIMER,RDSlAD
LDA #$~0 ~ Timed out restart AND STATE
STA STATE

~1~3(~2~,~

PATENT
-4û-LDA #$~7 AND ATIMER
STA ATIMER
JMP BCKGND ~ Time out start over RDSlAD: JSR PDATOD * Read PIR A/D
TAX b SAVE COPY FOR HYSTERESIS PROCESS
CMP UPIRl ~ Compare it with upper threshold BCS HADPOS ~ le39 than -~ go see if had one before?
BRSET 7, POL~R,CKPTHS ~ i9 greater, had one before?
BSET 7,POLAR ~ No Set Po~itive Polar BCLR 1,POLAR ~ Clear Pos Out of Threshold LDA #~30 b Set up counter STA POST~S
CLR PIEHIC ~ drive LED
BSET 1,ATIMER
LSET 0,PORTA
BRA STAlAD * Go try a~ain CKPTHS: BRCLR 1,POLAR,STAlAD * yes but not out of pos thrs ~SET l,ATIMER ~ WATCH OUT SIMULTANEOUS TEARS
BRA MVST2 ~ HAD ONE,OUT OF THRS,PUL CNT 2 HBADPO9: BRCLR 7,POLAR,CKNGTS * No previous positive ADD #$03 * 60 mVOLTS ~rYSTERESIS
CMP UPIR1 ~ DONT DEC IF VALUE IS HIGHER
BCC STAlAD * AFTER ADDING 60 mVolts D~C P05THS * ~ad previous positive dec counter BNE CKNG~S ~ didn't count out go check neg BSET 1,POLAR ~ Cou~ted out set Po~ Out of Thre~
CKNGTS: TXA ~ RETRI~VE COPY IF NEEDED FROM HYSTERIS
CMP LPIR1 ~ Check lf less than neg thrs BCC HADNEG ~ Go s~e if had neg BRCLR 6,POLAR,SETNEG ~ No neg go set lt BRCLR 0,POLAR,STAlAD ~ Not out of ~eg thre h BSET 2,ATIMER ~ WATCH OVT SIMULTANEOUS TIMERS
BRA MVST2 * qualified go to ~tate 2 SETNEG: BSET 6,POLAR ~ Set neg polar flag BCLR 0,POLAR * clear neg out of thres flag LDA #$30 STA NEGTHS
CLR PIRLOC ~ Dr~ve LED
BSET 2,ATIMER
BSET 0,PORTA
SlHOP: 8RA STAlAD
HEADNEG: BRCL~ 6,POLAR,STAlAD * Never had neg go back sva #$03 ~ DON'T DEC~EMENT COUNTER IE AFTER
CMP LPIR1 ~ SUBTRACTING 60 mVolts it is les~
BCS STAlAD ~ than setpoint make come up more D~C NEGTHS ~ D~crement negative threshold counter BNE SlHOP
BS~T 0,POLAR ~ Set Out of Neg Thr~hold flag 8RA SlHOP ~ Go do it again MVST2: LDA #$P0 2~13~2~

PAT~NT

A2~D STATE
STA STATE
BSET 0,PORTA
CLR POLAR
~RSET 0,T~SrYP,STPALM ~ If single tec PIR go alarm BSET 4,STATE
BSET 4,ATIMER
hDA TSR
LDA ICRL
LDA #SAl STA TCR ~ Enable Input Capture S~AT~2: JsR STINV~ * Read Sel~ Tese, Kick Dog BRSET 4,ATIMER,RDS2UW
BCLR 3,ATIMER ~ CLEAR STATE 1 TIME~
CLR STACNT
CLR POLAR
LDA #$E0 * Timed out re~tart STA STATE
JMP BCKGND * Time out itart over RDS2UW: ~RCLR 7,UWAVE,STATE2 * Check ~or the confirming uWave BSET 1, PORTA
BS2T 0,ATIMER
gT~WA: CLR UWAVE ~ jump in spot for ~ingle tec uWave STPALM: LDA #~80 STA STATE ~ alarm routine JSR CLERCT ~ CLEAR ALL COUNTERS
CLR POLA~ ~ Clear polariry reference BSET 7,ATIMER
BSET 2,PORTA ~ Drive Alarm BCLR 5,PORT~ ~ Drive Alarm Relay LD~ #$20 * Alarm 4 Second~
STA ALRMCT
JMP BCRGND
~ t~*b~ SINGLE TEC MICROWAV~ *~*
UWAVl:
BRCLR 7,UWAVE,CHEXST ~ HAD A VWAVB
BRSET 0,UW~VE,STUWA ~ Already had one BSET 0,UWAVE ~ No indicate 1 BSET 0,ATIMER ~ ~tart timer ChR UW~C
~CLR 7,UW~VE ~ Clear flag C~EKST: JSR STI~nJK ~ Check ~or CI or UI
CKOG: LDA TSR ~ Clear any flag LDA ICRL
~SET 7,TCa * Re-enable IC Interrupt ~RS3T 0,ATIMER,UWAVl ~ DON'T ST IF pending alarm BCLR 0,UWAVE ~ Timed out clear count BRCLR 5,STA~E,UWAVI ~ No Sel Te~t Continue BcLa 7,TCR ~ Disable input capture :

21~30 JMP CHKPWR * st interval ~ tc t tc n/a *~******~**~ *~*~**~*~**~*~*****~*~*~*~**~*~*~****~*
PIRCHK: LDX UPIRl * Compare Upper 5etpoint~ with self BNE SPFAIL
CPX LPIR1 * Make sure Lo~er Setpoint i~ lower ~CS SPEAlL

CPX LPIRl BNE SPFAIL

~CC SPFAIL
TAX ~ SAVE COPY OF A/D SAMPLE

BCC PIRUU~I * High alarm BRCLR 7,POLAR,CKLO ~ No high did we have a high ADD #$03 ~ 60 mVolts hysteresis CMP UPIRl ~ HIGER WHEN ADD 3 BCC PIRRTS ~ YES, LET DROP MOR~ DONT BOTHER

DEC POST~S * NO decrement out of pO9 thres ~3NE CKLO ~ Not out of thres yet BSET 1,POLAR ~ Out of thr~q not out of time C~LO: TXA ~ RETRIEVE COPY IF NEEDED

BCS PIRALO ~ Low alarm BRCLR 6,POLAR,PIRRTS * No low, haven't had onP eithPr SU~ #$03 * 60 mVOLTS ~YS$ERESIS
CMP LPIR1 ~ DONT DECREMENT IF LESS THAN WHEN
~0 BCS PIRRTS ~ 60 mVOLTS ~RE SUBTRACTED
DEC NEGTHS ~ Have had out of thres counter BNZ PIRRTS
BS~T 0,POLAR
BRA PIRRTS ~ Proce~ alarm SPFAIL: RSP * Go to Temp Comp try to recover BCLR 7,TCR ~ Di~able input capture ~JMP TMPCMP
PIRAHI:
CLR PIRHIC
BSET 1,ATIMER ~ Start high thre3hold Timer LDA #$30 * Set Hystere~is Thres to 48 STA POST~S * Po_itive Threshold Counter BSET 7,POLAR b Positive Polarity Signal BRA PIRLED ~ Re~tart counter PI~ALO:
LD~ #~30 STA NEGT~S * Set Hy3teresis Thres to 48 ~ Negative Threshold counter BSET 6,NEGINF * Negative In~ormer counter BSET 6,POL~R ~ Negative Threshold counter CLR PIRLOC

- - \
2~ :~3~2 ~3 PATENT

BSET 2,ATIMER ~ Start A:larm Timer Counter PIRLED: BSET 0,PORTA ~ Drive LED
CLR UWAVNF b ~ad a PIR clear uWave Informer CLR DELTIM ~ Clear Delta Timer CLR DELTA ~ Clear Delta Time Flag BCLR 6,STATE * Clear RES
CLR RESCT~ ~ Clear H:igh byte of RES Counter ~aSET 0,TESTYP,PIRRTS ~ Single Tec PIR leave BRCLR 0,ATIMER,MLEDS ~ r~ no uWave check LED~ .
CLR PIRCNT * else clear PIX Inf.
BSET 3,STATE ~ State 1 had a uWave and PIR
MLEDS:
BRCLR l,STATE,PLED ~ 3k.ip if no microwave in~or~ner BCLR l,STATE * Cle~r uWave Trouble BCLR 0,FAILl * Clear short ST Mode b**~*~ b~b*~**~**~**~h*~b*****~****bb*~b~*~b~*****b*h*
BCLR 6,TRBSTA b CLEAR INFORMER TROUBLE LATCH
****~**~*~****~**~*****~ **~***~**~*~*~**~**b*~
CLR LEDS
CLR FLASH
CLR PORTA
P~ED: BSET 0,PORTA
PIRRTS: aTs PIRINF: BRSET 0,TESTYP,NPIRIC ~ If Single Tec no Informer ~ PIRN: RTS * REMOVE GTEM STATEMENT NO INFORM
DEC NEGINF * Decrement Counter BNE NPIRIC
INC PIRCNT * Increment In~ormer LDA #$0F * Compare Informer Count to 16 CMP PIR~NT ~ I~ 16:1 drive trouble with code BCC NPIRIC
STA PIRCNT ~ ~eep count at 16 JSR CLERCT
BSET 0,STATE * PIR Trouble BCLR 3,TESTYP ~ Clear any temp comp error BCLR 4,TSTAT
LDA #$05 b Put out error Code STA FLASH
STA LEDS
~**~**~****~****b~*~*~**~**~*~*~*b*bb***~*~**~bb~b*~*~*~*
BRSET 6,TRBSTA,NOPRTR
BSET 6,TRBSTA ~ SET YL~G TO PVL9E FOR 4 SECONDS
BSET 5,TROUB * PULSE FOR 4 SECONDS
BSET 3,PORTA
*~b*~b*u*b~b~*b~**~*~*~ b*~*b~*~***~b*~*~*b~ ~****~*~b ~
NOPRTR: BRS~T l,FAILl,NPIRIC ~ If already in short mode skip ~.
8SET 1, FAILl b el~e ~et in short st mod~
8SET 5,STATE ~ do an immediate st CLR STIMM b clear signi~icant 9t counter~
CLR STIMH
NPIRIC: RTS

2~ ~3~2~;

PATENT

CLERCT: CLR ATIMER
Cl.~ PIR11IC
CL~ PIRLOC
CLR ST~CNT

CLR UWAVC
RTS
RDATOD: CLRA
~DX #$02 * Read A/D twice ~ divlde by two BCLR 7,ADSCR * START A/D
AGATOD; ~RCLR 7,ADSCR,AGATOD
ADD ADDR
DEX

RORA
RTS
END

*t******~****~*****~***~******~*~**~ *~****~******~******
* Delay Sub~outine Decrement3 Accumulator by 255 *
* times whatq in the index register. Mu3t lode *
* prior to calling the routine * Do not move this ~outine. t * *
t*~*****~h*~***~***~*~*******~*~**~*b*~*~*b**b*~*b~*~***~

XREF PSCT:COP
ORG $0032 * ZERO PAGE ROM CRUNCH
DE~AY:
Outl: CLR~ ~ A at Zero 3 S~A COP * Rick Dog 5 I~l: DECA * 3 x .5 uSec 256 x 6 =
BNB Inl * 3 x .5 uSec .8 mSec DECX * 3 X .S uSec 3 X x (.8 ~ .007)mSec BNE Outl ~ 3 x .5 uSec 3 RTS ~ Return from subroutlne END

21:~3~2~

PATENT
-53- -.
* * ~ * ~ * ~ ~ ~ ~ * ~ ~ ~ * * 1r ~
h Self Test Invoke Subroutine used for Command Input and user Invoking -- User Invoked performi the ~ame ~ as Command Input but shows (then clears) any ~tored ~ error code first (for 10 seconds) before ~umping to the beginning of self test, Command Input jumps write *
into the begginning o self Test The di3play codes are held in look up tables on zero ~ page ROM starting at location $20 a9 LED code Flash *
~ code. The error code is the actual addres~ of the * LED code to be display~d. The flash code is one above *
~ it. t lr lr ~ ~ b b ~ r * tr l~ lr lr Ir ~ l~ b ~ * ~ * ~ * l~ * ~ ~ * l~ * t~ lr lr ~ h ~
XREF BSCT:TESTYP,ERCODB,TTIME,PORT~,TCR
XREF PSCT:INIT,COP
XREF BSCT:LEDRIV

STINVK: CLRA * kick the dog STA COP
BRSET O,PO~TC,CXCMD t No Vser Invoke check CI
BSET 7,TESTYP ~ Indicate that now in Self Test LDX ERCODE ~ Get the error code BEQ JMTST ~ No error code just do test JSR LEDRIV ~ go put out proper error code LD~ #~15 ~ get the display time STA TTIME
ERWAIT: CLRA
STA COP ~ Hit Dog TST TTIME * wait delay period : :
BNE ERWAIT
SHORT2: STA COP ~ ~it Dog BRSET 0,PORTC,S~ORT2 ~ Now wait for 2nd short to ST
BRA JMTST ~ go run destructive ST
CKCMD: BRSET l,PORTC,RTTST ~ no Command Input return JMT5T: BCLR 7,TCR
SELF: BRA SELF ~ els run detructive ST check Dog RTTST: RTS ~ Return from subroutine END

XREF BSCT:TSTAT,TESTYP,FAlLl,ERCODE,STATE
XREF PSCT:LEDRIV
XDEF IRQ
By the fact that the proces30r is in this routine means there was an error Microwave Supervision Routine ~:
:

3~

IRQ:
BSET s, FAILl ~ had one error indlcate ~t it to Chkpwr routine BSET 5, STATE ~ Do an immediate self te t ~ once return~d to Background RTI
END

XREP PSCT:TIMER, IRQ, lNIT
~ Interrupt and Reset Vectors Al~o ROM Check sum and COP Rege~iter Code VECS:
ORCil $ 0 a PF
FC~ $49 ~ EOR OF ROM
ORG $0900 b M3sk Option Register FCE3 $ 01 ~ Q Edge * COP Disabled ORG $1FF0 FC13 $0 * COP Addras~ i~ $1FF0 FCB 0, 0, 0, 0, 0, 0, 0 ~ 7 zero~ unused area EDB TIME~ ~ Location $1FFB & $1FF9 El)B IRQ * Exter~al Interupt FA F13 FDEl INIT ~ SWI Vector $1FFC & FD
FD13 INIT * Re et Vector Julnp to Init END

The following component values have been found satisfactory for an operative embodiment of the invention. Unless otherwise specified all resistor values are in ohm~, one-tenth watt, i5% tolerance.
Unless otherwise specified all capacitor values are in microfarads, i20% tolerance, 50 working volts DC:

COMPON~NTs Re~erence No 'rype Value or Part 35 _ _ _ _ _ Number 12 microcon~roller MC58HC705P9 capaci~or 100 pF
16 capacitor g70, 25 WVDL

2 ~

18 suppre3qor P6KE20C
diode lN5818 22 voltage s-al2sopG
regulator 2~ resi~tor 3R
24 tran~i~tor 2N6726 ZS zener dlod~ lN5234 26 reYistor 12K
27 capacitor 1000 pF
resi~tor lX
29 capacitor 1000 pF
30,48 operational LM3508 amplifier 32 diode lN914B
34 re~i~tor 3K
38 capacitor 220,25WVDC
39 rasi~tor lK
re~i~tor 11.3K, 1~
42 potentiometer 5K, 20~ -43 capacltor 100 pt 44 resistor 20X, 1~
capacitor 1000 pY
46 resistor lR : - :
49 capacitor .01 ~0 tran~ijtor 2N3904 52 resi~tor 3X
54 resistor 12K
56 resistor lR ~: .
57 capacitor 1000 pF ~ :::
58 capacitor lOO,lOWVDC
62 capacitor .01 :: -66 passive ~eiman infrared LHI 958-3890 detector : -6~ re~istor lR
69 capacitor .01 - ~
re~istor 390 -: : :.:
72,82 operational LM358 :.~
amplifier :: --74 re~istor 47R
76 capacitor 100 pF
78 capacitor 47, 25 ~rvDc re~i~tor 12.1X, l~ :
a8 capacitor lO0 pF ::.
84 resistor 1 Meg, l~
86 capacitor .01 :~
88 re~istor 402R, l~ :
capacitor .027 92 re~i~tor 8.25R, 1%
94 capacitor lO0, 10 WVDC
96 capacitor .01 98 re~i~tor 787K, 1%
lO0 resi~tor 787X, 1%

2:~3~2~

PATENT

102 resistor lK
lo~ capacitor .01 103 resi3tor 1~
los reai3tor lK
S 110 resistor 20K, 1~
112 resistor 43.2K, 1%
113 capacitor 0.1 114 resi~tor lOX, 1 116 resistor lR
118,120, operational LM339 122,176 amplifier LM393 124,260 operational amplifier 12~ LED ~green) 129 resistor 1.2R, 1/8 watt 130 LED (yellow) 131 resistor 1.2R, 1/~ watt 134 LED ~red) 135 reslstor 1. 2K
l3a re~istor llOK, 1/2 watt 140 resistor 1 Meg 142,144 diode3 IN914 148 capacitor 100 pF
l5o capacitor .01 151 re31stor lOX
153 capacitor .01 154 resistor lOK
156 tran~i3tor 2N3904 157 resistor lR, 1/2 watt 159 ~ener diode P6~18A
166 resi tor lK
168 resi~tor lOOK
170 capaci~or l.o 134 r~sistor loX
186 xesistor lOR
18~ resistor lOX
192 resistor lOR
194 translstor 2N3904 196 tran~istor 2N3906 lg7 diode lN914B
200 relay reed 1 amp, 5 volt 500 ~hm coil 204 reqistor 3K
206 xe~istor lOOX
Z0~ zener diode lN5234 214 diode lN914~
216 ~ariitor 30 volt, 0.25 watt 218 ~aristor 30 volt, 0.25 watt 222 resistor lOR
226 translstor 2N3904 22~ .resistor lOK
230 capacitor 100 pP
232 re3~stor loK

2~ 302~j PATEN'I

234 reqistor 511X, 1%
240 reRistor lK
242 capacitor 0.1 244 capacitor .001 250 resi3tor lOR, 1 252 capacitor .001 254 thermistor lOX, 2 256 resistor lX
25a reqistor 2.2 Meg 0 259 capacitor 0.1 261 re3i~tor , lOK
26~ resistor lOK
269 resistor lK
290 r~sistor 10 Meg 2a2 guartz crystal 3.68 MHz 284 capacitor 27 pF
236 capacitor 27 pF
280 capacitor .01 :
289 tran~istor 2N3904 290 re~iqtor lOK -292 capaaitor .01 294,302,308, Schmidt 4584 312,314,316 trigger 2g6 re~i~tor 332K, 1~ -298 resistor 3.9K
300 diode lN914B .
303 capacitor .01 -304 diode lN914B
306 resistor 510 310 capacitor .0022 317 diode lN914B
318 resistor 510 ~ :
319 capacitor .0022 320 capacitor 470 pF
321 resistor lK, 1/8 watt 322 capacitor 100 pF .:~
324 tra~sistor 2N2907A
330 fiald ~f~ect ~SS123 transi~tor 332 re~istor ~OOK, 1 334 resistor 4.49K, l~
336 capac1tor .001 33~ capacitor 0.1, 63 WVDC
340 capacitor lOO pF
342 capacitor 0.1, 63 WVDC
344,360 operational TL082 amplifier 346 aapacitor 2700 pF
348 re3i3tor 825R, 1 350 r~istor 2.21X, l~
352 capacitor 22, 10 WVDC
354 resi~tor 499K, 1 356 resistor lK

--- 2~:l39~

PATENT

358 potentiometer lOK
362 reslstor 220K
365 capacitor 0.1 366 resistor 294K, 1 368 capacitor 3200 pF
370 re3istor 2.21K, 1%
372 capacitor 22, 10 WVDC
374,376 diod~ dual IN914, common anode 378,408 operational LM358 amplifier 380 resistor 20X, 1%
382 resistor 20K, li 384,306 diode dual IN914 common anode 30~ capacitor 47, 16 WVDC
390 capacitor 10, 16 WVDC
392 resistor 2.2 Meg 394 r~sistor 825K, l~
396,406 operational LM393 amplifier 398 transiitor 2N3906 400 resistor 47K
402 resistor lK
410 resistor 20R
412 capacitor 0.1 414 capacitor 0.1 416 capacitor 10, 16 WVDC
418 resi3tor lOOR
~20 resistor 432K, 1 422 resi~tor 432K, 1 424 resiqtor 232K, 1 426 capacitor .01 420 r&sistor lK
430 resi.stor 1 Meg, 1%
432 resistor 1.2 Meg .
434 capacitor .01 436 re~i~tor 1.2 Meg 43~ re3i~tor 2 Meg ~40 capacitor .33 442 capacitor .01 444 re3i~tor lOOK
446 resi~tor 10 Meg 502 Gunn diode Alpha Industries 504 Schottky mixer Alpha Indu~rie~
diode DMF 3475-99 500 re3istor lX

~1~3~

PATENT

It is apparent from the foregoing that a new and improved method and system have been provided for intru~ion detection using multiple types of sensor~.
While only certain preferred embodiments have been S described in detail, as will be apparent to those familiar with the art, certain changes and or modifications can be made without departing from the scope of the invention as defined by the following claims.

Claims (23)

1. An intrusion detection system comprising:
a first detecting means for detecting an intrusion in a volume of space by a first physical phenomenon and for generating a first signal in response to each detection of said intrusion;
a second detecting means for detecting an intrusion in said volume of space by a second physical phenomenon different from the first phenomenon, for generating a second signal in response to the detection of said intrusion; and logic means for generating an alarm signal in response to the occurrence of one first signal in response to one detection and one second signal in response to one detection within a first interval, the occurrence of another first signal within a second interval said second interval subsequent to said first interval, and the occurrence of another second signal in response to another detection within a third interval said third interval subsequent to said second interval.

2. The system of Claim 1 wherein said first detecting means comprises:
a passive infrared detector.

3. The system of Claim 2 wherein said second detecting means comprises:
a microwave detector.

4. The system of Claim 1 wherein said fir t detecting means comprises:
a microwave detector.

5. The system of Claim 4 wherein said second detecting means comprises:
a passive infrared detector.

6. The system of Claim 1 wherein said logic means comprises a microcontroller.

7. The system of Claim 1 wherein said logic means for generating an alarm signal further comprises:
timing means for limiting the duration of said alarm signal.

8. The system of Claim 1 wherein said logic means further generates an alarm signal in response to the failure of said first detecting means and the occurrence of one second signal and the occurrence of another second signal within a fourth interval, said fourth interval commencing upon the occurrence of the earlier of said second signals.

9. The system of Claim 1 wherein said logic means further generates an alarm signal in response to the failure of said second detecting means and the occurrence of one first signal and the occurrence of another first signal within a fourth interval said fourth interval commencing upon the occurrence of the earlier of first signals.

10. A method of detecting an intrusion within a volume of space comprising the steps of:
detecting an intrusion within a volume of space by a first physical phenomenon;
generating a first signal in response to the detection of said intrusion by said first physical phenomenon;

detecting an intrusion within said volume of space by a second physical phenomena, different from the first phenomena;
generating a second signal in response to the detection of said intrusion by said second physical phenomena;
generating an alarm signal in response to the occurrence of one first signal and one second signal within a first interval, the occurrence of another first signal within a second interval said second interval subsequent to said first interval, and the occurrence of another second signal within a third interval said third interval subsequent to said second interval.

11. The method of Claim 10 wherein said first physical phenomena is infrared radiation.

12. The method of Claim 11 wherein said second physical phenomenon is doppler shift microwave radio frequency.

13. The method of Claim 10 wherein said first physical phenomenon is doppler shift.

14. The method of Claim 13 wherein said second physical phenomenon is infrared radiation.

15. The method of Claim 10 further comprising the step of:
limiting the duration of the alarm signal.

16. The method of Claim 10 further comprising the step of:
generating an alarm signal in response to the failure of said first detecting means and the repeated occurrence of said second signal within the first interval.

17. The method of Claim 10 further comprising the step of:
generating an alarm signal in response to the failure of said second detecting means and the repeated occurrence of said first signal within the first interval.

18. An intrusion detection system comprising:
a first sensor for sensing an intrusion in a volume of space by a first physical phenomenon and for generating a first signal in response to the detection of said intrusion;
a second sensor for sensing an intrusion in said volume of space by a second physical phenomenon different from the first phenomenon, for generating a second signal in response to the detection of said intrusion; and a microcontroller for generating an alarm signal in response to the occurrence of one first signal and one second signal within a first interval, the occurrence of another first signal within a second interval said second interval subsequent to said first interval, and the occurrence of another second signal within a third interval said third interval subsequent to said second interval.

19. The system of Claim 18 wherein said first sensor comprises:
a passive infrared detector.

20. The system of Claim 19 wherein said second sensor comprises:
a passive infrared detector.

21. The system of Claim 18 wherein said first sensor comprises:
a microwave detector.

22. The system of Claim 21 wherein said second sensor comprises:
a passive infrared detector.

23. A method of detecting an intrusion within a volume of space comprising the steps of:
detecting an intrusion within a volume of space by a first physical phenomenon;
generating a first signal in response to the detection of said intrusion by said first physical phenomenon;
detecting an intrusion within said volume of space by a second physical phenomena, different from the first phenomena;
generating a second signal in response to the detection of said intrusion by said second physical phenomena;
generating an alarm signal in response to the occurrence of at least one first signal and at least one second signal within a first interval, the occurrence of one of another first signal and another second within a second interval said second interval subsequent to said first interval, and the occurrence of one of another first signal and another second signal within a third interval said third interval subsequent to said second interval.