CN100449948C

CN100449948C - Method and device of ldpc (low density parity check) code signal and checkout decode using parallel and simultaneous

Info

Publication number: CN100449948C
Application number: CNB2005100650528A
Authority: CN
Inventors: 巴中·申; 豪·西恩·特; 凯利·布赖恩·卡梅伦
Original assignee: Zyray Wireless Inc
Current assignee: Broadcom Corp; Zyray Wireless Inc
Priority date: 2004-04-05
Filing date: 2005-04-05
Publication date: 2009-01-07
Anticipated expiration: 2025-04-05
Also published as: CN1691522A

Abstract

LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node processing. This novel approach to decoding of LDPC coded signals may be described as being LDPC bit-check parallel decoding. In some alternative embodiment, the approach to decoding LDPC coded signals may be modified to LDPC symbol-check parallel decoding or LDPC hybrid-check parallel decoding. A novel approach is presented by which the edge messages with respect to the bit nodes and the edge messages with respect to the check nodes may be updated simultaneously and in parallel to one another. Appropriately constructed executing orders direct the sequence of simultaneous operation of updating the edge messages at both nodes types (e.g., edge and check). For various types of LDPC coded signals, including parallel-block LDPC coded signals, this approach can perform decoding processing in almost half of the time as provided by previous decoding approaches.

Description

The method and the device of ldpc coded signal position-verification parallel decoding

Related application

The present invention advocates U.S. Provisional Patent Application 60/559,701 priority, the name of this temporary patent application is called " using the position node and the code check node processing mode of parallel synchronous that low density odd-even check coded signal is decoded " (attorney docket BP3580), and the applying date is on April 5th, 2004.

Technical field

The present invention relates to communication system, more particularly, the present invention relates to the signal decoding in the communication system.

Background technology

For many years, data communication system is in the state of sustainable development always.Wherein, the communication system that has a class of great benefit recently is to use the communication system of turbo coding.What another kind was received benefit equally is the communication system of using LDPC (low-density checksum) coding.In these fields, the initial development direction is wrong flat (the Error floor) that reduces constantly in the communication system.Desirable target is to reach shannon limit in the communication channel (Shannon ' s limit).Shannon limit can be regarded as the data transfer rate that in communication channel, will use, have specific SNR (signal to noise ratio), make to reach the inerrancy transmission in the communication channel.In other words, for given modulation system and encoding rate, shannon limit is the theoretic boundary of channel capacity.

In some cases, the LDPC coding has shown the outstanding coding efficiency near shannon limit.For example, explicit declaration is arranged, the theoretic shannon limit of this LDPC decoder distance is within 0.3dB (decibel) scope.This example is to be that 1,000,000 abnormal LDPC coding obtains by using length, in any case it has proved that the LDPC coding has good application prospects in communication system.

The typical coding of ldpc coded modulation signal is to realize that by the signal that generation has a code element each code element has a public encoding rate and is mapped to independent modulation.That is to say that all code elements of ldpc coded modulation signal all have identical encoding rate and identical modulation (the identical letter group (constellation) with independent mapping).Sometimes, use this design of technology for encoding formerly with maximization this specially designed hardware and treatment effeciency, this is designed for the independent modulation of ldpc coded modulation signal generation has independent encoding rate and to(for) all code elements that wherein produce.

For the coding of this ldpc coded modulation signal, normally carry out based on given ldpc coded modulation signal bipartite graph, this bipartite graph comprises a node and check-node.The I relevant with received signal, Q (homophase, quadrature) value is relevant with symbol node, and this symbol node is relevant with corresponding position node.Then, for the individual bits of respective symbol is calculated the position yardstick, those yardsticks offer the position node of the bipartite graph of given LDPC coding.Calculating is corresponding to the edge messages at position node and edge, check-node commissure place, and suitably upgrades, and during to the ldpc coded signal iterative decoding, communicates by letter back and forth between node on the throne and the check-node.In such decode system, the position scale-value of application is a fixed value, and is re-used in the processing procedure of iteration coding.Therefore, therefore the execution of this technology is formerly limited a unique solution code method, and may require more iteration so that the information that includes in the ldpc coded signal can converge on a best estimate.

And, but the coding/decoding method of these ldpc coded signals generally includes the use concentration treatment upgrades respective edges information, and by this method, all marginal informations relevant with check-node are updated, all then marginal informations relevant with the position node are updated, and carry out repeatedly.From the angle of position node and check-node, this iterative decoding process (as updating edge information) is to carry out back and forth.Can introduce the stand-by period of certain grade by the mode that this coding/decoding method need be carried out, because, all marginal informations relevant with check-node all are updated, then, all are updated with the relevant marginal informations of position node, between position node and check-node constantly alternately, (if necessary) execution continuously.It may cause the processing speed of communication link receiver end (as decoder end) to descend to a certain extent.Thereby, existing all the time in the industry the craving for of a kind of technical scheme, this scheme can be carried out iterative decoding to ldpc coded signal more quickly and efficiently and be handled.

Summary of the invention

With synchronously and parallel mode to carrying out method for updating corresponding to the edge messages of position piece node with corresponding to the edge messages of check block node, can see each feature of the present invention in many equipment that LDPC (low-density checksum) modulation signals is decoded.This coding/decoding method can be described as LDPC position-verification parallel decoding usually and handles.

For example, can in the decoder of carrying out LDPC position-verification parallel decoding, find feature of the present invention.This decoder comprises yardstick (metrics) calculator, symbol node calculator function piece, position node computer functional block, and iterative decoding function blocks.This yardstick calculator can calculate the yardstick of the m bit symbols relevant with the code element (having the m position) of ldpc coded signal.This symbol node calculator function piece can calculate the position yardstick that uses m bit symbols yardstick.Position node computer functional block can be calculated the soft information in m position corresponding to code element.The iterative decoding function blocks can be used the edge messages of soft information initializing corresponding to the minimal set of position piece node, to support position-verification parallel decoding to handle during the decoding iterative operation of the default execution sequence group management of basis subsequently.The iterative decoding function blocks can be upgraded edge messages corresponding to first piece node in very first time section, and this iterative decoding function blocks can be upgraded edge messages corresponding to the first check block node simultaneously in very first time section.Afterwards, this iterative decoding function blocks can be upgraded edge messages corresponding to second piece node in second time period, and this iterative decoding function blocks can be upgraded edge messages corresponding to the second check block node simultaneously in second time period.This edge messages is corresponding with the edge, and this edge will be connected with a plurality of check block node communications ground corresponding to a plurality of piece nodes in the LDPC piece bipartite graph of LDPC coding, and ldpc coded signal produces by this LDPC coding.

In certain embodiments, the iterative decoding function blocks comprises a plurality of engine processors.In this case, can upgrade first edge messages corresponding to first piece node at first engine processor of very first time section, second engine processor can upgrade second edge messages corresponding to first piece node in very first time section.Equally, in certain embodiments, the iterative decoding function blocks comprises a plurality of verification engine processors.In this case, can upgrade first edge messages corresponding to the first check block node at the very first time section first verification engine processor, the second verification engine processor can upgrade second edge messages corresponding to the first check block node in very first time section.

First piece node can comprise the first multidigit node, and second piece joint can comprise the second multidigit node.Similarly, the first check block node can comprise first multiple check-node, and the second check block node can comprise second multiple check-node.

In certain embodiments, decoder can also comprise the first memory that is connected with the communication of iterative decoding function blocks, and the second memory that is connected with the communication of iterative decoding function blocks.When the iterative decoding function blocks when very first time section is upgraded edge messages corresponding to first piece node, the visit first memory; When the iterative decoding function blocks when very first time section is upgraded the edge messages of the corresponding first check block node, can also visit second memory simultaneously.

In some optional embodiment, decoder can also comprise the binary channels memory, and it allows to carry out simultaneously read and write access, and it is connected with the communication of iterative decoding function blocks.When the edge messages upgraded in very first time section corresponding to first piece node, this iterative decoding function blocks can be visited the binary channels memory, and when in very first time section renewal during corresponding to the edge messages of the first check block node, this iterative decoding function blocks also can be visited the binary channels memory.

This iterative decoding function blocks can be exported the soft estimation for the code element position of ldpc coded signal.In some cases, this encoder also comprises a hard limiter, this hard limiter can use the soft estimation of the code element position of ldpc coded signal that the code element position of ldpc coded signal is determined firmly, thereby produces the best estimate to the code word of ldpc coded signal.

In certain embodiments, after the iterative decoding function blocks is carried out last decoding iteration according to predetermined execution sequence group, the iterative decoding function blocks can reorder to any position corresponding to second piece node, and the order of this node may according to predefined a plurality of execution sequences variation take place.Should allow this iterative decoding function blocks to export the soft estimation of the code element position of ldpc coded signal corresponding to reordering of second piece node position according to an order, in this order, the information bit into ldpc coded signal that is encoded at first.

At some among other the embodiment, after the iterative decoding function blocks is carried out final decoding iteration according to predetermined execution sequence group, the iterative decoding function blocks can be carried out an extra decoding iteration and control without execution sequence, so naturally to may resequence with any position that has taken place according to predefined execution sequence group to change corresponding to second piece node.Similar in appearance to aforesaid, should allow this iterative decoding function blocks to export the soft estimation of the code element position of ldpc coded signal corresponding to reordering of second piece node position according to an order, in this order, the information bit into ldpc coded signal that is encoded at first.

In certain embodiments, use LDPC position-verification parallel decoding processing method that this place discloses and the ldpc coded signal of decoding is the LDPC variable modulation signal, it comprises a LDPC coded modulation code element and the 2nd LDPC coded modulation code element.The one LDPC coded modulation code element is to carry out modulating-coding according to first modulation that comprises the first letter group and corresponding first mapping; The 2nd LDPC coded modulation code element is to carry out modulating-coding according to second modulation that comprises the second letter group and corresponding second mapping.In addition, in other embodiments, first modulation and second modulation comprise a common letter group profile, yet wherein each all has different mappings.

Using the ldpc coded signal of this LDPC position-verification parallel decoding processing method decoding also can be a LDPC variable coding rate signal, and this signal comprises a LDPC code symbols and the 2nd LDPC code symbols.In this example, a LDPC code symbols is the LDPC coding according to first encoding rate, and the 2nd LDPC code symbols is the LDPC coding according to second encoding rate.

This decoder architecture of the present invention can be realized in the various types of communication equipments in the communication system of a lot of types.For instance, this communication system can be any one in satellite communication system, HDTV (high definition TV) communication system, cellular communication system, microwave telecommunication system, Point-to-Point Communication System, simplex system, intercommunication system, one-to-many communication system, optical fiber telecommunications system, WLAN (wireless domains office net) communication system and DSL (digital subscriber line) communication system.

According to an aspect of the present invention, provide the decoder of a kind of LDPC of execution (low-density checksum) position-verification parallel decoding, this decoder comprises:

Yardstick (metrics) calculator, it can calculate a plurality of m bit symbols yardsticks corresponding to the code element with m position of ldpc coded signal;

Symbol node calculator function piece, it uses the yardstick of a plurality of m bit symbols to calculate a plurality of yardsticks;

Position node computer functional block, it can use a plurality of soft information of a plurality of yardsticks calculating corresponding to the m position of code element;

The iterative decoding function blocks, it can use the edge messages of a plurality of a plurality of the piece nodes corresponding to minimum of a plurality of soft information initializings, and then supports the processing of position-verification parallel decoding in the decoding iteration of the default a plurality of execution sequences management of basis subsequently;

Wherein, this iterative decoding function blocks can be in a plurality of edge messages of very first time section renewal corresponding to first piece node;

Wherein, this iterative decoding function blocks also can be upgraded a plurality of edge messages corresponding to the first check block node simultaneously in very first time section;

Wherein, this iterative decoding function blocks can be upgraded a plurality of a plurality of edge messages corresponding to second piece node in second time period;

Wherein, this iterative decoding function blocks also can be upgraded a plurality of edge messages corresponding to the second check block node simultaneously in second time period;

Wherein, a plurality of edge messages are corresponding to a plurality of edges, and these a plurality of edges will be connected with a plurality of check block node communications ground corresponding to a plurality of piece nodes in the LDPC piece bipartite graph of LDPC coding, and ldpc coded signal produces by this LDPC coding.

Preferably:

This iterative decoding function blocks comprises a plurality of engine processors;

First engine processor in a plurality of engine processors can upgrade first edge messages corresponding to a plurality of edge messages of first piece node in very first time section; And

Second position engine processor in a plurality of engine processors can upgrade second edge messages corresponding to a plurality of edge messages of first piece node in very first time section.

Preferably:

This iterative decoding function blocks comprises a plurality of verification engine processors;

First verification engine processor in a plurality of verification engine processors can be in first edge messages of very first time section renewal corresponding to a plurality of edge messages of the first check block node; And

Second verification engine processor in a plurality of verification engine processors can be in second edge messages of very first time section renewal corresponding to a plurality of edge messages of the first check block node.

Preferably:

First piece node comprises the first multidigit node;

Second piece node comprises the second multidigit node;

The first check block node comprises more than first check-node; And

The second check block node comprises more than second check-node.

Preferably, decoder further comprises:

First memory, it is connected with iterative decoding function blocks communication ground;

Second memory, it is connected with iterative decoding function blocks communication ground;

Wherein, when a plurality of edge messages of upgrading in very first time section corresponding to first piece node, this iterative decoding function blocks can be visited first memory; And

Wherein, when a plurality of edge messages of upgrading in very first time section corresponding to the first check block node, this iterative decoding function blocks can be visited second memory simultaneously.

Preferably, this decoder further comprises:

The binary channels memory, it allows to carry out simultaneously read-write operation, and is connected with iterative decoding function blocks communication ground;

Wherein, when a plurality of edge messages of upgrading in very first time section corresponding to first piece node, the addressable binary channels memory of this iterative processing functional block; And

Wherein, when a plurality of edge messages of upgrading in very first time section corresponding to the first check block node, this iterative processing functional block also can be visited the binary channels memory simultaneously.

Preferably:

The soft estimation of the exportable ldpc coded signal code element of this iterative decoding function blocks position; And further comprise:

Hard limiter, the soft estimation of the code element position of its available ldpc coded signal determines firmly the code element position of ldpc coded signal, produces the best estimate of the code word of ldpc coded signal.

Preferably:

After the iterative decoding function blocks executed last decoding iteration according to default a plurality of execution sequences, this iterative processing functional block can be to reordering corresponding to a plurality of positions that changed second piece node of order according to default a plurality of execution sequences; And

Should allow this iterative decoding function blocks to export the soft estimation of the code element position of ldpc coded signal corresponding to reordering of second piece node position according to an order, in this order, the information bit into ldpc coded signal that is encoded at first.

Preferably:

After the iterative decoding function blocks is carried out last decoding iteration according to predetermined a plurality of execution sequence groups, the iterative decoding function blocks can be carried out an extra decoding iteration and without execution sequence control, so naturally to resequencing corresponding to according to predefined execution sequence a plurality of of second piece node changing having been taken place; And

Preferably:

This decoder can be implemented in communication equipment; And

This communication equipment can be applied among in the following communication system at least one, as: satellite communication system, HDTV (high definition TV) communication system, cellular communication system, microwave telecommunication system, Point-to-Point Communication System, simplex system, intercommunication system, one-to-many communication system, optical fiber telecommunications system, WLAN (wireless domains office net) communication system and DSL (digital subscriber line).

The yardstick calculator, it can calculate a plurality of m bit symbols yardsticks corresponding to the ldpc coded signal of the code element with m position;

Wherein, after the iterative decoding function blocks executed last decoding iteration according to default a plurality of execution sequences, this iterative processing functional block can be to reordering corresponding to a plurality of positions that changed second piece node of order according to default a plurality of execution sequences; And

Wherein, should allow this iterative decoding function blocks to export the soft estimation of the code element position of ldpc coded signal corresponding to reordering of a plurality of of second piece nodes according to an order, in this order, the information bit into ldpc coded signal that is encoded at first.

Preferably:

First engine processor in a plurality of engine processors upgrades first edge messages corresponding to a plurality of edge messages of first piece node in very first time section; And

Second position engine processor in a plurality of engine processors upgrades second edge messages corresponding to a plurality of edge messages of first piece node in very first time section.

Preferably:

First verification engine processor in a plurality of verification engine processors is in first edge messages of very first time section renewal corresponding to a plurality of edge messages of the first check block node; And

Second verification engine processor in a plurality of verification engine processors is in second edge messages of very first time section renewal corresponding to a plurality of edge messages of the first check block node.

Preferably:

First piece node comprises the first multidigit node;

Second piece node comprises the second multidigit node;

The first check block node comprises more than first check-node; And

The second check block node comprises more than second check-node.

Preferably, this decoder further comprises:

Preferably:

The soft estimation of the code element position of the exportable ldpc coded signal of this iterative decoding function blocks; And further comprise:

Hard limiter, the soft estimation of the code element position of its available ldpc coded signal determine firmly to the code element position of ldpc coded signal, thus the best estimate that produces the code word of ldpc coded signal.

Preferably:

This decoder can be implemented in communication equipment; And

The yardstick calculator, it can calculate a plurality of m bit symbols yardsticks corresponding to the code element with m position of ldpc coded signal;

Wherein, after the iterative decoding function blocks is carried out last decoding iteration according to predetermined a plurality of execution sequence groups, the iterative decoding function blocks can be carried out an extra decoding iteration and without execution sequence control, so naturally to resequencing corresponding to according to predefined execution sequence a plurality of of second piece node changing having been taken place; And

Preferably:

First piece node comprises the first multidigit node;

Second piece node comprises the second multidigit node;

The first check block node comprises more than first check-node; And

The second check block node comprises more than second check-node.

Preferably, this decoder further comprises:

Preferably:

Hard limiter, the soft estimation of the code element position of its available ldpc coded signal determine firmly the code element position of ldpc coded signal, and then produce the best estimate of the code word of ldpc coded signal.

Preferably:

This decoder can be implemented in communication equipment; And

According to an aspect of the present invention, provide a kind of Wireless Telecom Equipment, this equipment comprises:

Radio-frequency front-end, it is used for receiving and the filtering continuous time signal, and this signal comprises at least one use LDPC (low-density checksum) coding and the information encoded position;

ADC (analog to digital converter), it is used for the continuous time signal of this reception and filtering is sampled, thereby produces discrete-time signal and therefrom extract I, Q (homophase, quadrature) component;

Demodulator, it is used to receive I, Q component and execution I, the symbol mapped of Q component, thus produce centrifugal pump modulated symbol sequence; And

Can decode to the code element of centrifugal pump modulated symbol sequence, to obtain the best estimate of at least one signal bits wherein in LDPC position-verification code parallel decoder.

Preferably:

This LDPC position-verification code parallel decoder can carry out initialization to a plurality of edge messages of a plurality of a plurality of piece nodes corresponding to minimum, to support the processing of position-verification parallel decoding in the decoding iteration of the predetermined a plurality of execution sequences management of basis subsequently;

This LDPC position-verification code parallel decoder can upgrade a plurality of a plurality of edge messages corresponding to first piece node in very first time section;

This LDPC position-verification code parallel decoder also can be in a plurality of edge messages of very first time section inter-sync renewal corresponding to the first check block node;

This LDPC position-verification code parallel decoder upgrades a plurality of edge messages corresponding to second piece node in second time period;

This LDPC position-verification code parallel decoder is also in a plurality of edge messages of second time period inter-sync renewal corresponding to the second check block node; And

A plurality of edge messages are corresponding to a plurality of edges, and these a plurality of edges will be connected with a plurality of check block node communications ground corresponding to a plurality of piece nodes in the LDPC piece bipartite graph of LDPC coding, and ldpc coded signal produces by this LDPC coding.

Preferably:

This LDPC position-verification code parallel decoder comprises a plurality of engine processors:

First engine processor of a plurality of engine processors upgrades first edge messages corresponding to a plurality of edge messages of first piece node in very first time section; And

Second engine processor of a plurality of engine processors upgrades second edge messages corresponding to a plurality of edge messages of first piece node in very first time section.

Preferably:

This LDPC position-verification code parallel decoder comprises a plurality of verification engine processors;

The first verification engine processor of a plurality of verification engine processors upgrades first edge messages corresponding to a plurality of edge messages of first-check-node in very first time section; And

The second verification engine processor of a plurality of verification engine processors upgrades second edge messages corresponding to a plurality of edge messages of first-check-node in very first time section.

Preferably:

This LDPC position-verification code parallel decoder uses first memory and operates;

This LDPC position-verification code parallel decoder uses second memory and operates;

Visit first memory when this LDPC position-verification code parallel decoder upgrades corresponding to a plurality of edge messages of first piece node in very first time section; And

Synchronization of access second memory when this LDPC position-verification code parallel decoder also upgrades corresponding to a plurality of edge messages of the first check block node in very first time section.

Preferably, this equipment further comprises:

This LDPC position-verification code parallel decoder use allows to read while write binary channels (dualaccess) memory of visit and operates;

Visit binary channels memory when this LDPC position-verification code parallel decoder upgrades corresponding to a plurality of edge messages of first piece node in very first time section; And

Synchronization of access binary channels memory when this LDPC position-verification code parallel decoder also upgrades corresponding to a plurality of edge messages of the first check block node in very first time section.

Preferably:

After this LDPC position-verification code parallel decoder executed last decoding iteration according to default a plurality of execution sequences, this LDPC position-verification code parallel decoder can be to reordering corresponding to a plurality of positions that changed second piece node of order according to default a plurality of execution sequences; And

Should allow this LDPC position-verification code parallel decoder to export the soft estimation of code element position of the sequence of centrifugal pump modulated symbol according to an order corresponding to a plurality of of second piece node reorder, at least one information bit that is comprised in this order be encoded by LDPC at first.

Preferably:

After this LDPC position-verification code parallel decoder is carried out last decoding iteration according to predetermined a plurality of execution sequence groups, this LDPC position-verification code parallel decoder can be carried out an extra decoding iteration and without execution sequence control, so naturally to resequencing corresponding to according to predefined execution sequence a plurality of of second piece node changing having been taken place; And

Should allow this iterative decoding function blocks to export the soft estimation of the code element position of ldpc coded signal corresponding to reordering of a plurality of of second piece nodes according to an order, in this order, the information bit into ldpc coded signal that is encoded at first.

Preferably:

This first piece node comprises more than first position node;

This second piece node comprises more than second position node;

This first check block node comprises more than first check-node; And

This second check block node comprises more than second check-node.

Preferably:

The soft estimation of the code element position of this LDPC position-exportable centrifugal pump modulated symbol of verification code parallel decoder sequence; And

This LDPC position-verification code parallel decoder comprises hard limiter, and it can utilize the soft estimation of code element position to make the hard decision of code element position, is contained in the best estimate of at least one information bit in it with generation.

LDPC position-verification code parallel decoder, it is used for the code element of centrifugal pump modulated symbol sequence is decoded, to obtain being included in the best estimate of at least one information bit in it;

Wherein, this LDPC position-verification code parallel decoder can be to carrying out initialization corresponding to a plurality of edge messages of a plurality of piece nodes of minimum, to support position-verification parallel decoding to handle in the decoding iterative process according to predefined a plurality of execution sequence management subsequently;

Wherein, this LDPC position-verification code parallel decoder can upgrade a plurality of edge messages corresponding to first piece node in very first time section;

Wherein, this LDPC position-verification code parallel decoder also can be in a plurality of edge messages of very first time section inter-sync renewal corresponding to the first check block node;

Wherein, this LDPC position-verification code parallel decoder can upgrade a plurality of edge messages corresponding to second piece node in second time period;

Wherein, this LDPC position-verification code parallel decoder also can be in a plurality of edge messages of second time period inter-sync renewal corresponding to the second check block node; And

Preferably:

The first verification engine processor of a plurality of verification engine processors upgrades first edge messages corresponding to a plurality of edge messages of the first check block node in very first time section; And

The second verification engine processor of a plurality of verification engine processors upgrades second edge messages corresponding to a plurality of edge messages of the first check block node in very first time section.

Preferably:

Also synchronization of access second memory when this LDPC position-verification code parallel decoder upgrades corresponding to a plurality of edge messages of the first check block node in very first time section.

Preferably, this equipment further comprises:

This LDPC position-verification code parallel decoder use allows to read while write the binary channels memory of visit and operates;

Also synchronization of access binary channels memory when this LDPC position-verification code parallel decoder upgrades corresponding to a plurality of edge messages of the first check block node in very first time section.

Preferably:

This first piece node comprises more than first position node;

This second piece node comprises more than second position node;

This first check block node comprises more than first check-node; And

This second check block node comprises more than second check-node.

Preferably:

The soft estimation of the code element position of this LDPC position-verification code parallel decoder output centrifugal pump modulated symbol sequence; And

According to an aspect of the present invention, provide the method for a kind of LDPC of realization (low-density checksum) position-verification parallel decoding, this method comprises:

Receive and the filtering continuous time signal, this signal comprises at least one use LDPC (low-density checksum) coding and the information encoded position;

Continuous time signal to this reception and filtering is sampled, thereby produces discrete-time signal and therefrom extract I, Q (homophase, quadrature) component;

I, Q component are carried out demodulation and symbol mapped, thereby produce centrifugal pump modulated symbol sequence;

Code element to centrifugal pump modulated symbol sequence is decoded, and obtains being included in the best estimate of at least one signal bits in it to utilize LDPC position-verification parallel decoding of being controlled by predefined a plurality of execution sequences;

Wherein, the decoding step of this execution LDPC position-verification parallel decoding is included in very first time section and upgrades synchronously corresponding to a plurality of edge messages of first piece node and upgrade a plurality of edge messages corresponding to the first check block node;

Wherein, the decoding step of this execution LDPC position-verification parallel decoding was included in for second time period and upgrades synchronously corresponding to a plurality of edge messages of second piece node and upgrade a plurality of edge messages corresponding to the second check block node;

Preferably, this method further comprises:

The a plurality of a plurality of edge messages corresponding to a plurality of piece nodes of minimum of initialization are to support position-verification parallel decoding to handle in the decoding iteration of having managed according to predetermined a plurality of execution sequences subsequently.

Preferably, this method further comprises:

After executing last decoding iteration, to reordering corresponding to a plurality of positions that changed second piece node of order according to default a plurality of execution sequences according to default a plurality of execution sequences; And

Wherein, should allow to export according to an order the soft estimation of code element position of the sequence of centrifugal pump modulated symbol corresponding to a plurality of of second piece node reorder, at least one information bit that is comprised in this order is encoded by LDPC at first.

Preferably, this method further comprises:

After carrying out last decoding iteration according to predetermined a plurality of execution sequences, carry out an extra decoding iteration and without execution sequence control, so naturally to resequencing corresponding to according to predefined execution sequence a plurality of of second piece node changing having been taken place; And

Preferably:

This first piece node comprises more than first position node;

This second piece node comprises more than second position node;

This first check block node comprises more than first check-node; And

This second check block node comprises more than second check-node.

Preferably: this method further comprises:

The soft estimation of the code element position of output centrifugal pump modulated symbol sequence; And

Utilize the soft estimation execution of code element position to limit firmly, produce the best estimate that is included at least one information bit in it thus to make hard decision to the code element position.

Preferably:

This method is implemented in decoder;

This decoder can be implemented in communication equipment; And

According to an aspect of the present invention, provide a kind of method that is used to carry out LDPC (low-density checksum) position-verification parallel decoding, this method comprises:

Wherein, this coding/decoding method is to carrying out initialization process corresponding to a plurality of edge messages of a plurality of piece nodes of minimum, to support position-verification parallel decoding to handle in the coding iteration according to predefined a plurality of execution sequence management subsequently;

Wherein, after executing last decoding iteration, to reordering corresponding to a plurality of positions that changed second piece node of order according to default a plurality of execution sequences according to default a plurality of execution sequences; And

Wherein, should allow to export according to an order the soft estimation of the code element position of centrifugal pump modulated symbol sequence corresponding to a plurality of of second piece node reorder, at least one information bit that is comprised in this order is encoded by LDPC at first.

Preferably:

This first piece node comprises more than first position node;

This second piece node comprises more than second position node;

This first check block node comprises more than first check-node; And

This second check block node comprises more than second check-node.

Preferably: this method further comprises:

Preferably:

This method is implemented in decoder;

This decoder can be implemented in communication equipment; And

According to an aspect of the present invention, provide a kind of LDPC (low-density checksum) position-verification parallel decoding method that is used to carry out, this method comprises:

Wherein, after carrying out last decoding iteration according to predetermined a plurality of execution sequences, carry out an extra decoding iteration and without execution sequence control, so naturally to resequencing corresponding to according to predefined execution sequence a plurality of of second piece node changing having been taken place; And

Preferably:

This first piece node comprises more than first position node;

This second piece node comprises more than second position node;

This first check block node comprises more than first check-node; And

This second check block node comprises more than second check-node.

Preferably: this method further comprises:

Preferably:

This method is implemented in decoder;

This decoder can be implemented in communication equipment; And

The communication equipment of any kind of supporting function described herein and/or processing procedure has been contained in the present invention.And, can adopt various types of methods to support function described herein, and not depart from the scope of the present invention and spirit.

Description of drawings

System's legend of a kind of execution mode of the satellite communication system that Fig. 1 is according to the present invention to be set up;

System's legend of a kind of execution mode of HDTV (high definition TV) communication system that Fig. 2 is according to the present invention to be set up;

System's legend of a kind of execution mode of the unidirectional cellular communication system that Fig. 3 A and Fig. 3 B are according to the present invention to be set up;

System's legend of a kind of execution mode of the bi-directional cellular communication systems that Fig. 4 is according to the present invention to be set up;

System's legend of a kind of execution mode of the unidirectional microwave cellular communication system that Fig. 5 is according to the present invention to be set up;

System's legend of a kind of execution mode of the two-way microwave cellular communication system that Fig. 6 is according to the present invention to be set up;

System's legend of a kind of execution mode of the unidirectional point-to-point wireless communication system that Fig. 7 is according to the present invention to be set up;

System's legend of a kind of execution mode of the two-way point to point wireless communication system that Fig. 8 is according to the present invention to be set up;

System's legend of a kind of execution mode of the simplex system that Fig. 9 is according to the present invention to be set up;

System's legend of a kind of execution mode of the intercommunication system that Figure 10 is according to the present invention to be set up;

System's legend of a kind of execution mode of the one-to-many communication system that Figure 11 is according to the present invention to be set up;

System's legend of a kind of execution mode of WLAN (WLAN (wireless local area network)) communication system that Figure 12 is according to the present invention to be implemented;

System's legend of a kind of execution mode of DSL (digital subscriber line) communication system that Figure 13 is according to the present invention to be implemented;

System's legend of a kind of execution mode of the optical fiber telecommunications system that Figure 14 is according to the present invention to be set up;

System's legend of a kind of execution mode of satellite receiver STB (set-top box) system that Figure 15 is according to the present invention to be set up;

Figure 16 is the schematic diagram according to a communication system of some feature of the present invention, and this system comprises a plurality of base stations and/or access point, a plurality of Wireless Telecom Equipment and the network hardware;

Figure 17 is the schematic diagram according to a Wireless Telecom Equipment of some feature of the present invention, and this equipment comprises main frame and attached wireless receiver;

Figure 18 is the schematic diagram of the embodiment of another Wireless Telecom Equipment of institute's construction according to the present invention;

Figure 19 is the legend of a kind of embodiment of LDPC (low-density checksum) coding bipartite graph;

Figure 20 is a legend of using LDPC (low-density checksum) the coded modulation decoding function of position yardstick according to of the present invention;

Figure 21 is the legend (when carrying out n iteration) according to the another kind of embodiment of the LDPC coded modulation decoding function of use of the present invention position yardstick;

Figure 22 is the legend according to another embodiment of LDPC (low-density checksum) the coded modulation decoding function of a use of the present invention position yardstick (having a yardstick upgrades);

Figure 23 is the legend (when carrying out n iteration) according to the another kind of embodiment of LDPC (low-density checksum) the coded modulation decoding function of a use of the present invention position yardstick (having a yardstick upgrades);

Figure 24 A is a legend of using the position decoding of position yardstick (shown in LDPC (low-density checksum) coding bipartite graph) according to of the present invention;

Figure 24 B is a legend of using the position yardstick to upgrade the position decoding of (shown in LDPC (low-density checksum) coding bipartite graph) according to of the present invention;

Figure 25 A has a legend that symbol node is connected to LDPC (low-density checksum) coded modulation three components of a node according to of the present invention;

Figure 25 B has a legend (this bipartite graph is produced by three components of Figure 25 A) that symbol node is connected directly to LDPC (low-density checksum) the coded modulation bipartite graph (or code element bipartite graph) of check-node according to of the present invention;

Figure 26 A is the legend according to symbol decoding of the present invention (shown in LDPC (low-density checksum) coded modulation bipartite graph);

Figure 26 B is the legend according to a kind of embodiment of symbol decoding function of the present invention (by the support of LDPC (low-density checksum) sign indicating number modulation bipartite graph);

Figure 27 be according to the hybrid decoding function of LDPC of the present invention (low-density checksum) modulation signals (with the code element encoding ratio than the time its complexity reduce) the legend of a kind of embodiment;

Figure 28 be according to the hybrid decoding function of LDPC of the present invention (low-density checksum) modulation signals (when with the code element encoding ratio than the time have a complexity of simplification) the legend of another kind of embodiment;

Figure 29 is a legend of carrying out a kind of embodiment of LDPC position-verification parallel decoding of setting up according to the present invention;

Figure 30 is the legend of operating a kind of embodiment of LDPC position-verification parallel decoding function according to the present invention;

Figure 31 A is a kind of exemplary arrangement π that link is provided between LDPC piece bipartite graph and LDPC bipartite graph according to the present invention _{I, j} ¹The legend of embodiment;

Figure 31 B is a kind of exemplary arrangement π that link is provided between LDPC piece bipartite graph and LDPC bipartite graph according to the present invention _{I, j} ²The legend of another embodiment;

Figure 32 is the legend of another embodiment of the LDPC position-verification parallel decoding function operated according to the present invention.

Figure 33 is the legend of arranging a kind of embodiment of a LDPC piece-bipartite graph according to the present invention;

Figure 34 is the legend according to a kind of embodiment of the LDPC piece-bipartite graph of one of the present invention parallel block LDPC coding with 1/2 rate that piece is of a size of 1248 positions and 624 verification equatioies;

Figure 35 is the permutation table according to all edges of LDPC piece-bipartite graph of Figure 34 of the present invention;

Figure 36 be according to LDPC piece-bipartite graph of Figure 34 of the present invention by put in place the mapping table of piece node edge of check block node;

Figure 37 be according to LDPC piece-bipartite graph of Figure 34 of the present invention by the mapping table of position piece node to the check block node edge;

Figure 38 is the execution sequence table according to the LDPC piece-bipartite graph corresponding to Figure 34 of the present invention;

Figure 39, Figure 40, Figure 41 and Figure 42 are the various pieces according to the operation table that shows memory access of the LDPC piece-bipartite graph corresponding to Figure 34 of the present invention;

Figure 43 is optional execution sequence (is selectable to Figure 38) table according to the LDPC piece-bipartite graph corresponding to Figure 34 of the present invention;

Figure 44 is the legend according to a kind of embodiment of the LDPC piece-bipartite graph of one of the present invention parallel block LDPC coding with 2/3 rate that piece is of a size of 1200 positions and 400 verification equatioies;

Figure 45 be Figure 44 according to the present invention LDPC piece-bipartite graph by put in place the mapping table of piece node edge of check block node;

Figure 46 is the execution sequence table according to the LDPC piece-bipartite graph corresponding to Figure 44 of the present invention;

Figure 47 is the legend according to a kind of embodiment of the LDPC position-verification parallel decoding function of use of the present invention position yardstick;

Figure 48 is the flow chart according to a kind of embodiment of the method for execution LDPC of the present invention position-verification parallel decoding;

Figure 49 is the flow chart according to the another kind of optional embodiment of the method for execution LDPC of the present invention position-verification parallel decoding;

Figure 50 is the legend according to a kind of embodiment of the LDPC position-verification parallel decoding function of a use of the present invention position yardstick (having a yardstick upgrades);

Figure 51 is the legend of a kind of embodiment of the LDPC code element-verification parallel decoding function according to use code element yardstick of the present invention;

Figure 52 is the legend according to a kind of embodiment of the LDPC mixing-verification parallel decoding function of use code element yardstick of the present invention and position yardstick;

Figure 53 A is the legend according to a kind of embodiment of the first step of LDPC of the present invention position-verification parallel decoding processing;

Figure 53 B is the legend according to a kind of embodiment of the first step of LDPC code element of the present invention-verification parallel decoding processing.

Embodiment

Various decoding feature of the present invention can find in the equipment that LDPC (low-density checksum) code signal is decoded, and therefore can reach synchronously concurrently the renewal of the edge messages (under the situation that iterative decoding is handled) that is relevant to check-node and position node and carry out.Only using under the situation of position yardstick adapted for decoding LDPC code signal, can reach parallel running synchronously at iterative decoding process meta engine processor and verification engine processor.Compared with prior art, this decoding process can be saved service speed and the stand-by period in iterative decoding is handled significantly.For example, when decoding according to the present invention, consider this situation: when the verification engine processor service speed and the service speed of position engine processor are can be equally fast, the whole stand-by period of decoding processing (for example can reduce by about 49% coefficient so, the decoding speed of carrying out is almost fast one times), described in following a kind of embodiment.

In addition, when adapted for decoding LDPC code signal can extend to the ldpc coded signal coding/decoding method that exceeds those simple LDPC position-verification parallel decodings, this reached the parallel method updating edge messages synchronously.For example, the LDPC coding/decoding method based on code element or the operation of use mixed method also can benefit from the reaching the paralleling update method synchronously of edge messages of the ground of communication between variable-block node and check-node connection.For example, this method can be expanded to LDPC code element-verification parallel decoding or LDPC mixing-verification parallel decoding.That is to say that the parallel characteristics of the decoding processing that disclose in this place not only can be expanded the method for using the position that ldpc coded signal is decoded to only, and can extend to the code element of this ldpc coded signal of decodable code and the method for hybrid coding.

Generally speaking, various feature of the present invention can embody in any equipment that ldpc coded signal is decoded.Sometimes, these equipment are supported two-way communications and are used to finish the coding and the decoding of ldpc coded signal.And in certain embodiments, coding and decoding can be by carrying out in conjunction with LDPC coding and modulating-coding, to produce a ldpc coded signal.In some examples of the invention, this LDPC coding combines with modulating-coding to produce variable modulation signal, and the code element that is modulated at of this modulation signal is followed variation equally continually on the basis of code element.That is to say that the letter group of the code element of LDPC coding variable modulation signal and/or mapping can change equally continually on code element is followed the basis of code element.In addition, the code element encoding rate of code signal also can be followed on the basis of code element in code element and change equally continually.In a word, the LDPC signal that produces of coding characteristic according to the present invention can be a feature with variable encoding rate and/or modulation signal.

The novel method of the ldpc coded signal decoding that discloses in this place can be applicable in various types of ldpc coded signals (as, straight-preceding ldpc coded signal, ldpc coded modulation signal, the LDPC variable modulation signal, LDPC variable coding rate signal, or the like).

In the following description, at first disclose the general structure of parallel block LDPC coding.This structure is carried out the LDPC coding decoder that length is provided to a reality and feasible hardware.This general structure has also disclosed some known LDPC coding structure, as described in some special case.Thereupon, the coding/decoding method of various ldpc coded signals is also revealed, comprising: only position decoding, only position decoding (having a yardstick upgrades), symbol decoding, and hybrid decoding.Thereafter, each method of the whole bag of tricks of these ldpc coded signals decoding is described in this mode, by this mode, it can be used to reach synchronously the parallel iteration decoding processing corresponding to each the edge messages renewal in these coding/decoding methods.For example, introduced a LDPC decoder that utilizes the use LDPC position-verification parallel decoding function of position yardstick.This decoder can be looked at as LDPC position-verification code parallel decoder.By using the decoder of this function, position engine processor and the synchronous operation in the iterative decoding processing procedure of verification engine processor.In a special example, when hypothesis verification engine processor is identical with the position engine processing speed of service, with respect to the method for ldpc coded signal traditional and prior art, the method for this new introducing has saved for 49% stand-by period for adapted for decoding LDPC code signal so.

Various system embodiments are described below, and various features of the present invention can be implemented therein.In a word, the coding and/or the decoding device of any execution ldpc coded signal (the parallel and method for synchronous updating edge messages of use that disclose in this place) all can have benefited from the present invention.Again, this comprises that also those have the ldpc coded signal of variable coding rate and/or modulation, and those comprise synthetic LDPC coding and modulating-coding.

System's legend of a kind of execution mode of the satellite communication system that Fig. 1 is according to the present invention to be set up.Satellite launch vehicle is connected with dish communication ground, and this dish can communicate with satellite.This satellite launch vehicle also can be connected with cable network communication ground.This cable network comprises multiple network, comprises the Internet, proprietary network, other cable network and/or WANs (wide area network).This satellite launch vehicle communicates by the dish and the satellite of radio communication channel applied satellite.This satellite can communicate with one or more satellite receivers (each has a dish).Each satellite receiver also can be connected in to communication on the display.

Here, be sent to and can be looked at as a radio communication channel synergistically, or each is sent to or can be counted as two different radio communication channels from the communication linkage of satellite from the communication of satellite.

For example, in one embodiment, radio communication " channel " can be counted as not comprising the multi-hop wireless net.In the embodiment of another multi-hop, satellite is from satellite launch vehicle received signal (passing through dish), with its amplification and relay satellite receiver (by its dish); This satellite receiver also can utilize the land receiver to implement in other receiver types, as: satellite receiver, satellite-based phone and/or it is in the Internet of satellite receiver.Satellite receives and receives signal from satellite transmission device (by its dish), with its amplification, and relays, and this satellite can be looked at as " a transponder in this case; " this is the embodiment of a multi-hop.In addition, may there be other satellite, with the operation of this satellite cooperation with execution receiver and transmitter.In this case, by on the radio communication channel-each branch road of transmitting down can be considered to independently.

In any embodiment, satellite is all communicated by letter with satellite receiver.In certain embodiment (using local antenna), this satellite receiver can be looked at as a mobile unit; As selection, satellite receiver can be looked at as the ground satellite station that is connected with cable network communication ground, and in a similar manner, satellite launch vehicle also can be connected with cable network communication ground.

According at least some functions and/or the processing method in the various features of the present invention, satellite launch vehicle is encoded to information (utilizing encoder) in one way, will be sent in the communication channel that is connected with satellite launch vehicle and satellite receiver to help to produce.According at least some functions and/or the processing method in the various features of the present invention, this satellite receiver is decoded to information (utilizing decoder) in one way.The figure shows out an embodiment, wherein can find the one or more of various features of the present invention.

Fig. 2 is an embodiment of a HDTV (high definition TV) communication system of institute's construction according to the present invention.The HDTV reflector is connected with launching tower with communicating.The HDTV reflector utilizes its launching tower and sends a signal to local tower dish by radio communication channel.Local tower dish can be connected with HDTV STB (set-top box) receiver communication ground by coaxial cable.HDTV STB receiver comprises the function of the wireless transmitted signals that reception has been received by local tower dish.This function comprises required any conversion and/or down-conversion, before HDTV reflector and the emission of relevant launching tower thereof or any up-conversion that may finish during the emission, it is for communication channel that signal transformation one-tenth and transmission signals will the be utilized form of compatibility mutually that signal is carried out up-conversion with adaptation signal.For example, some communication system is before being transmitted into communication channel with signal, and the signal that will launch is transformed into IF (intermediate frequency) signal from baseband signal earlier, and then is transformed into carrier signal.Alternatively, some communication systems were carrier frequency with baseband conversion directly before this signal is emitted to communication channel.No matter adopt which kind of situation in this special embodiment, HDTV STB receiver can be carried out any down converted, and it becomes baseband signal to be necessary the signal transition that receives, and this baseband signal is applicable to demodulation and decoding, with therefrom information extraction.

HDTV STB receiver also is connected with HDTV display communication ground, so that can show demodulation that is received by HDTVSTB receiver and local tower dish thereof and the wireless transmitted signals of decoding.In this embodiment, HDTV reflector (by its tower) directly transmits to local launching tower by radio communication channel.In another embodiment, can at first use the satellite ground ground station station that is connected with HDTV reflector communication ground to receive a signal, by radio communication channel this signal that receives is transmitted into local tower teledish then from satellite.Under this situation, the HDTV reflector is worked as a repeater, in order to signal forwarding that satellite is provided at first to the final HDTV STB receiver of appointment of institute.For example, another ground satellite station can at first transmit a signal to satellite from the another location, and satellite is transmitted this signal to the ground satellite station that is connected with HDTV reflector communication ground.In this case, this HDTV reflector comprises transceiver function, so that it can at first carry out the receiver function, carries out transmitter function then, is sent to local tower dish with the signal with this reception.

In another embodiment, this HDTV reflector utilizes its ground satellite station by radio communication channel and satellite communication.This satellite can communicate with local tower dish; This this locality tower dish is connected with HDTV STB receiver communication ground by coaxial cable.This transmission path has still shown another communication path, and wherein HDTV STB receiver can communicate with the HDTV reflector.

No matter reach the HDTV reflector by with which kind of signal path communicating by letter with HDTV STB receiver in which kind of embodiment, HDTV STB receiver can both be from HDTV transmitter receipt communications and suitably with their demodulation and decoding.

A kind of mode of this HDTV reflector at least some functions in the various features and/or processing procedure according to the present invention is encoded (utilizing encoder) to information, with help to produce will launch into communication channel that HDTV reflector and HDTV STB receiver are connected in signal.HDTV STB receiver can be according to the present invention a kind of mode of at least some functions in the various features and/or processing procedure to the signal that from communication channel, receives decode (utilizing decoder).The figure shows another embodiment, wherein, one or more various features of the present invention can be found.

Fig. 3 A and Fig. 3 B are the system's legend of the embodiment of the unidirectional cellular communication system of institute's construction according to the present invention.

With reference to figure 3A, the local antenna that mobile transmitter is connected by communication with it.This mobile transmitter can be polytype reflector, and it comprises unidirectional cell phone, radio pager unit, has the mobile computer of transmitting function or the mobile transmitter of any other type.This mobile transmitter uses its local antenna will send a signal to cell tower by radio communication channel.This cell tower is connected with base station receiver communication ground; This receives tower can be by the local antenna reception transfer of data of radio communication channel from mobile transmitter.This cell tower is connected the signal that receives with base station receiver communication ground.

This mobile transmitter can be according to the present invention at least some functions in the various features and/or processing procedure in one way information is encoded by (use encoder), with help to produce will launch into communication channel that mobile transmitter and base station receiver are connected in signal.This base station receiver can be according to the present invention at least some functions in the various features and/or processing procedure in one way to the information that from communication channel, receives decode (use decoder).The figure shows another embodiment, wherein, one or more various features of the present invention can be found.

With reference to Fig. 3 B, base station transmitter comprises connection cell tower thereon.This base station transmitter uses its cell tower to transmit signals to mobile receiver by communication channel.Mobile receiver can be the receiver of any kind, and it comprises unidirectional cell phone, radio pager unit, has the mobile computer of receiving function or the mobile receiver of any other type.Mobile receiver is connected with local antenna with communicating; Local antenna can receive transfer of data from the cell tower of base station transmitter, and these data are transmitted by radio communication channel.This this locality antenna is connected the signal that receives with mobile receiver communication ground.

Base station transmitter according to the present invention at least some functions in the various features and/or processing procedure in one way information is encoded by (use encoder), with help to produce will launch into communication channel that base station transmitter and mobile receiver are connected in signal.This mobile receiver can be according to the present invention at least some functions in the various features and/or processing procedure in one way from communication channel to information decode (use decoder).The figure shows another embodiment, wherein, one or more various features of the present invention can be found.

Fig. 4 is the system's legend of a kind of embodiment of a bi-directional cellular communication systems of institute's construction according to the present invention, and wherein, this communication is carried out two-way communication by radio communication channel between base station transceiver and ambulatory transceiver device.

With reference to Fig. 4, this base station transceiver comprises that communication ground connects cell tower thereon.Base station transceiver uses its cell tower to send a signal to the ambulatory transceiver device by communication channel.This reverse link communication operation can be performed.The ambulatory transceiver device can send a signal to base station transceiver equally.This ambulatory transceiver device can be the transceiver of any kind, and it comprises the ambulatory transceiver device of cell phone, radio pager unit, the mobile computer with transmission-receiving function or any other type.This ambulatory transceiver device is connected with local antenna with communicating; This this locality antenna can receive from the transfer of data of the cell tower of the base station transmitter by radio communication channel communication.This this locality antenna is connected the signal that receives with ambulatory transceiver device communication ground.

Base station transceiver can be encoded to the information (using its corresponding encoder) that will be transferred into the ambulatory transceiver device.The signal of this this transmission of ambulatory transceiver device decodable code (using its corresponding decoder).Similarly, the ambulatory transceiver device can be encoded to the information (using its corresponding encoder) that will be transferred into base station transceiver.The signal of this this transmission of base station transceiver decodable code (using its corresponding decoder).

Adopt the embodiment of encoder and decoder the same with other, any encoder in base station transceiver or the ambulatory transceiver device according to the present invention at least some functions in the various features and/or processing procedure in one way information is encoded (using its corresponding encoder), to help produce will launch into communication channel that base station transceiver and ambulatory transceiver device are connected in signal.Any decoder in base station transceiver or the ambulatory transceiver device can be according to the present invention at least some functions in the various features and/or processing procedure in one way to the information of this transmission decode (using its corresponding decoder).The figure shows another embodiment, wherein, one or more various features of the present invention can be found.

System's legend of a kind of execution mode of the unidirectional microwave cellular communication system that Fig. 5 is according to the present invention to be set up.Microwave emitter is connected with microwave tower communication ground.Microwave emitter uses its microwave tower to transmit signals to microwave tower by radio communication channel.Be connected to the microwave receiver communication microwave tower.This microwave tower can be by the transmission signal of radio communication channel reception from microwave tower.

This microwave emitter according to the present invention at least some functions in the various features and/or processing procedure in one way information is encoded by (use encoder), with help to produce will launch into communication channel that microwave emitter and microwave receiver are connected in signal.Microwave receiver can be according to the present invention at least some functions in the various features and/or processing procedure in one way to the information that receives from communication channel decode (use decoder).The figure shows another embodiment, wherein, one or more various features of the present invention can be found.

System's legend of a kind of execution mode of the two-way microwave cellular communication system that Fig. 6 is according to the present invention to be set up.In Fig. 6, first microwave transceiver is connected with first microwave tower communication ground.First microwave transceiver uses first microwave tower (microwave tower of first microwave transceiver) to transmit signals to second microwave tower of second microwave transceiver by radio communication channel.This second microwave transceiver is connected to communication with second microwave tower (microwave tower of second microwave transceiver).Second microwave tower can be by the transmission signal of radio communication channel reception from first microwave tower.Use first and second microwave transceiver also can carry out reverse traffic operation.

Each microwave transceiver all can encode (using its corresponding encoder) to the information that will be transferred into another microwave transceiver.Each microwave transceiver all can be decoded to the transmission signals (using its corresponding decoder) that receives.Each microwave transceiver all comprises encoder and decoder.

Adopt the embodiment of encoder and decoder as other, each encoder of these two microwave transceivers can be according to the present invention at least some functions in the various features and/or processing procedure in one way information is encoded (use corresponding encoder), to help the signal that produces in the communication channel that will launch between these two microwave transceivers of into connection.Decoder in these two microwave transceivers can be according to the present invention at least some functions in the various features and/or processing procedure in one way to transmission signals decode (using corresponding decoder).The figure shows another embodiment, wherein, one or more various features of the present invention can be found.

System's legend of a kind of execution mode of the unidirectional point-to-point wireless communication system that Fig. 7 is according to the present invention to be set up wherein, communicates from a mobile unit reflector to a mobile unit receiver by radio communication channel.

The mobile unit reflector comprises the local antenna that is connected with it with communicating.The mobile unit reflector uses its local antenna to transmit signals to the local antenna of mobile unit receiver by radio communication channel.

This mobile unit reflector according to the present invention at least some functions in the various features and/or processing procedure in one way information is encoded by (use encoder), to help produce will launch into communication channel that mobile unit reflector and mobile unit receiver are connected in signal.This mobile unit receiver can be according to the present invention at least some functions in the various features and/or processing procedure in one way to the signal that receives from communication channel decode (use decoder).The figure shows another embodiment, wherein, one or more various features of the present invention can be found.

System's legend of a kind of execution mode of the two-way point to point wireless communication system that Fig. 8 is according to the present invention to be set up.The first mobile unit transceiver is connected with the first local antenna with communicating.This first mobile unit transceiver uses the first local antenna (the local antenna of the first mobile unit transceiver) by radio communication channel, transmits signals to the second local antenna of the second mobile unit transceiver.The second mobile unit transceiver is connected with the second local antenna (the local antenna of the second mobile unit transceiver) with communicating.The second local antenna can be by the transmission signals of radio communication channel reception from the first local antenna.Reverse communication also can be carried out between the first and second mobile unit transceivers.

Each mobile unit transceiver all can be encoded to the information (using its corresponding encoder) that will be transferred into another mobile unit transceiver.Each mobile unit transceiver all can decode (using its corresponding decoder) to its transmission signals that receives.Each mobile unit transceiver all comprises encoder and decoder.

The same with other embodiment that adopts encoder and decoder, each encoder of these two mobile unit transceivers can be according to the present invention at least some functions in the various features and/or processing procedure in one way information is encoded (use corresponding encoder), to help the signal that produces in the communication channel that will launch these two mobile unit transceivers of into connection.Each decoder of these two mobile unit transceivers can be according to the present invention at least some functions in the various features and/or processing procedure in one way to this transmission signals decode (using corresponding decoder).The figure shows another embodiment, wherein, one or more various features of the present invention can be found.

System's legend of a kind of execution mode of the simplex system that Fig. 9 is according to the present invention to be set up.Reflector communicates by uni directional communication channel and receiver.This uni directional communication channel can for the wire communication channel or radio communication channel depart from the scope of the present invention and spirit.The wired media that can be used as the one-way communication passage can be polytype, comprises coaxial cable, optical cable and copper cable, and other " wired " type.Similarly, can support the wireless mode that communicates with uni directional communication channel that all kinds are also arranged, comprise satellite communication, cellular communication, microwave communication, radio communication, and the radio communication of other type.

This reflector can be according to the present invention at least some functions in the various features and/or processing procedure in one way information is encoded by (use encoder), to help produce will launch into communication channel that reflector and receiver are connected in signal.This receiver can be according to the present invention at least some functions in the various features and/or processing procedure in one way to the signal that from communication port, receives decode (use decoder).The figure shows another embodiment, wherein, one or more various features of the present invention can be found.

System's legend of a kind of execution mode of the intercommunication system that Figure 10 is according to the present invention to be set up.First transceiver communicates by the bi-directional communication channel and second transceiver.This bi-directional communication channel can for the wire communication channel or radio communication channel depart from the scope of the present invention and spirit.The wired media that can be used as bi-directional communication channels can be polytype, comprises coaxial cable, optical cable and copper cable, and other " wired " type.Similarly, can support the wireless mode that communicates with bi-directional communication channel that all kinds are also arranged, comprise satellite communication, cellular communication, microwave communication, radio communication, and the radio communication of other type.

Each transceiver all can encode (using its corresponding encoder) to the information that will be transferred into another transceiver.Each transceiver its transmission signals that receives (using its corresponding decoder) of all can decoding.Each transceiver all comprises encoder and decoder.

The same with other embodiment that adopts encoder and decoder, each encoder in these two transceivers can be according to the present invention at least some functions in the various features and/or processing procedure in one way information is encoded (use corresponding encoder), to help the signal that produces in the communication channel that will launch these two transceivers of into connection.Each decoder of these two transceivers can be according to the present invention at least some functions in the various features and/or processing procedure in one way to this transmission signals decode (using corresponding decoder).The figure shows another embodiment, wherein, one or more various features of the present invention can be found.

System's legend of a kind of execution mode of the one-to-many communication system that Figure 11 is according to the present invention to be set up.In certain embodiments, can be by broadcsting transmitter by uni directional communication channel and a plurality of receiver, as receiver 1 ..., n communicates.This uni directional communication channel can for the wire communication channel or radio communication channel depart from the scope of the present invention and spirit.The wired media that can be used as communication port can be polytype, comprises coaxial cable, optical cable and copper cable, and other " wired " type.Similarly, can support the wireless mode that communicates with communication channel that all kinds are also arranged, comprise satellite communication, cellular communication, microwave communication, radio communication, and the radio communication of other type.

In the one-to-many communication system, adopt distributed points being provided to receiver 1 ..., the communication that n is fit to.In certain embodiments, receiver 1 ..., each of n all receives identical communication, distinguishes separately in whole communications afterwards to send to that part of of them.

This reflector according to the present invention at least some functions in the various features and/or processing procedure in one way to information encode (use encoder), will launch into and reflector and receiver 1 to help producing,, the signal in the communication channel that n is connected.This receiver 1 ..., each among the n can be according to the present invention at least some functions in the various features and/or processing procedure in one way to the signal that from communication channel, receives decode (use decoder).The figure shows another embodiment, wherein, one or more various features of the present invention can be found.

Figure 12 is system's legend of a kind of execution mode of WLAN (WLAN (wireless local area network)) communication system performed according to the present invention.

System's legend of a kind of execution mode of WLAN (WLAN (wireless local area network)) communication system that Figure 12 is according to the present invention to be set up.This WLAN communication system can comprise a plurality of equipment that intercom mutually by WLAN.Each all has the function that is connected with WLAN in above-mentioned a plurality of equipment, for example, these equipment comprise following listed one or more: kneetop computer, television set, PC (personal computer), pen-based computer (can be counted as sometimes PDA (personal digital assistant), personal electric plan this, or similar devices), mobile device (but can be counted as phone, beep-pager or some other moves the WLAN operating equipment) and/or permanent plant (can be counted as being placed on usually the equipment in the special place in the WLAN).The antenna of the arbitrary equipment in the various WLAN interactive devices can be integrated in the corresponding apparatus, and does not depart from the scope of the present invention and spirit.

Above listed this group can with the equipment of WLAN interaction, be not exhaustive list,

This equipment group of giving an example that can be connected with WLAN not can for the exclusive list of the equipment of WLAN interaction, shown in represent any communication equipment that comprises this function as the general device of WLAN connection device, to be connected with the WLAN associated device with WLAN itself and/or other.On the whole, any one be looked at as WLAN interactive device of these and WLAN associated device and not departing from the scope of the present invention and spirit.Each this equipment and WLAN interactive device can be counted as being placed on the node of WLAN.

Notice that equally this WLAN itself also comprises the function of permission itself and other network interaction.These external networks are commonly referred to WAN (wide area network).For example, this WLAN comprises the Internet I/F (interface), and its permission is connected with the Internet itself.This Internet I/F can be looked at as the base station equipment of WLAN, and it allows any WLAN interactive device access internet.

Notice equally, except can with Internet connection, this WLAN also comprises and can intersect the function be connected with other network (as other WANs).For example, this WLAN can comprise microwave tower I/F, its can with the microwave tower interaction, thereby can communicate with one or more microwave networks.Similar to above-mentioned the Internet I/F, this microwave tower I/F can be counted as the base station equipment of WLAN, and it allows any WLAN interactive device to visit one or more microwave networks by this microwave tower.

And this WLAN can comprise ground satellite station I/F, thereby it allows to allow to communicate with one or more ground satellite stations with the ground satellite station interaction.For WLAN, this ground satellite station I/F can be counted as base station equipment, and it allows any WLAN interactive device to visit one or more satellite networks by this ground satellite station I/F.

This limited tabulation with the variety of network types of WLAN interaction is not exhaustive.For example, any other network can by have can make the WLAN interactive device visit other network function suitable I/F communication be connected to WLAN.

In the various WLAN interactive devices described in the present embodiment any one all comprises encoder and decoder, to allow carrying out two-way communication with other WLAN interactive device and/or WAN.Again, comprise among the embodiment of bi-directional communication device at other with encoder and decoder, the encoder of the arbitrary equipment in these all kinds WLAN interactive device can be according to the present invention at least some functions in the various features and/or processing procedure in one way information is encoded (using its corresponding encoder), to help produce will launch into communication channel that another WLAN interactive device is connected in signal.The decoder of any the WLAN interactive device in these types can be according to the present invention at least some functions in the various features and/or processing procedure in one way to transmission signals decode (using its corresponding decoder).The figure shows another embodiment, wherein, one or more various features of the present invention can be found.

In general, any one the be characterized by IEEE (IEEE) in the WLAN interactive device but 802.11 operating equipments.For example, but but but but such one 802.11 operating equipment can be a 802.11a operating equipment, a 802.11b operating equipment or a 802.11g operating equipment.Sometimes, but 802.11 operating equipments can communicate according to a plurality of standards (following 802.11g again) as promptly following 802.11a in the example.IEEE 802.11g standard extends to 2.4GHz (Giga-Hertz) frequency range with packet transfer rate.This expansion can realize by two kinds of dissimilar bags (being also referred to as frame) are coexisted in this frequency band.As the part of 802.11b standard, utilize the frame of DSSS/CCK (Direct swquence spread spectrum) to be defined as on the 2.4GHz bandwidth to transmit up to the speed of 11Mbps (megabyte per second) with compensation codes keying.802.11a standard uses different frame format OFDM (OFDM) to transmit on the carrier frequency of 5GHz scope with the speed up to 54Mbps.The IEEE802.11g standard allows this OFDM frame and the coexistence of DSSS/CCK frame on 2.4GHz.

System's legend of a kind of execution mode of DSL (digital subscriber line) communication system that Figure 13 is according to the present invention to be set up.This DSL communication system comprises the interface that is connected in the Internet (or some other WAN).The Internet itself shown in this figure does not depart from the scope of the present invention and spirit but other WANs also may be utilized.ISP (Internet Service Provider) can send data and receive data from the Internet to the Internet.This ISP is connected with CO (central office) communication ground, and this CO is controlled by telephone service company usually.This CO can also provide telephone service for one or more users.Yet this CO allows Internet service to be connected with one or more users' (its interactive device is called subscriber equipment) interface equally.These subscriber equipmenies can be any one in the various device, comprise desktop computer, kneetop computer, server and/or handheld device and do not depart from the scope of the present invention and spirit.Any one of these subscriber equipmenies also can be wired or wireless type equipment.Each subscriber equipment is connected to this CO by the DSL modulator-demodulator.But this DSL modulator-demodulator also is connected to communication multi-user's access point or hub to allow a plurality of user equipment access the Internets.

This CO and these various DSL modulator-demodulators also can comprise encoder and decoder, to allow to carry out therein two-way communication.For example, when communicating by letter with different DSL modulator-demodulator and ISP dealing, this CO can encode and decode data.Similarly, when with CO and one or more communications of user equipment separately, each different DSL modulator-demodulator can be encoded and decode data.

In other the employing encoder and the embodiment of decoder, the encoder of any CO and different DSL modulator-demodulator can be according to the present invention at least some functions in the various features and/or processing procedure in one way information is encoded (using its corresponding encoder), with help to produce will launch into communication channel that CO and different DSL modulator-demodulator are connected in signal.The decoder of any CO and different DSL modulator-demodulator can be according to the present invention at least some functions in the various features and/or processing procedure carry out in one way transmission signals decode (using its corresponding decoder).The figure shows another embodiment, wherein, one or more various features of the present invention can be found.

System's legend of a kind of execution mode of the optical fiber telecommunications system that Figure 14 is according to the present invention to be set up.This optical fiber telecommunications system comprises DWDM (dense wave division multipurpose is under the optical fiber communication situation) Line cards, and it is inserted between line scan pickup coil side and the client.Recently the benefit of DWDM technology obtains continuous growth.From technology and economic two aspects, it is the remarkable advantages of DWDM technology that the ability of potential unlimited transmission capacity can be provided.Adopt DWDM, not only can protect the current investment of having done, and it may be optimized 32 times at least the fiber basis facility.When demand changed, the quantity by independent device upgrade or the wavelength (λ) by increasing optical fiber cable itself can add bigger capacity, does not need the upgrading of costliness.Owing to can reach the output of the cost on the equipment of being retracted in, the investment of existing optical fiber production factory can be retained.From the bandwidth aspect, the more noticeable technical advantages of DWDM may be summarized as follows:

1, the transparency of DWDM: because DWDM is PHY (physical layer) structure, it can be supported TDM (time division multiplexing) pellucidly and as data format, gigabit Ethernet, the ESCON (business system connection) of ATM (asynchronous transfer mode), reach the fiber channel that has open interface on usual physical layer.

2, the upgrading ability of DWDM: DWDM can replenish the abundant amount of dark fibre in city, a lot of big city and the enterprise network, to satisfy the demand to point-to-point link and existing SONET/SDH (Synchronous Optical Network)/(synchronous digital hierarchy system) ring capacity apace.

3, the dynamic provisioning ability of DWDM: network connect fast, simple and dynamic supply makes supplier can provide in the sky rather than in the ability of the high-bandwidth service of the moon.

Optical fiber connects each user side and the line scan pickup coil side that is applied to the DWDM Line cards.The DWDM Line cards comprises transmission processor, and it comprises the function of supporting the long communication distance transmission of DWDM, the transmission of DWDM metropolitan area, SONET/SDH multiplexer of future generation, digital crossover connection and fibre-optic terminus and testing equipment.At line scan pickup coil side, the DWDM Line cards comprises reflector, and in order to transmit to the light medium, it can carry out the conversion of electrical-optical; Also comprise receiver, for from light medium received signal, it can carry out the conversion of light-electricity.At user side, the DWDM Line cards comprises the 10G serial module, and it can utilize the arbitrary miscellaneous equipment on the user side of optical fiber interface and optical fiber telecommunications system to communicate.Alternatively, this interface can use non-fiber medium to realize, comprises the interface medium of copper cable and/or some other types.

The DWDM transmission processor of DWDM Line cards comprises decoder, and the signal that is received from line scan pickup coil side and user side of being used to decode, and an encoder are sent to the signal of line scan pickup coil side and user side in order to coding.

In other the employing encoder and the embodiment of decoder, this encoder can at least some functions and/or the processing procedure in the various features be encoded to information in one way according to the present invention, with help to produce will launch into communication channel that the DWDM Line cards is connected in signal.This decoder can be according to the present invention at least some functions in the various features and/or processing procedure in one way the signal that receives from channel is decoded.The figure shows another embodiment, wherein, one or more various features of the present invention can be found.

System's legend of a kind of execution mode of satellite receiver STB (set-top box) system that Figure 15 is according to the present invention to be set up.This satellite receiver STB system is included in the advanced person's who moves in the digital structure modulation satellite receiver.And in certain embodiments, this advanced person's modulation satellite receiver can be realized on single integrated circuit.This satellite receiver STB comprises the satellite tuner by L-frequency band (is in the hyperfrequency radio frequency range of 390-1550MHz as frequency range) received signal.This satellite tuner extracts I from the signal that the L-frequency band is received, Q (homophase, quadrature) component also offers this advanced person's modulation satellite receiver with them.This advanced person's modulation satellite receiver comprises decoder.

In other the embodiment of employing decoder, this decoder can at least some functions and/or the processing procedure in the various features be encoded to information in one way according to the present invention, to help to produce the signal that will launch in the communication channel that is connected with advanced modulation satellite receiver.The figure shows another embodiment, wherein, one or more various features of the present invention can be found.

This advanced person's modulation satellite receiver can connect with HDTV MPEG-2 (dynamic picture expert group, the second layer) transmission demultiplexer, audio/video decoder and display engine communication ground.This advanced person's modulation satellite receiver and HDTV MPEG-2 transmission demultiplexer, audio/video decoder and display engine are connected with host CPU (central processing unit) communication ground.This HDTV MPEG-2 transmission demodulation multiplexer, audio/video decoder and display engine also are connected with memory module and traditional access function piece communication ground.This HDTV MPEG-2 transmission demultiplexer, audio/video decoder and display engine provide and can be video and the audio frequency output that the HDTV display provides HD (high definition).

This advanced person's modulation satellite receiver is embodied as the single-chip digital satellite receiver of the decoder that support operates by the inventive method, this decoder according to the present invention at least some functions and/or the processing procedure in the various features operate in one way.This advanced person's modulation satellite receiver can receive the communication from transmitter, and this transmitter also includes encoder.

Figure 16 is the schematic diagram according to a communication system of some feature of the present invention, and this system comprises a plurality of base stations and/or access point, a plurality of Wireless Telecom Equipment and the network hardware.This Wireless Telecom Equipment can be kneetop computer, PDA (personal digital assistant), PC (personal computer) and/or cell phone.Any one of these Wireless Telecom Equipments is described in more detail with reference to following Figure 17.

BS (base station) or AP (access point) connect by corresponding LAN (local area network (LAN)) and are connected with the network hardware.This network hardware connects for communication system provides WAN (wide area network), and it can be router, switch, bridge, modulator-demodulator, system controller and other.Each BS or Ap have the relevant antenna or the aerial array that communicate with Wireless Telecom Equipment in its zone.Generally, this Wireless Telecom Equipment signs in to a specific BS or AP to receive the service from communication system.For direct connection (that is, point-to-point communication), Wireless Telecom Equipment directly communicates by a channel appointed.

Usually, BS can be used for the system of cell phone system and similar type, and AP is used for the wireless network in indoor or the building.The special type of communication system no matter, each Wireless Telecom Equipment all comprises built-in wireless transmitter and/or is connected with wireless transmitter.This wireless transmitter comprises that highly linear amplifier and/or programmable casacade multi-amplifier are to strengthen the property, reduce cost, to reduce size and/or or enhancing broadband application.

Figure 17 is the schematic diagram according to a Wireless Telecom Equipment of some feature of the present invention, and this equipment comprises main frame and attached wireless transmitter.For the cell phone main frame, wireless transmitter is built-in parts.For PDA (personal digital assistant) main frame, kneetop computer and/or personal computer, this wireless transmitter can be built-in or external parts.

Shown in legend, main process equipment comprises processing module, memory, wireless transmitter interface, input interface and output interface.This processing module and memory are carried out the corresponding instruction of being made by main process equipment usually.For example, for the cell phone main process equipment, this processing module is carried out the corresponding communication function according to special cellular telephony standard.

This wireless transmitter interface allows to receive and send data to this wireless transmitter.For receiving data (as inbound data) from wireless transmitter, this wireless transmitter interface provide data to processing module with further processing and/or be sent to output interface.This output interface provides connection to output display unit, as display, monitor, loud speaker and other, so that the data that receive can be shown and suitably use.This wireless transmitter interface also provides data from processing module to wireless transmitter.Processing module can receive export-oriented data or self from input equipment by input interface and produce data, this input equipment such as keyboard, keypad, microphone and other.For the data that receive by input interface, processing module is carried out corresponding host function and/or is sent to wireless transmitter by the wireless transmitter interface on data.

Wireless transmitter comprises host interface, digital received processing module, ADC (analog to digital converter), filtering/gain module, IF mixing down conversion level, receiver filter, LNA (low noise amplifier), emission/reception change over switch, local oscillating module, memory, digit emitter processing module, DAC (digital to analog converter), filtering/gain module, IF mixing frequency up-conversion level, PA (power amplifier), reflector filtration module and antenna.This antenna can be the antenna that the shared single antenna of emission/reception and the transmission path of being controlled by Tx/Rx (emission/reception) switch and RX path are separated.The realization of this antenna depends on the special standard that Wireless Telecom Equipment is abideed by.

This digit receiver processing module and digit emitter processing module combine with the operational order that is stored in the memory, and correspondingly combine digital receiver function and digit emitter function.The digit receiver function comprises that digital IF (intermediate frequency) separates mapping to conversion, demodulation, the letter group of base band, decoding and/or descrambling, but be not limited only to these.The digit emitter function comprises the conversion to IF of scrambling, coding, letter group mapping, modulation and/or digital baseband, but is not limited only to these.

Similar to other employing encoder and the embodiment of decoder (or carrying out coding or decoding), the encoding operation that should carry out by the digit emitter processing module can be according to the present invention at least some functions in the various features and/or processing procedure carry out in one way, with help to produce will launch into communication channel that Wireless Telecom Equipment is connected in signal.Similarly, the decode operation of carrying out by the digit receiver processing module can be according to the present invention at least some functions in the various features and/or processing procedure carry out in one way.For example, the encoding operation that should carry out by the digit emitter processing module be carried out by utilizing described LDPC coding, and the decode operation of carrying out by the digit receiver processing module can be carried out by the utilization mode updating edge messages of running simultaneously.

Digit receiver and reflector processing module can be utilized shared processing equipment, individual processing equipment or a plurality of treatment facility and carry out.This treatment facility can be microprocessor, microcontroller, DSP (digital signal processor), microcomputer, CPU (CPU), FPGA (field programmable gate array), programmable logic device, state machine, logical circuit, analog circuit, digital circuit and/or any can be according to the equipment of the processing signals (simulation and/or numeral) of operational order.Such memory device can be ROM (read-only memory), RAM (random asccess memory) but, the equipment of volatile memory, nonvolatile storage, static memory, dynamic memory, flash memory and/or any storing digital information.Notice, when or digit receiver processing module or digit emitter processing module when carrying out one or more its function by static machine, analog circuit, digital circuit and/or logical circuit, the memory that stores corresponding operational order can be embedded into circuit, comprises static machine, analog circuit, digital circuit and/or logical circuit.

In operation, wireless transmitter receives export-oriented data by host interface from main process equipment.This host interface is sent to the digit emitter processing module with the data of output, and it handles export-oriented data to produce the data of digital delivery form according to a special wireless communication standard (as IEEE 802.11, bluetooth etc.).This digital delivery formatted data is digital baseband signal or the low IF signal of numeral, wherein, low IF usually at 100KHz (KHz) to the frequency range of several MHz (megahertz).

DAC is converted into analog domain with the digital delivery formatted data from numeric field.This analog signal is being provided to the IF mixed class filtering/gain module elder generation's filtering and/or adjust its gain.Based on the reflector local oscillations that provides by local oscillating module, this IF mixed class becomes the RF signal with Analog Baseband or low IF signal transformation.PA amplifies the RF signal, to produce export-oriented RF signal, its filtering by the transmitter filter module.Antenna is sent to target device with export-oriented RF signal, as base station, access point and/or another Wireless Telecom Equipment.

To the RF signal, this signal was by BS in wireless transmitter also received by antenna, AP or the emission of another Wireless Telecom Equipment.Antenna offers receiver filtration module with interior to the RF signal by the Tx/Rx switch, and wherein, Rx filter bandpass filtering should be interior to the RF signal.The Rx filter offers LNA with filtering RF signal, and LNA amplifies signal to produce amplify interior to the RF signal.LNA provides the RF signal of this amplification to the IF frequency mixing module, and this frequency mixing module interiorly is directly changed into introversive low IF signal or baseband signal to the RF signal based on what will amplify by the receiver local oscillations that local oscillating module provided.The down converted module offers filtering/gain module with low IF signal of introversion or baseband signal.This filtering/gain module filtering and/or the low IF signal of this introversion that gains or interior to baseband signal to produce the interior of filtering to signal.

This ADC is converted to numeric field with the interior of filtering to the signal from analog territory, to produce the digital received formatted data.In other words, produce discrete-time signal (receiving formatted data) therefrom to continuous time signal in this ADC sampling as numeral.This digit receiver processing module according to special wireless communication standard decoding, the descrambling carried out by wireless transmitter, separate mapping and/or this digital received formatted data of demodulation to obtain back inbound data again.The input data that host interface will be fetched by the wireless transmitter interface offer main process equipment.

The Wireless Telecom Equipment that persons of ordinary skill in the art may appreciate that Figure 17 can utilize one or more integrated circuits and realize.For example, this main process equipment can be realized on an integrated circuit, digit receiver processing module, digit emitter processing module and memory can be realized on second integrated circuit, the other parts (except that antenna) of wireless transmitter can realize on the 3rd integrated circuit.As an optional example, this wireless transmitter is realized on a single integrated circuit.As another example, the processing module of main process equipment and digit receiver and reflector processing module can be the shared treatment facilities of realizing on a single integrated circuit.Further, the memory of main process equipment and wireless transmitter also can be realized on a single integrated circuit and/or the same integrated circuit in the shared processing module of main process equipment processing module, digit receiver and the reflector processing module of wireless transmitter.

Figure 18 is the schematic diagram of the optional embodiment of a Wireless Telecom Equipment of institute's construction according to the present invention.The embodiment of this Wireless Telecom Equipment comprises an antenna that can communicate with one or more other Wireless Telecom Equipments.Antennal interface is being sent to suitable path (transmission path or RX path) from the signal of Wireless Telecom Equipment emission or the signal that is received by this Wireless Telecom Equipment.

The wireless transmitter front end comprises receiver function and transmitter function.This wireless transmitter front end is connected with A/D conversion function piece communication ground.This wireless transmitter front end is connected with modulator/demodulator communication ground, and this wireless transmitter is connected with channel coder/decoder communication ground.

Along RX path:

The receiver function of front end comprises LNA (low noise amplifier)/filter.As previously mentioned, this performed filtering in this receiver function can be counted as the filtering of limiting device performance.The down converted of any being required of receiver function executing of front end (comprising directly down converted alternatively) from the received signal frequency to base-band signal frequency.The operation of front end generally can comprise: receive continuous time signal, carry out the down converted of suitable filtering and any necessity to produce baseband signal.No matter adopt which kind of down converted mode, this baseband signal of sampling is exported and offered to baseband signal from the receiver function of front end, and (it also is continuous time signal, though on base band frequency) ADC (analog to digital converter), and produce discrete-time signal baseband signal (as the number format of baseband signal); This ADC also extracts and exports the I of discrete-time signal baseband signal, Q (homophase, quadrature) component.

These I, Q component are provided for the demodulator part of modulator/demodulator, can be to the I of discrete-time signal baseband signal, and Q component carries out any decode-regulating/symbol mapped.This suitable I then, Q component are mapped to suitable modulation (comprising letter group and corresponding mapping).For example, the modulation of this class can comprise BPSK (binary phase shift keying), QPSK (quaternary phase shift keying), 8PSK (octal system phase shift keying), 16QAM (16 ary quadrature amplitude), even the modulation type of high-order more.Then, these demodulation code elements are provided for the decoder section of channel coder/decoder device, make being included in the best estimate of the information bit in the continuous time signal that primary reception arrives at this.

Along transmission path:

With the RX path contrast, some similarly reaches opposite processing by performed in transmission path.Utilize the encoder in the channel coder/decoder that the information bit that will launch is encoded.The position of these codings is provided to the modulator in the modulator/demodulator, wherein, carries out modulating-coding/symbol mapped according to interesting modulation.The DAC (digital to analog converter) that the I of these code elements this moment, Q component are transferred into the analog/digital conversion functional block then is with I, and Q component is converted into the connect hours transmit (as analog signal).Transmit continuous time this moment and be transferred into the emission driver then, transmit driver to the connect hours transmit signal carry out any necessity up-conversion/corrections (as amplification and/or filtering) so that itself and communication channel match, on this communication channel, but signal is transferred into another piconet operating equipment by antenna.

As adopt other embodiment of encoder and decoder, the encoder of this Wireless Telecom Equipment can at least some functions and/or the processing procedure in the various features be encoded to information in one way according to the present invention, with help to produce will launch into communication channel that Wireless Telecom Equipment is connected in signal.The decoder of this Wireless Telecom Equipment according to the present invention at least some functions in the various features and/or processing procedure in one way the signal that receives is decoded.The figure shows another embodiment, wherein, one or more various features of the present invention can be found.

In addition, the following described several special embodiment of accompanying drawing can be used to carry out features more of the present invention, and it comprises adopting with running simultaneously decodes to ldpc coded modulation signal to the mode that the edge messages relevant with position piece node upgraded and relevant edge messages is upgraded with the check block node.Several detailed descriptions in these features are provided below.At first, provide LDPC the describe, in general terms of coding.

Figure 19 is the legend of a kind of embodiment of LDPC (low-density checksum) coding sign indicating number bipartite graph.LDPC coding can be looked at as the coding with binary parity check matrix so that nearly all matrix element be 0 value (as, the binary parity check matrix is sparse).For example, H=(h _{I, j}) _{M * N}Can be counted as the parity matrix of LDPC coding with block length N.If each of matrix is classified d as _v1 ' s, each behavior d of matrix _c1 ' s, this coding is called (d so _v, d _c) regular LDPC coding.For example, can be looked at as its binary parity check matrix be every row 41 ' s and every row 721 ' s for (4,72) LDPC of a rule coding.These regular LDPC are coded in " low-density checksum coding " of R.Gallager has introduction, Cambridge, publishing house of the Massachusetts Institute of Technology, 1963.

The LDPC coding of a rule can be expressed as a bipartite graph by its parity matrix, and the node on this bipartite graph left side is represented the variable of bits of coded, and right node is represented the verification equation.Coding bipartite graph by the H definition can define by N variable node and M check-node.Each variable node of N variable node has accurate d _vThe edge, it is connected to this node on one or more check-nodes (in M check-node).d _vThis quantity at edge can be called as the variable node degree.Similarly, each check-node of M check-node has accurate d _cThe edge, it is connected to this node on one or more variable nodes.d _cThis quantity at edge can be called as the check-node degree.

Variable node V _iAnd check-node C _jBetween the edge can pass through e=(i j) defines.Yet, on the other hand, suppose that (i, j), the node at this edge is represented as e=(v (e), c (e)) to an edge e=alternatively.A given variable node V _i, can define and pass through E _v(i)={ e|v (e)=i} is from node V _iThe edge group of emission.A given check-node C _j, can define and pass through E _c(j)={ e|c (e)=j} is from node C _jThe edge group of emission.Then, the result of derivation is | E _v(i) |=d _VAnd | E _c(j) |=d _c

An irregular LDPC coding also can be expressed as a bipartite graph.Yet the every group node degree in the irregular LDPC coding can be selected according to some distributions.Therefore, two different variable node V that encode for an irregular LDPC _I1And V _I2, | E _v(i ₁) | may be not equal to | E _v(i ₂) |.This relation is also set up for two check-nodes.The notion of irregular LDPC coding is at first at M.Lugy, M.Mitzenmacher, A.Shokrollahi, in K.Spielman and V.Stemann " actual reduction resilient coding " (" Practical loss-resilient codes ") introduction is arranged, IEEETrans.Inform.Theory, Vol.47, pp.569-584, February calendar year 2001.

In a word, the LDPC code pattern has been arranged, the parameter of LDPC coding can define by degree of distribution, as people such as M.Lugy (with reference to as mentioned above) and T.J.Richardson and R.L.Urbanke described in " message transmits the low-density checksum coding capacity under the decoding " (" The capacity of low-density parity-checkcode under message-passing decoding "), IEEE Trans.Inform.Theory, Vol.47, pp.599-618, February calendar year 2001.This distribution is as described below:

If λ _iFor emission edge mark, establish ρ from variable node degree i _iExpression is from the emission edge mark of check-node degree i, and so, degree distributes to (λ _i, ρ _i) may be defined as:

λ (x) = Σ_{i = 2}^{M_{v}} λ_{i} x^{i - 1} andρ (x) = Σ_{i = 2}^{M_{c}} ρ_{i} x^{i - 1},

Wherein, M _vAnd M _cThe very big node degree of representing variable node and check-node respectively.

A lot of embodiment described herein utilizes the example of regular LDPC coding, it should be noted that, the present invention is applicable to that promptly regular LDPC coding also is applicable to the abnormal LDPC coding.

LLR (the logarithm similar value is than (Log-Likelihood the Ratio)) decoding of LDPC coding can be as described below: when in fact 1 be launched, the actual calculated value of possibility that receives a position in the vector was 1.Similarly, when in fact 0 be launched, the actual calculated value of possibility that receives a position in the vector was 0.These possibilities of using the LDPC coding and calculating are used to the odd even that verification receives vector.LLR is the logarithm of the ratio of these two possibilities that calculate.LLR will be to the measuring to communication channel of out-degree, and signal transmits on communication channel, and the position in the vector is produced undesirable influence.

But the LLR decoding mathematics face of land of this LDPC coding is shown:

Start from C={v|v=(v ₀... v _N-1), vH ^T=0} is as LDPC coding and a reception vector, y=(y ₀... y _N-1), send signal and have form ((1) ^V01..., (1) ^VN-1), the matrix of channel can be defined as p (y so _i| v _i=0), p (y _i| v _i=1), i=0 ..., N-1.The LLR of a matrix can be defined as so:

L_{metric} (i) = \ln \frac{p (y_{i} | v_{i} = 0)}{p (y_{i} | v_{i} = 1)}

For each variable node v _i, its LLR value of information can be defined as:

\ln \frac{p (v_{i} = 0 | y_{i})}{p (v_{i} = 1 | y_{i})} = L_{metric} (i) + \ln \frac{p (v_{i} = 0)}{p (v_{i} = 1)}

Because variable node v _iIn a code word, these rate values so,

\ln \frac{p (v_{i} = 0)}{p (v_{i} = 1)},

Can be expressed from the next:

\ln \frac{p (v_{i} = 0, {vH}^{I} = 0 | y)}{p (v_{i} = 1, {vH}^{T} = 0 | y)} = \underset{(i, j) = E_{v} (i)}{Σ} \ln \frac{p (v_{i} = 0, {vh}_{j}^{T} = 0 | y)}{p (v_{i} = 1, {vh}_{j}^{T} = 0 | y)}

Wherein, E _v(i) be the aforesaid v that starts from _iOne group of edge.

When under this situation, when carrying out BP (reliability propagation) decoding coding mode, so

\ln \frac{p (v_{i} = 0, {vh}_{j}^{T} = 0 | y)}{p (v_{i} = 1, {vh}_{j}^{T} = 0 | y)}

Value can represent by following relation:

L _Check(i j) is known as about edge (i, check-node C j) _jEXT (outside) information.

In addition, notice e ∈ E _e(i) { { i, j}} represent that all are from check-node C _jThe edge of emission is except from check-node C _jBe emitted to variable node V _iThe edge.The external information value can be counted as those calculated values to help to produce the best estimate that receives the actual place value in the vector.Equally, in a BP mode, about edge (i, variable node V j) _iExternal information can be defined as:

From certain aspect, the present invention can implement in the communication system that comprises in conjunction with the modulating-coding with LDPC coding, to produce the modulation signal of LDPC coding.The modulation signal of these LDPC codings can have encoding rate and/or the modulation (letter group and mapping) of a change frequency with the code element on the code element basis.Up to the present, aspect the LDPC coding combines, done some at modulating-coding and attempted, but these attempt all being confined to only adopt consequent single encoding rate or modulation (letter group and mapping) code element.But, some will be described modulating-coding following with the possible scheme that the LDPC coding combines.In addition, the different schemes that the code element of the ldpc coded modulation signal that uses no gray scale coding mapping code is decoded also will be described,

Figure 20 is a legend of using LDPC (low-density checksum) the coded modulation decoding function of position yardstick according to of the present invention.For the ldpc coded modulation signal with m position burst is decoded, can adopt the function among this figure.After I, the Q of symbol node place received signal (homophase, quadrature) value, a m bit symbols yardstick calculator function piece calculates corresponding code element yardstick.In this symbol node, these code element yardsticks then can be transferred into symbol node calculator function piece, and this symbol node calculator function piece uses the position yardstick of these code element yardsticks that receive calculating corresponding to those code elements.These yardsticks then are transferred into the position node that is connected with symbol node.

After this, node on the throne place, position node computer functional block is calculated the soft information in corresponding position.Then, handle according to iterative decoding, position node computer functional block receives edge messages from check-node operating function piece, and upgrades from the edge messages of the position yardstick that symbol node calculator function piece receives.After being updated, these edge messages are transferred into check-node operating function piece.

At check node, check-node operating function piece then receives these edge messages from position node (from position node computer functional block), and correspondingly they is upgraded.The edge messages of these renewals then be transmitted the return node (as, be sent to a node computer functional block), use the current iteration value of position yardstick and edge messages to calculate the soft information of position at this node place.After this, utilize the soft information of this position of just having calculated (being shown soft information), position node computer functional block is used the previous value of edge messages (from previous iteration of just having carried out) and the soft information updating edge messages that has just calculated.This iterative process is encoded according to LDPC and is proceeded between bipartite graph node on the throne and the check-node, and this LDPC coding bipartite graph once was utilized to just encoding at decoded signal.

By position node computer functional block and these performed iterative decoding treatment steps of check-node operating function piece, by predefined number of iterations be repeated (as, repeat n time, wherein n is optional).Alternatively, these iterative decoding treatment steps repeat, and the syndrome (syndromes) of encoding up to LDPC is equal to 0 (in a certain accuracy).

During each decoding iteration, produce soft output information in the node computer functional block of position.In the present embodiment, this soft output can be provided for the hard limiter that can make hard decision, and this hard information can be provided to syndrome (syndrom) calculator and whether equal 0 (in a certain accuracy) all with the syndrome that determines LDPC.That is to say on some predefined accuracy, whether each syndrome related with the LDPC coding all equals 0 in fact in this syndrome calculator decision.For example, when syndrome has a mathematical nonzero value, it thinks so that less than the defined threshold value of predefined accuracy this syndrome equals 0 in fact.When syndrome has a mathematical nonzero value, it thinks so that greater than the defined threshold value of predefined accuracy this syndrome is not equal to 0 in fact.

When syndrome was not equal to 0 in fact, by suitably transmitting edge messages between renewal and node computer functional block on the throne and the check-node operating function piece, this iterative decoding was handled and is proceeded once more.

After all these iterative processing steps executed, the best estimate of position was output based on the soft information in position.In the method for this embodiment, the position scale-value of calculating by symbol node calculator function piece is a fixed value, and is repeated to use in updated space nodal value process.

Figure 21 is the legend (when carrying out n iteration) according to a kind of embodiment of the LDPC coded modulation decoding function of use of the present invention position yardstick.This embodiment shows when predefined decoding iterations (being depicted as n) when being performed, and this iterative decoding is handled and how to be carried out.If this iterations is known in advance, as in the embodiment of precognition decoding iterations, this node computer functional block utilizes its yardstick itself that its respective edges message (not being the soft information of last embodiment and aforesaid position) is upgraded so.This processing can all decoding iteration except last iteration (as, iteration 1 is to n-1) in carry out.Yet the last time in the iteration, position node computer functional block is calculated the soft information (shown in soft output) of position.This soft output provides then to a hard limiter, and this hard limiter is made the hard decision of position.In the present embodiment, owing to only carry out the decoding iteration of pre-determined number, thereby do not need to calculate syndrome.

Figure 22 is a legend of using LDPC (low-density checksum) the coded modulation decoding function of position yardstick (having a yardstick upgrades) according to of the present invention.For execution has the decoding of the ldpc coded modulation signal of m position burst, the function in this legend may be utilized.Receive I, Q (homophase, the quadrature) value of a signal at the symbol node place after, m bit symbols yardstick calculator function piece calculates corresponding code element yardstick.At the symbol node place, these code element yardsticks then are transferred into symbol node calculator function piece, and this functional block is used the position yardstick of the code element yardstick calculating of these receptions corresponding to those code elements.These yardsticks then are transferred into the position node that links to each other with symbol node.This symbol node calculator function piece also can upgrade by the contraposition yardstick during decoding iteration subsequently.

After this, node on the throne place, position node computer functional block is calculated the soft information of corresponding position.Then, according to the iteration encoding process, position node computer functional block receives edge messages from check-node operating function piece, utilizes from the position yardstick that symbol node calculator function piece receives and comes updating edge messages.During iteration subsequently, the renewal of edge messages can utilize the position yardstick after the renewal and carry out.After being updated, these edge messages then are transferred into check-node operating function piece.

At check node, check-node operating function piece then receives these edge messages from position node (from position node computer functional block) and reaches correspondingly with they renewals.These edge messages that are updated then are transmitted return node (as to position node computer functional block), wherein, utilize the position yardstick to calculate the soft information of position and the current iteration value of edge messages.After this, use the soft information (soft information as shown in the figure) of this position of just having calculated, position node computer functional block utilizes the previous value (from previous iteration) of edge messages to reach calculated soft information updating edge messages just.Simultaneously, because the soft information (soft information as shown in the figure) of position is just calculated, this information can be transferred back to symbol node (as symbol node calculator function piece) with the updated space yardstick, and it will be used in decoding iteration subsequently.This iterative process is according to proceeding (also by adopt the position yardstick that upgrades during decoding iteration subsequently) between LDPC coding bipartite graph node on the throne and the check-node, this LDPC coding bipartite graph once was utilized to just encoding at decoded signal.

By position node computer functional block and check-node operating function piece, the iterations that these iterative decoding treatment steps repeat to be scheduled to (as repetition n time, wherein n is optional).Alternatively, these iterative decoding treatment steps repeat, and the syndrome of encoding up to LDPC is equal to 0 (in a certain accuracy).

During each decoding iteration, position node computer functional block produces soft output information.In the present embodiment, this soft output can be provided for the hard limiter that can make hard decision, and this hard information can be provided to the syndrome calculator, whether equals 0 (in a certain accuracy) all with the syndrome that determines LDPC.When they were not equal to 0, by suitably transmitting edge messages between updating edge messages and node computer functional block on the throne and the check-node operating function piece, this iterative decoding was handled and is proceeded once more.

After all these iterative decoding treatment steps execute, the best estimate of position is exported based on the soft information in position.In the method for this embodiment, the position scale-value of being calculated by symbol node calculator function piece is a fixed value, and reuses when the updated space nodal value.

Figure 23 is the legend according to a kind of optional embodiment of LDPC (low-density checksum) the coded modulation decoding function of a use of the present invention position yardstick (having a yardstick upgrades).This embodiment shows to handle when this iterative decoding of predefined coding iterations (being depicted as n) when being performed (again, when adopting the position yardstick to upgrade) and how to carry out.If the known in advance iterations of should decoding, as the predefined embodiment of the iterations of decoding, use its yardstick/updated space yardstick itself so, this node computer functional block can be upgraded (the soft information that is not last embodiment and above-mentioned position) to its respective edges message.This processing can all decoding iteration except last iteration (as, iteration 1 is to n-1) in carry out.Yet the last time in the iteration, position node computer functional block is calculated the soft information (shown in soft output) of position.This soft output provides then to a hard limiter, and this hard limiter is made the hard decision of position.In the present embodiment, owing to only carry out the decoding iteration of pre-determined number, thereby do not need to calculate syndrome.

Figure 24 A is a legend of using the position decoding of position yardstick (shown in LDPC (low-density checksum) coding bipartite graph) according to of the present invention.Generally speaking, receive the I of a signal at the symbol node place, after the Q value, calculate m bit symbols yardstick.Then, at the symbol node place, use the code element yardstick to calculate the position yardstick.The position yardstick then is transferred into the position node that is connected with symbol node.The soft information of position is calculated at node on the throne place, uses soft information to upgrade the edge messages from the check-node with yardstick.These edge messages then are transferred into check-node.At check node, the edge messages of coming the self-alignment node to be upgraded, these values are transmitted the return node.

As above-mentioned embodiment, after all these iterative decoding treatment steps execute, the best estimate of position is exported based on the soft information in position about corresponding function.In the method for this embodiment, the position scale-value of being calculated by symbol node calculator function piece is a fixed value, and reuses when the updated space nodal value.

Figure 24 B is a legend of using the position yardstick to upgrade the position decoding of (shown in LDPC (low-density checksum) coding bipartite graph) according to of the present invention.About the LDPC coding bipartite graph that this contraposition yardstick upgrades, decoding processing can be carried out as follows:

Receive the I of signal at the symbol node place, after the Q value, calculate m bit symbols yardstick.Then, at the symbol node place, use the code element yardstick to calculate the position yardstick.These values then are transferred into the position node that is connected with symbol node.Node on the throne place, with the edge messages of position yardstick renewal from check-node, these edge messages are transferred back to check-node.In addition, a simultaneously soft information is updated and is transferred back to symbol node.At the symbol node place, be used for information updating position, the soft position yardstick of self-alignment node.At check node, come the marginal information of self-alignment node to be updated, these information are transmitted the return node.

As above-mentioned embodiment, after all these iterative decoding treatment steps execute, based on the soft information in position, the best estimate of carry-out bit about corresponding function.Again, in the method for this embodiment, the position scale-value is fixed value not; The updated space scale-value is so that use in decoding iteration subsequently.The position scale-value of this and previous embodiment is only calculated reaches once that to keep fixed value distinct once more into all decoding iteration.

Figure 25 A has a legend that symbol node is connected to LDPC (low-density checksum) coded modulation three components of a node according to of the present invention.In this embodiment, the position node is connected on the symbol node as can be seen.According to the LDPC coding that just is being used, suitable corresponding positions node also is connected on the check-node.Yet, notice that the code element of wanting decoded is determined individually by the position that is connected to respective symbol.Utilize this characteristic so that a position node can be removed from LDPC three components, and then symbol node can directly be connected to check-node, produces LDPC coded modulation bipartite graph thus.

As described in an example, 3 symbol node s ₀, s ₁, s ₂, be connected to 9 position node b ₀, b ₁, b ₂..., b ₈, according to following mapping:

s_{0} &LeftRightArrow; (b_{0}, b_{3}, b_{8})

s_{1} &LeftRightArrow; (b_{1}, b_{4}, b_{7}) - - - (EQ 1)

s_{2} &LeftRightArrow; (b_{2}, b_{6}, b_{8})

According to following mapping, can obtain 9 position node b ₀, b ₁, b ₂..., b ₈With 3 check-node c ₀, c ₁, c ₂Between connection:

b_{0} &LeftRightArrow; (c_{0}, c_{2})

b_{1} &LeftRightArrow; (c_{0}, c_{1})

b_{2} &LeftRightArrow; (c_{1}, c_{2})

b_{3} &LeftRightArrow; (c_{0}, c_{1})

b_{4} &LeftRightArrow; (c_{1}, c_{2})

b_{5} &LeftRightArrow; (c_{0}, c_{2})

b_{6} &LeftRightArrow; (c_{0}, c_{1})

b_{7} &LeftRightArrow; (c_{1}, c_{1})

b_{8} &LeftRightArrow; (c_{0}, c_{1})

Figure 25 B has a legend (this bipartite graph is produced by three components of Figure 25 A) that symbol node is connected directly to LDPC (low-density checksum) the coded modulation bipartite graph (or code element bipartite graph) of a node according to of the present invention.A feature of the present invention be can by directly symbol node is connected to check-node (as, by change LDPC coded modulation three components to produce a LDPC coded modulation bipartite graph), to reduce the quantity of node in the LDPC bipartite graph.Yet, must carry out very carefully to guarantee being correctly decoded of this ldpc coded signal.As described herein, the mark symbol node need be carried out carefully with being connected of check-node, to guarantee being correctly decoded of code element.

In this LDPC coding bipartite graph, the edge only is connected between symbol node and the check-node.In this case, the edge of each connection symbol node and check-node is labeled by the value of basis EQ1 as previously shown.In certain embodiments, these edges utilize the octal system value and are labeled.

For example, use the octal system labeling method, connect symbol node s ₀With check-node c ₀The edge (be expressed as (s ₀, c ₀)) be marked as 7, because three position b ₀, b ₃, b ₆All be connected to c ₀(as, because b ₀, b ₃, b ₆=111 and be marked as 7).Similarly, connect symbol node s ₀With check-node c ₁The edge (be expressed as (s ₀, c ₁)) be marked as 6, because two position b are only arranged ₀, b ₃Be connected to c ₁(as, because b ₀, b ₃, b ₆=110 and be marked as 6).As another embodiment, connect symbol node s ₀With check-node c ₂The edge (be expressed as (s ₀, c ₂)) be marked as 1, because a position b is only arranged ₀Be connected to c ₂(as, because b ₀, b ₃, b ₆=100 and be marked as 1).According to this rule, the edge that other communication ground connects symbol node and check-node also can be labeled.

Symbol node a to advantage of the LDPC coding bipartite graph of check-node is that when carrying out the decoding processing of LDPC code symbols, decoder can use the code element yardstick and replace a yardstick.Thereby in the method for this execution decoding processing, do not need to carry out yardstick and upgrade; Yardstick in the decoding processing upgrades and has undesirable influence, promptly requires to increase the quantity of the memory that uses.And, in fact surpassed (out-perform) based on the encode execution of decoding processing of three components (its node is connected on the check-node) of LDPC based on the decoding of LDPC coding bipartite graph (being sometimes referred to as code element LDPC coding bipartite graph).In addition, the LDPC symbol decoding can provide the LDPC position decoding more performance that needs the updated space yardstick than comprising.

Figure 26 A is the legend according to symbol decoding of the present invention (shown in LDPC (low-density checksum) coded modulation bipartite graph).Performed symbol decoding processing can be used LDPC coded modulation bipartite graph and carry out according to the present invention, and the symbol node in this bipartite graph is connected directly to check-node.In a word, provide the I of code element, the Q value is carried out iterative decoding according to a method and is handled to symbol node, and in the method, the communication ground, edge of mark connects symbol node to check-node.

Use such LDPC coded modulation bipartite graph to carry out in the example of decoding processing how, LDPC coding, 8PSK (octal system phase shift keying) modulation signal of 2/3 encoding rate are decoded, and made a detailed description.This LDPC coding can be regular LDPC coding, or irregular LDPC coding, and does not depart from the scope of the present invention and spirit.The block length of LDPC coding is 3N, one 3 bit symbols s _iAccording to following representation mapped (as, use symbol mapper):

s _i＝(b ₁，b _N+i，b _2N+i)

The parity matrix of LDPC coding can be represented as [h ₁] _{N * 3N}Corresponding to this 3 bit symbols s _iEstimated symbol r _iCan be expressed as r ₁=(r ₀₁, r ₁₁, r ₂₁).Use the code element and the parity matrix of the estimation of LDPC coding, the syndrome S of part ^m(i) and S _m(i) (be commonly referred to syndrome and be referenced, as mentioned in other embodiments) can be calculated by following formula:

Below, so that burst Y is carried out decoding processing this processing procedure is described.As calculated, satisfy the Probability p (S of the burst Y of part syndrome ⁱ(i)=m|Y) equal A _{I, j}(m) (as, Probability p (S ⁱ(i)=m|Y)=A _{I, j}(m)).In addition, other probability also can calculate; In other words, satisfy the Probability p (S of the burst Y of part syndrome _j(i)=m|Y), equal B as calculated _{I, j}(m) (as, Probability p (S _i(i)=m|Y)=B _{I, j}(m)).These probability all calculate based on following condition:

Because decoding can be carried out in log-domain, therefore can use addition to carry out multiply operation, and use subtraction to carry out divide operations, these variablees can be redefined in following log-domain:

α _i，j(m)＝log(A _i，j(m))

β _i，j(m)＝log(B _i，j(m))

These values can be described as the yardstick (α of α or front _{I, j}(m)), and the yardstick of β or back, (β in decoding processing, adopted _{I, j}(m)).

The edge messages that is transferred into symbol node from check-node can be expressed as Medge[i] [j] [k], wherein, i changes according to the edge of suitable mark in the LDPC coded modulation bipartite graph.

As some examples:

1. if be labeled as 7, k from 0 to 7 changes so,

2. if be labeled as 3,5 or 6, k from 0 to 3 changes so, and

3. if be labeled as 1,2 or 6, k is 0 to 1 variation so.

In addition, can adopt one from 0 ..., 7} is to { 0,1} and the new function x that changes are (v).Value v can be counted as an integer with octal representation.So, value v can be expressed as v=(v ₀, v ₁, v ₂).This new function x (v) can be expressed as follows:

x (v) = v_{0} &CirclePlus; v_{1} &CirclePlus; v_{2} - - - (EQ 3)

Wherein Be exclusive OR function (as, binary addition).

Also available in other embodiments symbol decoding processing of symbol that uses above and definition is described, and its decoding process and/or function will be described in detail below.More particularly, below the embodiment that will discuss describes in detail and how to utilize these different values to carry out check-node renewal and sequence of symhols estimation, and symbol node is upgraded.

Figure 26 B is the legend according to a kind of embodiment of symbol decoding function of the present invention (being supported by LDPC (low-density checksum) coded modulation bipartite graph).This embodiment illustrates in greater detail how to carry out check-node renewal and sequence of symhols estimation, and symbol node is upgraded.

Estimate in check-node renewal and sequence of symhols under the situation of (comprising the symbol node renewal), decoding processing described in this embodiment can be understood better, and it can carry out (1) symbol decoding and (2) hybrid decoding (combination of its execute bit layer and code element layer decoder) at least two different embodiment described herein according to the present invention.This figure (Figure 26 B) has described a possible embodiment of symbol decoding, and the embodiment of various possible hybrid decodings carried out will be described below will being shown in according to all the other that are disclosed.

From the left side of this figure,, also comprise value α (α corresponding to the input information of calculated part syndrome _{I, j}And β (β (m)) _{I, j}(m)) (as, to before and after to yardstick) initial value, provide to check-node update functions piece.In check-node update functions piece, the sum of check-node is carried out iterative decoding from the beginning to the end handle.For example, i is carried out M iteration (wherein i changes, and M is the sum of the check-node of LDPC bipartite graph) from the beginning to the end between 0 to M-1.

In carrying out this iteration encoding process process, this check-node upgrades each the code element calculated value α (α that is included as the block of symbols that receives at first _{I, j}And β (β (m)) _{I, j}(m)) (only surpass the initial value that is provided during the initial iteration).The iterative decoding of this calculating α and β is handled and can be used forward direction-back to carry out to handling procedure to the block of symbols that receives.

Being calculated as follows of α and β is described.

For j=0 to deg (c ₁)-1 and m=0,1, can adopt this forward direction-back to calculate α (a to handling procedure _{I, j}And β (β (m)) _{I, j}(m)), as follows:

α_{i, j} (m) = \min * {Medge [i] [j - 1] [k] + α_{i, j - 1} (m &CirclePlus; x (k)) | all possiblek}

β_{i, j} (m) = \min * {Medge [i] [j + 1] [k] + β_{i, j + 1} (m &CirclePlus; x (k)) | all possiblek}

Since these α of each code element and the value of β can get in the block of symbols that receives, utilize the renewable edge messages Medge[i of value of these α that calculate and β] [j] [k] (its communication ground connects symbol node and check-node).

For j=0 to deg (c ₁)-1 and all possible k can be calculated as follows edge messages Medge[i] renewal of [j] [k]:

This min* processing capacity described herein can be better understood by following description.This min* handle comprise from two values (as, determine a minimum value at the min (A, B)) of min* shown in handling, and in selecting less yardstick, determine a logarithm modifying factor (as, the lh (1+e shown in the min* processing ^{-| A-B|})).In addition, also notice, can select to use max* to handle and replace min* to handle.This max* handles the logarithm correction that is also included within the bigger yardstick of selection.Notice when in given execution mode, carrying out when preferred the min* operation that various embodiment of the present invention can adopt max* to operate to replace.

When input A and B were operated, min* handled and can be expressed as follows:

min*(A，B)＝min(A，B)-ln(1+e ^-|A-B|)

Again, this min* handles and can use max* to handle to replace.When input A and B were operated, this max* handled and can be expressed as follows:

max*(A，B)＝max(A，B)+in(1+e ^-|A-B|)

And, when a plurality of values (as, above 2) when go up carrying out a plurality of min* operation, this min* handles and can be expressed as follows:

mln*(x ₁，...，x _N)＝min＊(min＊(x ₁，...，x _N-1)，x _N) (EQ?4)

After finishing code check node processing, sequence of symhols is estimated and symbol node update functions piece utilizes this check-node updating message to operate to continue this decoding processing.

Since the sum at edge on both sides (as, from the symbol node limit and from the check-node limit) be the same, this edge basis just is rearranged preface naturally in decoded code element.This reorders and can use LUT (check table (Look-Up Table)) to be carried out naturally, with the correct order of guaranteeing that check-node upgrades.In other words, when estimation of actuating code metasequence and symbol node renewal, can use LUT to carry out the function that edge messages is brought.In addition, for the check-node that correctly sorts upgrades, this reordering function can be implemented in hardware inherently, so that its order of upgrading corresponding to a suitable symbol node.For to sequence (as, first code element is to a last code element) code element is correctly decoded, need sorts to code element.Yet when carrying out the check-node renewal, this code element ordering is not crucial.That is to say, then, the ordering that check-node upgrades can be carried out according to any ordering of wanting, according to this order of wanting (as, first code element is to a last code element) to guarantee correct symbol decoding, carry out this check-node and upgrade, can suitably be sorted inherently according to the required order of this decoding processing to guarantee edge messages.

More particularly,, discuss edge messages Medge[i for the ease of understanding] decoding processing of [j] [k], wherein i is to all symbol node values, and j is according to the edge degree of symbol node and value, and k is according to the mark of LDPC bipartite graph and value.

The description of this embodiment shown in this figure is about comprising the code element coding of 3 positions, modulating according to 8PSK (octal system phase shift keying) and encode.Yet, notice that this coding/decoding method can be used for the signal with bigger figure place is decoded equally at an easy rate.For example, can adopt this coding method to carry out to having the more decoding of the signal of high order modulation code element, this modulation comprises 16QAM (16 quadrature amplitude modulation), 16APSK (16 asymmetric phase shift keyings), 64QAM and other modulation type and do not depart from the scope of the present invention and spirit.

Mark on the j of check-node i can be decided to be L _{I, j}(L v) can be defined and adopt a new function sh, to help decoding processing described herein.This new sh (L v) can be defined as follows:

sh (L, (v_{0}, v_{1}, v_{2})) = \{\begin{matrix} v_{2} & L = 1 \\ v_{1} & L = 2 \\ (v_{1}, v_{2}) & L = 2 \\ v_{0} & L = 4 \\ (v_{0}, v_{2}) & L = 5 \\ (v_{0}, v_{1}) & L = 6 \\ (v_{0}, v_{1}, v_{2}) & L = 7 \end{matrix} - - - (EQ 5)

When use said method with edge messages inherently (intrinsically) and suitably reorder after, sequence of symhols is estimated and symbol node update functions piece continues operation according to subsequent step.

For m=0 ..., 7, the probable value of soft symbol estimation can be calculated as follows (as, calculate the probable value of the soft information of code element):

p_{1} (m) = Metri c_{1} [m] + Σ_{j = 0}^{\deg (c_{1}) - 1} (\underset{{Li}_{, j}}{Σ} Medge [i] [j] [sh (L_{i, j}, m)]),

Wherein, Metric ₁[m] suitable code element yardstick for from received signal, being obtained according to suitable modulation (letter group and mapping value).

By adopting soft symbol estimation value that code element is estimated, sequence of symhols is estimated and symbol node update functions piece continues operation.More particularly, make code element s _iTo the estimation of m, so that p ₁(m) be from all probable value p ₁(0), p ₁(1) ..., p ₁(7) in one of selected minimum.

After the soft symbol estimation of use is estimated code element, use old edge messages updating edge messages in sequence of symhols estimation and symbol node update functions piece.More particularly, edge messages is updated as follows:

For the ease of understanding this processing procedure, to the edge label L _{I, j}Discuss:

1. if L _{I, j}=7, so for m=0 ..., 7,

Medge[i][j][k]＝p ₁[m]-Medge[i][j][k]。

2. alternatively, if L _{I, j}=3,5,6, so for m ₀, m ₁∈ 0, and 1}, the value of edge messages can be defined as follows:

Medge [i] [j] [(m_{0}, m_{1})]

= \{\begin{matrix} \min * (p_{1} (0, m_{0}, m_{1}), p_{1} (1, m_{0}, m_{1})) - Medge [i] [j] [(m_{0}, m_{1})] & L_{i, j} = 3 \\ \min * (p_{1} (m_{0}, 0, m_{1}), p_{1} (m_{0}, 1, m_{1})) - Medge [i] [j] [(m_{0}, m_{1})] & L_{i, j} = 5 \\ \min * (p_{1} (m_{0}, m_{1}, 0), p_{1} (m_{0}, m_{1}, 1)) - Medge [i] [j] [(m_{0}, m_{1})] & L_{i, j} = 6 \end{matrix}

3. alternatively, if L _{I, j}=1,2,4, so for m=0,1, the value of edge messages can be defined as follows:

Medge [i] [j] [(m)]

= \{\begin{matrix} \min * {p_{1} (k_{0}, k_{1}, m) | k_{0}, k_{1} &Element; {0,1}} - Medge [i] [j] [m] & L_{i, j} = 1 \\ \min * {p_{1} (k_{0}, m, k_{1}) | k_{0}, k_{1} &Element; {0,1}} - Medge [i] [j] [m] & L_{i, j} = 2 \\ \min * {p_{1} (m, k_{0}, k_{1}) | k_{0}, k_{1} &Element; {0,1}} - Medge [i] [j] [m] & L_{i, j} = 4 \end{matrix},

Wherein, the old edge messages of the right of these equatioies for sending out by check-node.

The edge messages of use upgrading (its be updated a predefined number of times and/or in edge messages is converged in a certain accuracy) continues iterative decoding to be handled, and obtains the code element best estimate of receiving symbol piece then.

Figure 27 is the legend according to a kind of embodiment of the hybrid decoding function of LDPC of the present invention (low-density checksum) modulation signals (relatively having reduced complexity with symbol decoding).Hybrid decoding shown in this embodiment is handled and can be counted as up to the present in the modification of preceding described decoding processing scheme (as, change).Total, shown in the symbol decoding embodiment as previously described, in handling, adopts iterative decoding similar decoding function piece, and still, the method for operation of these functional blocks is different; These differences provide the coding/decoding method than low-complexity, and (following visible performance comparison) hybrid decoding method about various coding/decoding methods on performance, also have significant improvement (as, when only with position when contrast decoding).

This hybrid decoding function is by receiving the I of received signal, Q value and beginning., utilize this I thereafter, the Q value, m bit symbols yardstick calculator function piece calculates corresponding code element yardstick.Equally, a functional block is carried out the edge messages initialization of LLR (likelihood relationship degree) position to be used for the iteration of decoding for the first time; This initialization only need be carried out once.If desired, for first iteration (as, iteration i=0), this initial LLR position edge messages initialization value can be 0.From these functional blocks, code element yardstick and initialized LLR position edge messages are transferred into the iterative decoding function blocks, and this iterative decoding function blocks comprises that check-node update functions piece and sequence of symhols are estimated and symbol node update functions piece.In decoding iterative process the first time that iterative decoding is handled, sequence of symhols estimation and symbol node update functions piece use the initial condition (or initial value) and the code element yardstick of these LLR position edge messages.

This check-node update functions block operations method and the aforesaid check-node operating function piece about LDPC coded modulation decoding function of position two time scales approach (as Figure 20) that uses have similarity.In a word, this check-node functional block is to upgrading from the edge messages that sequence of symhols is estimated and symbol node update functions piece receives.This sequence of symhols is estimated and symbol node update functions piece (the hybrid decoding method) is estimated with those sequence of symhols and symbol node update functions piece (the symbol decoding method) is inequality.

When carrying out the renewal of edge messages in check-node update functions piece, the position edge messages contraposition edge messages of the renewal that the last iteration of this check-node update functions piece utilization hands down is upgraded.In the iterative process of decoding for the first time, can comprise the initial value that uses the position edge messages.Yet during iterative decoding was handled, the edge messages that check-node update functions piece will upgrade was sent to sequence of symhols and estimates and symbol node update functions piece.

Again, notice that sequence of symhols is estimated and symbol node update functions piece in its iterative decoding is handled first time iteration, use the initial condition of LLR position edge messages.It also in the iteration subsequently that iterative decoding is handled, uses the code element scale-value that receives at first.This sequence of symhols is estimated and symbol node update functions BOB(beginning of block) calculating possible soft symbol estimation.Then, this sequence of symhols estimation and symbol node update functions piece use the renewal of this information to help edge messages.More particularly, this sequence of symhols is estimated and symbol node update functions piece uses the code element yardstick (from m bit symbols yardstick calculator) that calculates, in conjunction with the position edge messages that the last iteration from check-node update functions piece sends, the contraposition edge messages is upgraded.From considering on the one hand, it has shown the hybrid decoding function, this mode (as described below equally) that position layer information and code element layer information are used in combination, compare with the symbol decoding method among some embodiment and can have good equally performance, it is easier also can to make complexity significantly reduce, carry out simultaneously.Usually, the hybrid decoding method is compared with symbol decoding, and its performance is good equally, and is perhaps weaker; But, compare with the symbol decoding method, the easier enforcement of hybrid decoding method (as, processing, memory and storage administration resource significantly reduce).

Iterative decoding is handled between sequence of symhols estimation and symbol node update functions piece and check-node update functions module and is proceeded, so that reaching alternatively (alternatively) constantly, continuously, edge messages upgrades, with the end value that converges on an edge messages (perhaps after the iteration of carrying out pre-determined number, perhaps reach enough accuracy and position edge messages and converged on after the end value, it has enough accuracy).For the renewal that sequence of symhols is estimated and symbol node update functions piece carries out, its renewal is continuous and optional, and subsequently, check-node update functions module is upgraded, and the iterative decoding processing procedure is then proceeded.

In the iteration of in the end decoding, use the possible soft symbol estimation that has calculated, code element is estimated by sequence of symhols estimation and symbol node update functions piece.This soft symbol estimation then exports hard limiter to from sequence of symhols estimation and symbol node update functions piece, and this hard limiter can determine firmly to each position in this soft symbol estimation.This final output can be counted as each individual bits of the position in the code element of decoding according to the hybrid decoding method and estimate.That is to say that hard limiter is made the position estimation based on best estimate for each code element, so that the position estimation is the hard decision of each individual bits of those corresponding code elements.

(with reference to shown in Figure 27) in one embodiment, estimate and symbol node update functions piece, check-node update functions piece by sequence of symhols, these iterative decoding treatment steps by predetermined iterations repeat (as, repeat n time, wherein n is optional).

Figure 28 is the legend according to the another kind of embodiment of the hybrid decoding function of LDPC of the present invention (low-density checksum) modulation signals (complexity reduces when comparing with symbol decoding).In this optional execution mode, repeat these iterative decoding treatment steps and all equal 0 (in a certain accuracy) until the syndrome of LDPC coding.As previously mentioned, soft symbol estimation is estimated by sequence of symhols and the generation of symbol node update functions piece.This soft output information can be provided to the hard limiter of making hard decision, and this hard information can be provided to the syndrome calculator, whether is equal to 0 (in a certain precision degree) with the syndrome of determining the LDPC coding.When it is not 0, a syndrome verification failure signal will provide to iterative decoding function blocks (and when having determined that this decoding iteration is not when decoding iteration for the last time), this iterative decoding is handled and is proceeded once more by suitable renewal, and transmits this edge messages between check-node update functions piece and sequence of symhols estimation and symbol node update functions piece.After all these iterative decoding treatment steps are finished, then, based on soft symbol estimation, the best estimate of carry-out bit.Notice that equally when the syndrome of LDPC coding does not converge on 0 (in a certain precision degree) in fact, and the iteration of decoding at last is when in fact executed is intact, can carry out some other decision and/or operation.

Above-mentionedly shown to have at least two kinds of possible modes can realize the hybrid decoding method, to allow using position layer and code element layer both information (thereby being called mixing) that ldpc coded signal is decoded about the function diagram shown in Figure 27 and Figure 28.

How to all kinds ldpc coded signal (as, comprise direct forward direction ldpc coded signal, ldpc coded modulation signal, the LDPC variable modulation signal, LDPC variable coding rate signal, or the like) the several different embodiment that decodes, the coding/decoding method that each of this ldpc coded signal is different can have benefited from the treatment characteristic of running simultaneously of updating edge messages.At first, introduce the method for LDPC position-verification parallel decoding.To the LDPC of each other type decoding (as, only position decoding (having a yardstick upgrades), symbol decoding and hybrid decoding) also introduce, with the characteristic of running simultaneously and handling of explanation updating edge messages.

Introduce before some details of this novel coding/decoding method, introduce some features of parallel block ldpc coded signal earlier.Notice that a typical position ldpc coded signal also can be counted as the parallel ldpc coded signal (from the viewpoint of parallel block ldpc coded signal) of piece of each piece with single-element.

In various types of communication systems (foregoing several), use an advantage of ldpc coded signal to be that the iterative decoding of ldpc coded signal handles and can parallel mode carry out.That is to say that position node and all check-nodes to all can adopt the mode of parallel synchronous that its edge messages is upgraded.In following various enforcements, the edge messages of node on the throne more new processor is called an engine processor, the edge messages of check-node more new processor be called the verification engine processor.If a ldpc coded signal has N position node and R check-node, N position engine processor parallel running can be arranged, same, R also parallel running of verification engine processor.Yet when N was very big, with current technology, such mode cost was too high, to such an extent as to so big parallel processing can't realize.

The method of a kind of reduction processing requirements (thereby higher relatively executory cost) is to adopt the parallel block ldpc coded signal.The characterizing definition of this ldpc coded signal is as follows:

If p is a positive integer, establish N=pn and R=pr.

With N the position node 0 ..., ph-1 divides into n sub-piece, so that each piece has p element.By B _iIndicate i piece, comprise a node b in this piece _{I, 0}..., b _{I, p-1}, wherein, i=0 ..., n-1.We claim B _iBe position piece node.

2. with R check-node 0 ..., pr-1 divides into k sub-piece, so that each piece has p element.By C _iIndicate i piece, comprise check-node c in this piece _{I, 0}..., c _{I, p-1}, wherein, i=0 ..., r-1.We claim C _iBe the check block node.

3. the construction of piece bipartite graph has between with following characteristic n position piece node and r the check block node.If B _iAnd C _jBe connected among the figure, have so one 0,1 ..., the arrangement π of p-1} _{I, j}, make

K=0 ₁..., p-1 is the edge in the position bipartite graph of this LDPC coding.Herein, some edges to verification in piece may be non-existent in the bipartite graph in fact on the throne.Therefore, if this situation has taken place, those edges are false so.And the parallel edge in the piece bipartite graph is allowed to.Yet because should parallel edge, corresponding arrangement must be different to allow this situation.For these features are described, provide a special example (with reference to Figure 33) below to illustrate the feature of parallel block ldpc coded signal.Yet, before this, for carrying out the LDPC method that the position-the verification parallel decoding is set up, and the generality embodiment of the feature of some LDPC positions-verification parallel decoding function at first in following being described (as, referring to Figure 29, Figure 30, Figure 31 A, Figure 31 B and Figure 32).

Figure 29 is the legend of a kind of embodiment that sets up LDPC position-verification parallel decoding that carries out according to the present invention.For carrying out LDPC position-verification parallel decoding, original bipartite graph is divided into piece bipartite graph.This raw bits node b _i(or variable node, v _i) be divided carry piece Node B _iSimilarly, original checksums node c also _iBe divided into check block node C _iUse and arrange π _{I, j}, the method that original LDPC bipartite graph meta node (or variable node) is connected with check-node converts the method that the LDPC piece bipartite graph meta piece node of generation is connected with the check block node to.This arranges π _{I, j}Use, guaranteed the continuity at any non-existent parallel edge in the bipartite graph of original LDPC position.That is to say,, arrange π when being converted to " LDPC piece bipartite graph " territory when carrying out LDPC position-verification parallel decoding _{I, j}Use can guarantee that this non-parallel edge is present in the original LDPC bipartite graph.This situation may occur, that is: in fact LDPC piece bipartite graph has some parallel edges, but arranges π _{I, j}Use guaranteed in the LDPC bipartite graph, not exist any parallel edge.Generally speaking, arrange π _{I, j}The use of various values guaranteed management method, in this method, when carrying out iterative decoding and handle, edge messages is updated.

Arrange π by using _{I, j}Various values, therefore LDPC position-verification parallel decoding function that disclose in this place can adapt to the original LDPC coding of various extensive change types.That is to say that the LDPC bipartite graph of any extensive change type can be linked to the LDPC piece bipartite graph of extensive change type, can expand the type scope of the LDPC coding that each feature according to the present invention handles thus.This arranges π _{I, j}Allow the transformation between original LDPC bipartite graph and the LDPC piece bipartite graph, to adapt to various types of LDPC codings.Notice this arrangement π _{I, j}Can design by diverse ways.π is arranged in a kind of generation _{I, j}Method be to adopt loop shifting, between the LDPC of raw bits LDPC bipartite graph and generation piece bipartite graph, change.Again, this arranges π _{I, j}Use allow various types of LDPC coding selection to have the broad degree of freedom.In brief, arrange π _{I, j}Use allow the user use a more changeableization type the LDPC coding (as, when execute bit-verification parallel decoding not fixedly the time, can select to adopt which kind of LDPC coding).Significantly, when between the LDPC piece bipartite graph of different original LDPC bipartite graphs and various generations, changing, can use different arrangements.

Therefore, produce execution sequence.The generation of this execution sequence is included in all check block nodes in the LDPC piece bipartite graph of new generation to the mapping of the connection between all piece nodes.In addition, the generation of execution sequence is included in the mapping of all piece nodes to the internodal connection of all check blocks.These forms of dividing other mapping to tabulate are classified, as shown in some following various optional embodiments.Utilize these various all piece nodes to the internodal connection of all check blocks, and all check block nodes to the mapping of the internodal connection of all pieces, can produce actual execution sequence.According to LDPC position-verification parallel decoding, these execution sequences allow parallel processing and updating edge (LDPC piece bipartite graph).

Notice that the selection of these execution sequences can carry out by the designer of LDPC position-verification parallel decoding function.That is to say that the designer need select special execution sequence to handle to finish LDPC position-verification parallel decoding.Task the most difficult in LDPC position-verification parallel decoding function design, that require great effort most that the selection of this execution sequence can be counted as.When producing these execution sequences, this function also comprises the minimal set of determining the position-check-node that will be initialised, to help the parallel decoding processing of finishing corresponding to the Synchronous Processing at the edge of at least one piece node and at least one check block node.

Figure 30 is the legend of operating a kind of embodiment of LDPC position-verification parallel decoding function according to the present invention.The diagram of LDPC position-verification parallel decoding function at first shows continue to be carried out before parallel decoding handles, and how to be initialised corresponding to the edge messages of the minimal set of position piece node; It was performed during the time period 0.

In the time period 0, in case corresponding to the edge initialization of the minimal set of this piece node, this parallel decoding is handled in time period 1 beginning.Use the arrangement π that present embodiment adopted _{I, j}Various values, the method for the edge being handled according to this parallel decoding processing mode with management.

Carry out the processing of running simultaneously of first at least one check block node, and the processing of running simultaneously of first at least one piece node.Notice in this time period 1, corresponding to the edge of at least 1 check block node and processed corresponding to the edge of at least 1 position piece node.In case processed the finishing of particular edge that these are relevant with position piece node and relevant with the check block node can be applied in the time period subsequently in another function corresponding piece.

For example, in case the edge corresponding to a specific position piece node is updated in the time period 1, in the later time section (as the time period 2 and after), in the processing relevant with the check block node of any kind, these edges are available.Opposite also is correct; In case the edge corresponding to a particular verified piece node during the time period 1 is updated, in the later time section (as time period 2 and after), in the processing relevant with the position piece node of any kind, these edges are available.To the wisdom of execution sequence and suitable design can guarantee that in decoding iteration subsequently suitable edge relevant with position piece node and the suitable edge of being correlated with the check block node are available.This parallel processing (renewal is relevant to the edge that an edge of piece node and renewal are relevant to the check block node) be performed repeatedly (as, from the time period 1 to the time period 2 ... to time period n).

After parallel decoding iteration repeatedly, based on the execution sequence that once was used to support that above-mentioned parallel decoding is handled, a rearrangement position piece node (as, the position).That is to say, arrange π _{I, j}The use of various values, be applied to managing edge treated (as, visit according to execution sequence, reorder and handle/upgrade), more particularly, during parallel processing, according to the use of the execution sequence of LDPC piece bipartite graph, some of execute bit piece node reorder inherently.Reordering of the functional block execute bit piece node that this is last, make a piece node be in the suitable order form, so that the information bit to the code word extracted from received signal is made best estimate, this received signal is just at decoded signal according to respective rule of the present invention.

For example, this reorders and can be counted as making the position to get back to a suitable order, so that they are being exactly to handle according to this suitable order in decoded data (initially being encoded into the LDPC signal) just with the edge messages update functions piece output of this suitable order from being controlled by execution sequence.For example, before extracting the soft information in position, and before the soft estimation of the code element position of the centrifugal pump modulated symbol sequence that produces from the ldpc coded signal that receives of output, contraposition is reordered.Thereafter, from suitably extracting the soft information in position the position of ordering, with of the ordering influence of cancellation execution sequence to it.According to this soft information, make the just best estimate of the one or more information bit in decoded original LDPC signal.

Ensuing two figure illustrate in greater detail some possible embodiment, in this embodiment, form each check-node of check block node j and form the connection that forms reality between each node of piece node i.Notice that these embodiment only are the simple case of certain methods, wherein, each piece node in each check-node in the check block node and the position piece node can be according to arranging π _{I, j}Connected by communication ground.Significantly, but the embodiment that the ground of other communication in the distinct methods connects falls into scope of the present invention too.

Each check-node in the check block node and position piece node are (as by various arrangement value π _{I, i} ¹And π _{I, j} ²And mark) in each internodal these various links shown connection between LDPC piece bipartite graph and LDPC bipartite graph (its parallel edge).In these examples each is one { 0,1,2 ..., the arrangement π of n} is { 0,1,2 ..., the mapping one to one on the n}.

Figure 31 A is a kind of exemplary arrangement π that link is provided between LDPC piece bipartite graph and LDPC bipartite graph according to the present invention _{I, j} ¹The legend of embodiment.In this example, arrangement is defined as a mapping, { 0,1,2 ..., the x of n} ₁Be defined as follows:

π ₁(0)＝1，π ₁(1)＝3，π ₁(2)＝0，π ₁(3)＝4，andπ ₁(4)＝2。

This arrangement can be marked as (01342).

Arrange according to this, being connected of each node in each check-node among the check block node j and the piece node i is as follows:

1. check-node j ₀Be connected to a node i ₂

2. check-node j ₁Be connected to a node i ₀

3. check-node j ₂Be connected to a node i ₄

4. check-node j ₃Be connected to a node i ₁

5. check-node j ₄Be connected to a node i ₃

Figure 31 B is a kind of exemplary arrangement π that link is provided between LDPC piece bipartite graph and LDPC bipartite graph according to the present invention _{I, j} ²The legend of another embodiment.In this example, arrangement is defined as a mapping, { 0,1,2 ..., the π of n} ₂Be defined as follows:

π ₂(0)＝4，π ₂(1)＝0，π ₂(2)＝1，π ₂(3)＝2，andπ ₂(4)＝3.

This arrangement can be marked as (04321).This arranges π _{I, j} ²Also be that a cyclic shift is arranged.

1. check-node j ₀Be connected to a node i ₁

2. check-node j ₁Be connected to a node i ₂

3. check-node j ₂Be connected to a node i ₃

4. check-node j ₃Be connected to a node i ₄

5. check-node j ₄Be connected to a node i ₀

Even supposition check block node j and a position piece node i have two parallel edges (as, connect from the edge of two separation of an independent check block node to an independent position piece node) incident, use two different arrangement value π _{I, j} ¹And π _{I, j} ²(derive as Figure 31 A and Figure 31 B each check-node in check block node j shown in respectively and the connection between each node in the piece node i of position) can guarantee not have respectively between check-node in check block node j and position piece node and the position node edge that walks abreast.As mentioned above, use arrangement π _{I, j}Can guarantee not have parallel edge in the LDPC position bipartite graph (as, initial LDPC bipartite graph), even in fact they may be present in the LDPC piece bipartite graph.

Figure 32 is the legend of the optional embodiment of the LDPC position-verification parallel decoding function operated according to the present invention.This decoding function is similar to the described embodiment of Figure 30 before time period n.

For example, the LDPC position shown in this figure-verification parallel decoding function equally at first shows and continue to carry out before parallel decoding handles, and how to be initialised corresponding to the edge messages of the minimal set of position piece node, and it was carried out during the time period 0.

Method among the embodiment of same and Figure 30 is similar, and in the time period 0, in case corresponding to the edge initialization of the minimal set of this piece node, this parallel decoding is handled in the time period 1 and begun.Use the arrangement π that present embodiment adopted _{I, j}Various values, the method for the edge being handled according to this parallel decoding processing mode with management.

For example, in case the edge corresponding to a specific position piece node is updated in the time period 1, in the later time section (as the time period 3 and after), in the processing relevant with the check block node of any kind, these edges are available.Opposite also is correct; In case the edge corresponding to a particular verified piece node during the time period 1 is updated, in the later time section (as time period 2 and after), in the processing relevant with the position piece node of any kind, these edges are available.To the wisdom of execution sequence and suitable design can guarantee that in decoding iteration subsequently suitable edge relevant with position piece node and the suitable edge of being correlated with the check block node are available.This parallel processing (renewal is relevant to the edge that an edge of piece node and renewal are relevant to the check block node) be performed repeatedly (as, from the time period 1 to the time period 2 ... to time period n).

Yet last functional block of this figure is different with its previous embodiment.In this embodiment, after several parallel decoding iteration are finished, carry out at least one other decoding iteration and do not need execution sequence control.Tagmeme piece node (as, position) is reset in this at least one other decoding iterative processing (inherently) naturally, and the order of this piece node may be carried out ordering according to supporting this parallel decoding to handle the execution sequence that adopt.

This last other decoding iteration can be considered to be at the LDPC decoding of carrying out under the situation of the support that does not have LDPC piece bipartite graph.That is to say, using the LDPC coding/decoding method to carry out in the decoding processing, this iteration of decoding for the last time be carry out alone (as, do not carry out LDPC position-verification parallel decoding method).In other words, handle the edge messages relevant with each check block node in the LDPC bipartite graph (as, uncorrelated with the check block node in the LDPC piece bipartite graph), then handle the edge messages relevant with each position node in the LDPC bipartite graph (as, uncorrelated with the piece node in the LDPC piece bipartite graph).

This last decoding iteration is not carried out concurrently, and this can cause the stand-by period to a certain degree in whole decoding processing.

Yet though this last decoding iteration is not to carry out concurrently, it still can reduce based on the needs that reorder of execution sequence bit block node (as, position), and this execution sequence is used to support parallel decoding to handle.This last decoding iteration is after executing under the support that need not execution sequence control, before extracting the soft information in position, and before the soft estimation of the code element position of the centrifugal pump modulated symbol sequence that produces from the ldpc coded signal that receives of output, do not need to carry out any piece node (as, the position) reorder.After this, from naturally, extract the soft information in position (because last decoding iteration does not need execution sequence control) the position of suitably reordering corresponding to the LDPC bipartite graph.According to this soft information, make the just best estimate of the one or more information bit in decoded original LDPC signal.

Figure 33 is the legend of arranging a kind of embodiment of a LDPC piece-bipartite graph according to the present invention.Can see that from this figure the position node is aligned to several piece nodes.For example, initial bit node, b ₀, b ₂..., b _n, all be arranged carry piece Node B ₁, and position node b _k, b _K+1..., b _{K+ (N-1)}, all be arranged carry piece Node B _cSimilarly, check-node is arranged into several check block nodes.For example, initial check-node, c ₀, c ₂..., c _nAll be arranged into check block node C ₁, and position node b _k, b _K+1..., b _{K+ (N-1)}All be arranged into check block node C _dThe edge transition of LDPC bipartite graph is become the method at the edge in the LDPC piece bipartite graph, can be described as arranging π _{I, j}That is to say, arrange π _{I, j}Be the relation between this method, adopt this method, the edge is connected between position node and the check-node in the LDPC bipartite graph, and the edge be connected between the position piece node and check block node in the LDPC piece bipartite graph.

Notice have several different methods the initial bit node division can be become position piece node, and also have several different methods initial check-node can be divided into the check block node equally.These can be realized by suitable method, adopt the designer of the system and method for various features of the present invention to determine this method.And the arrangement π of which kind of type is adopted in selection _{I, j}This problem also should be judged decision by the designer of this system or method.In a word, when selecting to arrange π _{I, j}The time, this designer must attempt to guarantee not parallel edge in the piece bipartite graph.

As preceding mentioning, illustrate the feature of parallel block ldpc coded signal below with reference to Figure 34.

Figure 34 is the legend according to a kind of embodiment of the LDPC piece-bipartite graph of one of the present invention parallel block LDPC coding with 1/2 rate that piece is of a size of 1248 positions and 624 verification equatioies.In the figure, black surround is represented parallel edge.This figure discussion has the example that bit length is the 1/2 rate LDPC coding of 1248 and 624 verification equatioies.If P=52 has 24 position piece (as directed B so ₀, B ₁, B ₂..., B ₂₃) and 12 check block (as directed C ₀, C ₁, C ₂..., C ₁₁).First 12 pieces are B _i=52i, 52i+1 ..., 52 (i+1) i-1}, i=0 ..., 11.Next 12 position pieces are expressed as B _j=52j, and 52j+12,52j+24 ..., 52j+51 * 12}, j=0 ..., 11.Figure 34 has provided the diagram for example of this specific piece bipartite graph.

In this drawing, black surround is represented parallel edge.The arrangement π at each edge _{I, j}Be cyclic shift, it is listed in the table of Figure 35.

Figure 35 is the permutation table according to all edges of LDPC piece-bipartite graph of Figure 34 of the present invention.Again, the arrangement π at each edge _{I, j}Be cyclic shift, shown in the table 1 of this figure.In the table 1 as shown in the drawing, if do not have numeral in a unit, show those specific nodes (as, do not connect between on the throne node and check block node) between do not connect, otherwise, the degree of depth of this digitized representation cyclic shift.Two numerals two cyclic shifts at parallel edge.

Some embodiment of parallel block LDPC coding disclose in the front and (comprise regular LDPC coding, wherein, each independent position node is looked at as a position piece node and each check-node is looked at as a check block node---and for example, each piece only has an element).In addition, employed LDPC encodes and represented the embodiment of another parallel block LDPC coding of making a profit from various feature of the present invention in the European standard of DVB-2.The description of this this LDPC coding is with reference to as follows:

The ETSI EN 302 307 that " is used for broadcasting, iteration service; digital video broadcasting (DVB) second generation frame structure, chnnel coding and modulating system (Digital video broadcasting (DVB) second generation framing structure; channel coding and modulation system forbroadcasting; iterative services; news gathering and other broadband satelliteapplications) that massage set and other broadband satellite are used ", V1.1.1,2004-01.

More many cases of parallel block LDPC coding can find in 3 following references:

1.H.Zhong reach T.Zhang, " the directed LDPC coding (Design of VLSIimplementation-oriented LDPC codes) of carrying out of VLSI ", IEEE media technology half a year association (VTC), in October, 2003.

2.S.J.Johnson reach S.R.Weller, " the class circulation LDPC coding (Quasi-cyclicLDPC codes from difference families) of different series ", 3 ^RdAusCTW, Canberra, Australia, 4-5 day in February, 2002.

3.F.Verdier and D.Declercq, " the LDPC parity matrix structure (ALDPC parity check matrix construction for parallel hardware decoding) of parallel hardware decoding ", Third International's discussion of Turbo coding and relevant proposition, Brest, France, in September, 2003.

And, briefly mention as the front, notice that a traditional position LDPC coding itself can be considered to the parallel LDPC coding of piece that each piece only has an element.Therefore, at the remainder of this description, term---parallel block ldpc coded signal can be counted as representing position LDPC coding and parallel block LDPC encode both (wherein DPC coding just a type of parallel block LDPC coding).

Equally, above various communication systems and the apparatus embodiments introduced, the general signal encoding of carrying out according to the LDPC coded system has been described.These comprise the various embodiment that carry out the LDPC coding any one also all can be counted as and produce the parallel block ldpc coded signal.Therefore, for any one the be counted as contraposition ldpc coded signal and the parallel block ldpc coded signal of various embodiment of LDPC position-verification parallel decoding decode.Again, general ldpc coded signal can be looked at as the parallel block ldpc coded signal a special type (as, wherein each piece includes only an element).

At first introduce the operation of the non-position-verification parallel mode that ldpc coded signal is decoded, to compare with position-verification parallel decoding method effectively, this method will be described in more detail in the back.

1. for i=0 ..., n-1 carries out p position engine concurrently, with to all positions piece Node B _iUpdating edge messages (it comprises the initialization to the edge messages with yardstick);

2. for i=0 ..., r-1 carries out p verification engine concurrently, with to all check block node Ci updating edge messages (it comprises the initialization to the edge messages with yardstick);

3. if number of iterations does not reach capacity (will carry out the total degree of decoding iteration), decode procedure is got back to step 1 so.Otherwise, make hard decision based on the soft information that is relevant to edge messages, and the best estimate of making code word is then with its output.

An optional step 3 can be carried out as follows:

Carry out hard decision to produce the code word of estimating (corresponding to a special decoding iteration), decode, so that it is carried out syndrome (syndrome) verification.If by the syndrome verification, this decode procedure is not got back to step 1 to the code word of estimating so.Otherwise the best estimate of making code word is then with its output.

In with non-position-verification parallel mode the LDPC encoded signals being decoded, engine processor on the throne obtains after all edge messages, and the verification engine processor begins to handle.Usually, edge messages is stored in the memory, as RAM (random access memory), wherein corresponding to edge (B _i, C _i) the p value of edge messages be incorporated into together.This non-position-verification parallel mode that ldpc coded signal (or parallel block ldpc coded signal) is decoded is operated like this: all edges (step 1) of front of upgrading one or more positions piece node, then, repeat these steps (step 1 of front and step 2) alternatively.Owing to do not have parallel work-flow, thereby some edges of any piece can upgrade simultaneously with the edge of any check block.Step 1 and step 2 in the non-position-verification parallel method that ldpc coded signal is decoded can not be carried out simultaneously.

That is to say that in the non-position-verification parallel mode of aforesaid ldpc coded signal decoding, verification engine processor and position engine processor are not to operate synchronously and concurrently.Aforesaid operating procedure 1 and step 2 are not to carry out synchronously and concurrently.

The coding/decoding method of a novelty that discloses by this place, in fact above-mentioned step 1 and step 2 can be reached synchronously concurrently and be carried out.Various systems and the mode of carrying out LDPC position-verification parallel decoding are disclosed in herein.

In order to be easy to statement, use with the above-mentioned example that provides in identical LDPC encode.As above introduce, this coding has 1248 positions, forms 24 position piece (as directed B ₀, B ₁, B ₂..., B ₂₃) and 12 check block (as directed C ₀, C ₁, C ₂..., C ₁₁).Except first check-node, each check-node has a degree 7.Therefore, shown in the table 2 among Figure 35 (the piece bipartite graph of 1/2 rate parallel block LDPC coding), each check block node has connected 7 position piece nodes.

Following table 2 (as shown in figure 35) has provided this connection.

Figure 36 be according to LDPC piece-bipartite graph of Figure 33 of the present invention by put in place the mapping table of piece node edge of check block node.This table 2 is according to the special initial LDPC coding that is adopted and arrange π _{I, j}, between check block node and position piece node, provide this special connection, wherein, arrange π _{I, j}Initial bit LDPC bipartite graph is converted to LDPC piece bipartite graph.Shown in first example, this check block node C ₀Be connected to each piece Node B ₀, B ₁, B ₄, B ₇, B ₉, B ₁₂, B ₂₃Between other check block node and the position piece node other is connected and can similarly finds in this table 2.

The position piece of above-mentioned table 2 to the corresponding relation of check block can exchange, to produce table 3 (as shown in Figure 37).

Figure 37 be according to LDPC piece-bipartite graph of Figure 34 of the present invention by the mapping table of position piece node to the check block node edge.This table 3 is according to the special initial LDPC coding that is adopted and arrange π _{I, j}, provide this special connection between on the throne node and the check block node, wherein, arrange π _{I, j}Initial position LDPC bipartite graph is converted to LDPC piece bipartite graph.As first example, position piece Node B ₀Be connected to each check block node C ₀, C ₁, C ₃, C ₅, C ₈, C ₉, C ₁₀Between other piece node and the check block node other is connected and can similarly finds in table 3.

Based on above-mentioned two tables (table 2 and table 3 shown in Figure 36 and Figure 37 difference), and suppose that position engine processor and verification engine processor use identical time updating edge messages basically, can produce execution sequence table (table 4 as shown below (Figure 38)).In this table 4, in delegation, corresponding to the position engine processor and both operations of verification engine processor of position piece node and check block node, the ground updating edge messages of can running simultaneously mutually.

Figure 38 is the execution sequence table corresponding to LDPC piece-bipartite graph according to Figure 34 of the present invention.This table 7 has comprised the minimum edge collection about position piece node, and wherein, position piece node is initialised to support the position-verification parallel decoding processing in the decoding iteration of carrying out according to this group fill order subsequently.Afterwards, the edge that is relevant to an edge of piece node and is relevant to the check block node can upgrade with running simultaneously.

When execution sequence is selected, can use various standards, wherein, execution sequence can be used to carry out iterative decoding to be handled, can be by the while parallel processing so that be relevant to some piece nodes and be relevant to the edge of some check block nodes.A simple and clear method that can produce this execution sequence provides as follows:

Be used to produce the standard of execution sequence:

During iteration i, on the check block node, if a check block node c is in k is capable, so all position piece nodes that is connected to this check block node c (as, b ₀..., b _m) should look like this:

1. this row is respectively with k-I ₀..., k-I _mExpression, I _i＞0.And those row of position piece node should also have identical position piece node iteration, i;

2. do not have the row of the k of piece node iterations i before capable.

For example, the decision that this makes standard is used to design execution sequence, and it can be better understood by an example.The check block node 10 of consideration in iteration 1.It is positioned at the 14th row.The position piece node that is connected to the check block node is expressed as follows:

0,2,10,11,21,22 wherein 0 be arranged in a block iteration 1 the 2nd the row

2 are arranged in the 5th row of a block iteration 1

10 are arranged in the 4th row of a block iteration 1

11 are arranged in the eighth row of a block iteration 1

21 are arranged in the 7th row of a block iteration 1

22 are arranged in the eighth row of a block iteration 1

And neither one is arranged in the row before the 14th row with piece node iteration 2 in 0,2,10,11,21,22.

Utilize these execution sequences of suitably setting up, use the position yardstick LDPC position-verification parallel decoding function (as, among the embodiment shown in Figure 47) operation can followingly constitute:

1. for a given number of iterations 1, this decoder can upgrade corresponding to position piece node and both edge messages of check block node according to this execution sequence table with running simultaneously;

Based on this edge messages make hard decision, produce the best estimate of code word, then with its output.Alternatively, after all positions engine processor is finished a decoding iteration, can make hard decision, and should determine firmly to be used for syndrome (syndrome) verification (as, by the syndrome calculator).If the code word that should estimate is not by the syndrome verification, this decoding processing is returned step 1.Otherwise, produce the best estimate of code word, then with its output.

Notice that equally not finishing of each iteration and verification iteration can side by side be finished.For example, in the execution sequence of this certain embodiments, shown position iteration 1 shown in be done before 6 time quantums of verification iteration 1 before being done.Finishing of each iteration and verification iteration can and be finished continuously by (alternatively) alternatively, shown in this special embodiment.This with technical method formerly in pairs than, formerly in the technology, finishing of iteration of position is just completed before the verification iteration begins, and finishing of verification iteration is just completed before iteration on the throne begins.

Though, for two addresses of same time (as, in the binary channels memory devices), can from memory, read and write memory; But, also can adopt the memory that a kind of complexity is low and cost is also low (as, single channel memory devices only).In any given time, if memory has only an address accessed (deposit in or export), it can save hardware, like this, can adopt cheap single channel memory devices.Use the processing method of running simultaneously mentioned herein that parallel block ldpc coded signal (comprising a ldpc coded signal) is decoded, only need two memories, be called left memory and right memory (or being called first memory and second memory alternatively).Certainly, alternatively, can adopt an independent memory (as, binary channels memory), it logically is divided into left half and right half.

Use this two memories, be explained in more detail in conjunction with the step 1 of the table 5 that is used for previous defined same 1/2LDPC coding (Figure 39,, the 4th part shown in Figure 40, Figure 41 and Figure 42) to above-mentioned coding/decoding method.

Figure 39, Figure 40, Figure 41 and Figure 42 are the various pieces according to the operation table that shows memory access corresponding to Figure 34 LDPC piece-bipartite graph of the present invention.In these 4 exemplary graphs of table 5, " L " refers to that left memory (as, first memory) and " R " refer to right memory (as, second memory).Again, left memory (as, first memory) and right memory (as, second memory) can be the independent memory devices logical partitioning part simply of (as, binary channels memory devices).

For the various types of decoders that disclosed, some support the possible memory of the treatment step of this table 5 to arrange also has more detailed description in Figure 53 A and Figure 53 B.

Carried out the iterative decoding iteration I time if table 5 shows, this position-verification code parallel decoder needs

Individual time quantum.Because the piece bipartite graph of this coding has 84 edges, traditional decoder needs 2 * 84I=168I time quantum.

Like this, LDPC position-verification code parallel decoder has been saved (50-(50/I)) the % stand-by period.When number of iterations has surpassed 49, new decoder has saved about 49%.Work as I=50, so 42+84I=4242 and 168I=8420.

Therefore, only move in the time of 26 iteration at the LDPC of traditional type decoder, the LDPC position-verification code parallel decoder of institute's construction can be finished 50 times all LDPC positions-verification decoding iteration according to the present invention.The service speed that this means such LDPC position-verification code parallel decoder is the twice of the LDPC decoder of traditional type.

In a word, for decoding parallel block ldpc coded signal (and decoded bit ldpc coded signal), can at first produce the table that mapping connects (as, the Figure 36 that provides above and table 2 and the table 3 of Figure 37 are provided, for a special example), wherein, connection from position piece node to the check block node, and from the check block node to a position piece node.So, number of times characteristic (degree property) according to the table of these two suitable construction and parallel block LDPC coding, can produce the table that another one comprises suitable execution sequence, so that about various nodes (as, the position piece node in the above-mentioned example) and about the edge messages of check block node can and renewal with running simultaneously.

Use can produce the suitable LDPC position-verification parallel decoding operation table of design, with the method for control and treatment edge and reference to storage by the execution sequence control operation that this table provided.So, position-verification code parallel decoder can be decoded to ldpc coded signal according to this operation table.

As an example, when considering the parallel LDPC coding of a piece, have when encoding E required edge and I iteration, so, this LDPC position-verification code parallel decoder needs the individual time quantum of maximum E (I+1), and a traditional decoder needs 2 * E * I time quantum.Therefore, this new LDPC parallel-by-bit decoder has been saved almost the closely time of implementation of the traditional LDPC decoder of half.

Those skilled in the art is appreciated that generally an engine processor does not have verification engine processor complexity usually.Therefore, can adopt the position engine processor that doubles verification engine processor speed (2x).In this case, can produce another execution sequence table (an optional table), utilize coding that above-mentioned example is produced with decoding.

Table 4 (shown in Figure 38) is based on hypothesis verification engine processor and the position engine processor can design with substantially the same time quantum processing edge messages.Yet following table 6 (as shown in figure 43) is when using the position engine processor double verification engine processor speed, the execution sequence table that produces alternatively for the LDPC coding of above-mentioned identical 1/2 rate.That is to say, suppose that the fact is that the operation of an engine processor is faster relatively than the operation of verification engine processor, can produce more suitable special (tailored) execution sequence table.

Figure 43 is the optional execution sequence table (is selectable to Figure 38) according to the LDPC piece-bipartite graph corresponding to Figure 34 of the present invention.

According to table 6 and table 4 (respectively as Figure 43 and shown in Figure 38) and above-mentioned description, if I iteration is performed as can be seen, LDPC position-verification code parallel decoder needs 24+168I time quantum, and traditional decoder needs 84+2 * 84=252 time quantum to finish the iteration of an iterative decoding.Like this, need 252I time quantum to finish iteration I time.Like this, when the iterative decoding number of times surpassed 7, LDPC position-verification code parallel decoder had been saved and has been surpassed for 32% stand-by period.When I=50,24+168I=8424 and 252I=12600 so, position-verification code parallel decoder has saved for 33% stand-by period like this.In other words, when a traditional LDPC decoder had been carried out 34 iteration, new LDPC position-verification code parallel decoder had been finished 50 times all decoding iteration.Alternatively, can be by this true description, in the identical time period, LDPC position-verification code parallel decoder can be carried out 20 times iteration more than conventional decoder.

In order to export orderly data, can wish position-verification code parallel decoder is combined with traditional decoder, as described below:

1. if a given iterations is I, according to execution list with updating edge messages;

2. carry out iteration the I+1 time by conventional decoder, that is, carry out the edge messages of an engine processor earlier and upgrade, then carry out the edge messages of verification engine processor and upgrade.

3. make hard decision based on edge messages, and the code word of estimating be output and.(or after all positions engine processor has been finished iteration, make hard decision and use it for the syndrome checking treatment (as, by a syndrome calculator)).If by the syndrome verification, this decoding processing is not returned step 1 to code word so.Otherwise, make the best estimate of code word, then with the code word output of estimating.

Figure 44 is the legend according to a kind of embodiment of the LDPC piece-bipartite graph of one of the present invention parallel block LDPC coding with 2/3 rate that piece is of a size of 1200 positions and 400 verification equatioies.This example considers that having bit length is that the encoding rate of 1200 and 400 verification equatioies is 2/3 LDPC coding.This encoding rate is that 2/3 LDPC coded representation is as follows:

If p=40.30 position piece nodes and 10 check block nodes are arranged so.The one 20 position piece is B _i=(40i, 40i+1 ..., 40 (i+1) i-1), i=0 ..., 20.Following 10 position piece nodes are B _j=(40j, 40j+10,40j+20 ..., 40j+39 * 10), j=0 ..., 9.This LDPC piece bipartite graph is drawn in Figure 44.In LDPC piece bipartite graph, black surround is represented parallel edge.(i, permutation table j) is shown π at the edge _{I, j}Between on the throne node 0 and the check block node 0 two edges are arranged.Three different arrangements are arranged, be called π _0,0 ¹And π _0,0 ²And.Similarly, different arrangements is arranged:

π _0,5 ¹, π _0,5 ², π _0,6 ¹, π _0,6 ², π _0,8 ¹,, π _0,8 ², π _0,9 ¹, π _0,9 ²π _1,1 ¹, π _1,1 ², π _1,1 ³, π _1,2 ¹, π _1,2 ², π _1,3 ¹, π _1,3 ², π _1,4 ¹, π _1,4 ², π _2,6 ², π _5,5 ¹, π _5,5 ²And π _17,7 ¹, π _17,7 ², π _17,7 ³

As previously mentioned, this special LDPC coding has 1200 positions, is formed 30 position piece nodes and 10 check block nodes.The number of degrees that each each check-node except first check-node has are 10.Therefore, disclose as corresponding LDPC piece bipartite graph, each check block node is connected on 10 position piece nodes.Table 7 (as shown in figure 45) provides this connection.

Figure 45 be according to LDPC piece-bipartite graph of Figure 44 by put in place the mapping table of piece node edge of check block node.Similar in appearance to the table 2 (the another one example among Figure 36) that the front provided, table 7 provides according to employed this specific initial LDPC coding and has arranged π _{I, j}, the special connection between check block node and position piece node, it converts initial bit LDPC bipartite graph to LDPC piece bipartite graph.

Figure 46 is the execution sequence table corresponding to LDPC piece-bipartite graph according to Figure 44 of the present invention.Similar in appearance to other embodiment described below, the generation of this table 8 comprises execution sequence equally, and this execution sequence is used to control corresponding to the edge of position piece node and corresponding to the renewal of running simultaneously at the edge of check block node.Equally also with reference to the above embodiments, this table 8 also comprises a minimum edge collection that is relevant to a piece node, and this minimum edge collection is initialised, so that according to this execution sequence group, supports position-verification parallel decoding to handle in decoding iteration subsequently.After this initialization that is relevant to the minimum edge collection of a piece node was finished, the edge that is relevant to an edge of piece node and is relevant to the check block node can be reached concurrently synchronously to be upgraded.

Figure 47 is the legend according to a kind of embodiment of the LDPC position-verification parallel decoding function of use of the present invention position yardstick.At first, the iterative decoding that comprises the edge parallel processing that is relevant to a piece node and be relevant to the edge treated of check block node in execution is handled (using at least one engine processor and at least one verification engine processor), and before, this embodiment is similar in appearance to the described embodiment of Figure 20.

For example, as the I that receives the signal on symbol node, after the Q value, m bit symbols yardstick calculator function piece calculates corresponding code element yardstick.On this symbol node, these code element yardsticks then are transferred into a symbol node calculator function piece, and it uses the position yardstick of the code element yardstick calculating of these receptions corresponding to these code elements.These yardsticks then are transferred into the position node that is connected in this symbol node.

The iterative decoding of this embodiment is handled different with the embodiment of Figure 20, because the renewal that is relevant to a renewal of the edge messages of piece node and is relevant to the edge messages of check block node is all reached concurrently synchronously to be carried out.At least one engine processor and at least one verification engine processor cooperation executable operations, upgrading respectively to the edge messages that is relevant to a piece node and check block node.These at least one engine processors and at least one verification engine processor also all use the first memory of edge messages and the second memory of edge messages.Again, described in other embodiment, this first memory and this second memory can be single access memory equipment.Alternatively, this first memory and this second memory can be realized by the logical gate in the binary channels memory devices.When the position engine processor is visited the first memory of this edge messages, the second memory of verification engine processor visit edge messages.For example, when engine processor renewal in position is relevant to first group of edge messages of at least one piece node, the first memory of position engine processor visit edge messages, and when the renewal of verification engine processor is relevant to first group of edge messages of at least one check digit piece node, the second memory of verification engine processor visit edge messages.Then, exchange this renewal and handle: when the position engine processor then upgrades when being relevant to second group of edge messages of at least one piece node the second memory of position engine processor visit edge messages.When the renewal of verification engine processor is relevant to second group of edge messages of at least one check block node, the first memory of verification engine processor visit edge messages.

This iterative decoding handle and can repeat by predefined iterations (as, repeat n time, wherein n is optional).Alternatively, repeat these iterative decoding treatment steps, the syndrome of encoding up to LDPC is equal to 0 (in a certain accuracy).

During each decoding iteration, in the engine processor of position, produce soft output information.In this embodiment, this soft output can be offered a hard limiter, it can make hard decision, and this hard information can be provided to a syndrome calculator, is equal to 0 (in a certain accuracy) with the syndrome that determines whether the LDPC coding.That is to say the syndrome calculator determines whether each syndrome that is relevant to the LDPC coding equals 0 in fact in predetermined a certain accuracy rating.For example, when a syndrome has mathematical non-0 value, it is less than defined certain threshold value of predefined a certain accuracy for a short time, and this syndrome can be considered to equal 0 in fact so.When a syndrome has mathematical non-0 value, it is less than defined certain threshold value of predefined a certain accuracy greatly, and this syndrome can be considered to be not equal to 0 in fact so.

When syndrome was not equal to 0 in fact, this iterative decoding was handled and is continued suitably to upgrade between at least one engine processor and this at least one verification engine processor in this again and transmit edge messages.After all these iterative decoding treatment steps were finished, so based on this soft information, the best estimate of position (forming a code word) was output.In the method for this embodiment, the position scale-value of calculating by symbol node calculator function piece is a fixed value, reuses this value when carrying out node updates.

Figure 48 is the flow chart according to a kind of embodiment of the method for execution LDPC of the present invention position-verification parallel decoding.This method comprises continuous time signal of reception.Be coded in the information bit in this continuous time signal, utilized the LDPC coded system to encode.This LDPC coding can be counted as parallel block LDPC coding.On the continuous time signal of this reception, can notice that this method comprises first continuous time signal of the carrying out any necessity down converted of (as, the continuous time signal of primary reception), produces one second continuous time signal therefrom.Down converted can be from the carrier frequency to the base band direct conversion, or change by an IF (intermediate frequency) alternatively and without departing from the spirit or scope of the invention.

This method also comprise sampling first (or second) connect hours signal (as, use ADC) produce a discrete-time signal therefrom and therefrom extract I, Q (homophase, quadrature) component.Then, this method also comprises demodulation I, Q component and execution I, and the symbol mapped of Q component produces a centrifugal pump modulated symbol sequence therefrom.Afterwards, this method also comprises the renewal of carrying out edge messages according to predefined execution sequence.The renewal that this edge messages relevant with the check block node reaches the edge messages relevant with position piece node is to reach concurrently synchronously to carry out.For example, this method is included as the position engine of all position piece node updates edge messages and handles, and this method is included as the verification engine processing of all check block node updates edge messages.

In this special embodiment, this method comprises based on described and is used to manage the execution sequence that parallel decoding is handled, to piece node (as, position) rearrangement.Reordering of this bit block node (as, position) is after last decoding iteration is finished and carry out.This method also comprises based on corresponding to the soft information of the edge messages of final updating and make hard decision.By using these hard decisions, this method also comprises the best estimate of the relevant code word that transmits of output (having at least one information bit to be included in it), and wherein, this code word is to extract from the continuous time signal that receives.

Figure 49 is the flow chart according to a kind of optional embodiment of the method for execution LDPC of the present invention position-verification parallel decoding.At first, the operation of this special method is very similar to the described embodiment of Figure 48.This method comprises continuous time signal of reception.Be coded in the information bit in this continuous time signal, utilized the LDPC coded system to encode.This LDPC coding can be counted as parallel block LDPC coding.On the continuous time signal of this reception, can notice that this method comprises first continuous time signal of the carrying out any necessity down converted of (as, the continuous time signal of primary reception), produces one second continuous time signal therefrom.Down converted can be from the carrier frequency to the base band direct conversion, or change by an IF (intermediate frequency) alternatively and without departing from the spirit or scope of the invention.

Yet from now on, this method will break away from the operation of method shown in Figure 48.In this special embodiment, this method comprises based on the soft information of respective edges message makes hard decision, estimates to produce current code word.This estimation comprises that equally the current state bit block node based on execution sequence reorders, to make the effective current estimation of code word.That is to say, consider the current state of execution sequence, so that arrange a position piece node (as, position) with suitable order, thereby the effective current estimation that makes code word is in correct position order.The current state of execution sequence can be counted as the execution sequence that has been employed before at this point (step).Equally, notice the execution of making hard decision be engine on the throne finish dealing with at least one the decoding iteration after and carry out.

After the current estimation of making this code word, this method comprises the syndrome verification of the current estimation of run time version word.Passed through the syndrome verification with the current estimation that determines whether this code word.If the syndrome verification is not passed through, this method comprises that (synchronous and execution concurrently) turns back to the edge messages step of updating according to predefined execution sequence so.Yet, in fact passed through if find the syndrome verification, this method comprises the execution sequence of managing the parallel decoding processing before this step based on above-mentioned being applied to so, the bit block node (as, the position) resequence.By the control of above-mentioned syndrome checking procedure, the reordering of this piece node (as, position) carried out after executing last decoding iteration.

By using these suitable position piece nodes that reorder (as, position), this method also comprises the best estimate (having at least one information bit to be included in it) of the transmission code word that output is extracted from the continuous time signal that receives.The best estimate of this transmission code word produces according to hard decision, and wherein, hard decision is based on corresponding to the soft information of the edge messages of final updating and makes.

The principle that the utilization position yardstick that disclose the front is carried out LDPC position-verification parallel decoding function and method also can extend to other various embodiment that are applied to adapted for decoding LDPC code signal.For example, these reach the principle of parallel updating edge messages synchronously, applicable to utilizing a position yardstick (having a yardstick upgrades) according to the decoding that the LDPC piece-verification parallel decoding function is carried out, and the decoding that utilizes code element yardstick and position yardstick to carry out according to LDPC mixing-verification parallel decoding function.Some about the edge messages of how to carry out various variable nodes and check block node synchronously and parallel method for updating, in these special coding/decoding methods each, all be disclosed among the following figure.

Figure 50 is the legend according to a kind of embodiment of the LDPC position-verification parallel decoding function of a use of the present invention position yardstick (having a yardstick upgrades).At first, before execution is relevant to the edge parallel processing of a piece node and handles about the iterative decoding of the edge treated of check block node (using at least one engine processor and at least one verification engine processor), the operation of this embodiment is similar to the described embodiment of above-mentioned Figure 22.

Decode for ldpc coded modulation signal, can adopt the function among this figure burst with m position.The place receives I in symbol node, and after Q (homophase, the quadrature) value, m bit symbols yardstick calculator function piece calculates corresponding code element yardstick.At the symbol node place, these code element yardsticks then are transferred into symbol node calculator function piece, and it uses the position yardstick of these code element yardsticks that receive calculating corresponding to these code elements.But symbol node calculator function piece is also execute bit yardstick renewal during decoding iteration subsequently.

The iterative decoding of present embodiment is handled different with the embodiment of Figure 22 because, be relevant to a renewal of the edge messages of piece node and be relevant to the check block node edge messages renewal both be synchronously and execution concurrently.At least one engine processor and at least one verification engine processor cooperation are respectively carried out the renewal of the edge messages be relevant to a piece node and check block node.These at least one engine processors and at least one verification engine processor also all use the first memory of edge messages and the second memory of edge messages.Again, as mentioning among other embodiment, first memory and second memory can be independent access memory equipment.Alternatively, first memory and this second memory can be realized by the logical gate in the binary channels memory devices.When the position engine processor is visited the first memory of this edge messages, the second memory of verification engine processor visit edge messages.For example, when engine processor renewal in position is relevant to first group of edge messages of at least one piece node, the first memory of position engine processor visit edge messages; When the renewal of verification engine processor is relevant to first group of edge messages of at least one check block node, the second memory of verification engine processor visit edge messages.Then, exchange this renewal and handle: when the position engine processor then upgrades when being relevant to second group of edge messages of at least one piece node the second memory of position engine processor visit edge messages.When the renewal of verification engine processor is relevant to second group of edge messages of at least one check digit piece node, the first memory of verification engine processor visit edge messages.

Figure 51 is the legend according to a kind of embodiment of the LDPC code element verification parallel decoding function of use code element yardstick of the present invention.At first, comprise in execution and to handle (using at least one sequence of symhols and symbol node more new processor and at least one verification engine processor) by the iterative decoding of edge parallel processing that is relevant to the block of symbols node and the edge treated that is relevant to the check block node before, this embodiment is similar in appearance to the described embodiment of Figure 26 B.The initial decoding process of this embodiment is similar in appearance to Figure 26 B.。

Yet the iterative decoding of this embodiment is handled the embodiment that is different from Figure 26 B because, be relevant to the block of symbols node edge messages renewal and be relevant to the check block node edge messages renewal both carry out synchronously and concurrently.At least one sequence of symhols and symbol node more new processor and at least one verification engine processor respectively cooperation carry out the renewal that is relevant to the edge messages of block of symbols node and is relevant to the edge messages of check block node.These at least one sequence of symhols and symbol node more new processor and at least one verification engine processor are also all used the first memory of edge messages and the second memory of edge messages.Again, as mentioning among other embodiment, first memory and second memory can be realized on independent access memory equipment.Alternatively, first memory and this second memory can be realized by the logical gate in the binary channels memory devices.When a sequence of symhols and symbol node are upgraded the first memory of processor access edge messages, the second memory of verification engine processor visit edge messages.For example, when sequence of symhols and symbol node were upgraded update processor and be relevant to first group of edge messages of at least one block of symbols node, sequence of symhols and symbol node were upgraded the first memory of processor access edge messages.When the renewal of verification engine processor is relevant to first group of edge messages of at least one check block node, the second memory of verification engine processor visit edge messages.Then, exchange this renewal and handle: when sequence of symhols and symbol node more new processor then upgrade when being relevant to second group of edge messages of at least one block of symbols node, sequence of symhols and symbol node are upgraded the second memory of processor access edge messages.When the renewal of verification engine processor is relevant to second group of edge messages of at least one check block node, the first memory of verification engine processor visit edge messages.

During each decoding iteration, more produce soft output information in the new processor in sequence of symhols and symbol node.In this embodiment, this soft output can be offered a hard limiter, it can make hard decision, and this hard information can be provided to a syndrome calculator, is equal to 0 (in a certain accuracy) with the syndrome that determines whether the LDPC coding.That is to say the syndrome calculator determines whether each syndrome that is relevant to the LDPC coding equals 0 in fact in predetermined a certain accuracy rating.For example, when a syndrome has mathematical non-0 value, it is less than defined certain threshold value of predefined a certain accuracy for a short time, and this syndrome can be considered to equal 0 in fact so.When a syndrome has mathematical non-0 value, it is less than defined certain threshold value of predefined a certain accuracy greatly, and this syndrome can be considered to be not equal to 0 in fact so.

When syndrome is not equal to 0 in fact, this iterative decoding is handled and is continued to use this at least one sequence of symhols and symbol node more new processor and this at least one verification engine processor again, and edge messages that is relevant to the block of symbols node and the edge messages that is relevant to the check block node are suitably upgraded.All these iterative decoding treatment steps execute, and so based on the soft information of code element, export the best estimate of one or more code elements (cooperating and forming a code word).

Figure 52 is the legend according to a kind of embodiment of the LDPC mixing verification parallel decoding function of use code element yardstick of the present invention and position yardstick.At first, execution comprise the combination that is relevant to a piece node and block of symbols node (as, use position piece node and both mixing of block of symbols node) the edge parallel processing and be relevant to before the iterative decoding processing execution of edge treated of check block node (using at least one sequence of symhols and symbol node more new processor and at least one verification engine processor), the operation of this embodiment is similar to front Figure 27's.The initial iterative processing operation of this embodiment is similar to Figure 27.

Yet, the iterative decoding of present embodiment is handled and is different from the described embodiment of Figure 27, because, be relevant to a piece node and block of symbols node the mixing combination edge messages renewal and be relevant to the check block node edge messages renewal both carry out synchronously and concurrently.At least one sequence of symhols and symbol node more new processor and at least one verification engine processor respectively cooperation carry out the mixing combination that is relevant to a piece node and symbol node edge messages renewal and be relevant to the renewal of the edge messages of check block node.These at least one sequence of symhols and symbol node more new processor and at least one verification engine processor are also all used the first memory of edge messages and the second memory of edge messages.Again, as mentioning among other embodiment, first memory and second memory can be realized on independent access memory equipment.Alternatively, first memory and this second memory can be realized by the logical gate in the binary channels memory devices.When a sequence of symhols and symbol node are upgraded the first memory of processor access edge messages, the second memory of verification engine processor visit edge messages.For example, when sequence of symhols and symbol node were upgraded update processor and be relevant to first group of edge messages of mixing combination of at least one piece node and block of symbols node, sequence of symhols and symbol node were upgraded the first memory of processor access visit edge messages.When the renewal of verification engine processor is relevant to first group of edge messages of at least one check block node, the second memory of verification engine processor visit edge messages.Then, exchanging this renewal handles: when sequence of symhols and symbol node when more new processor then upgrades second group of edge messages of the mixing combination that is relevant at least one piece node and block of symbols node, sequence of symhols and symbol node are upgraded the second memory of processor access edge messages.When the renewal of verification engine processor is relevant to second group of edge messages of at least one check block node, the first memory of verification engine processor visit edge messages.

Similar in appearance to more foregoing other embodiment, this iterative decoding handle and can repeat by predefined iterations (as, repeat n time, wherein n is optional).Alternatively, repeat these iterative decoding treatment steps, the syndrome of encoding up to LDPC is equal to 0 (in a certain accuracy).

During each decoding iteration, more produce the soft output information (comprising a code element layer and a position layer both information) of mixed type in the new processor in sequence of symhols and symbol node.In this embodiment, this soft output can be offered a hard limiter, it can make hard decision, and this hard information can be provided to a syndrome calculator, is equal to 0 (in a certain accuracy) with the syndrome that determines whether the LDPC coding.That is to say the syndrome calculator determines whether each syndrome that is relevant to the LDPC coding equals 0 in fact in predetermined a certain accuracy rating.For example, when a syndrome has mathematical non-0 value, it is less than defined certain threshold value of predefined a certain accuracy, and this syndrome can be considered to equal 0 in fact so.When a syndrome has mathematical non-0 value, it is greater than defined certain threshold value of predefined a certain accuracy, and this syndrome can be considered to be not equal to 0 in fact so.

When syndrome is not equal to 0 basically, this iterative decoding handle continue to utilize again at least one sequence of symhols and symbol node more new processor and at least one verification engine processor by suitably upgrading the mixing combination that is relevant to a piece node and block of symbols node edge messages and about the edge messages of check block node.All these iterative decoding treatment steps are finished, the best estimate of so one or more code elements, and be included in position (forming code word jointly) in it exported based on mixing soft information (as, a soft information of code element and a soft information).

When syndrome is not equal to 0 in fact, this iterative decoding is handled and is continued to use again this at least one sequence of symhols and symbol node more new processor and this at least one verification engine processor, and the edge messages of the mixing combination that is relevant to a piece node and block of symbols node and the edge messages that is relevant to the check block node are suitably upgraded.All these iterative decoding treatment steps execute, so based on mixing soft information (as, the soft information of soft information of code element and position), and the best estimate of exporting one or more code elements, this position is contained in wherein (cooperating and forming a code word).

Figure 53 A is the legend according to a kind of embodiment of the first step of LDPC of the present invention position-verification parallel decoding processing.This figure shows simply with respect to the left memory of edge messages and with respect to the right memory of edge messages, and how P engine processor and P verification engine processor are operated.In very first time section, when P position engine processor just during the edge messages in update package is contained in the left memory of edge messages, P verification engine processor be the edge messages in update package is contained in the right memory of edge messages just.Then, engine processor and P position, P position engine processor replaces the visit of two memories.In second time period, when P position engine processor upgrades edge messages in the right memory be included in edge messages, P the interior edge messages of left memory that the verification engine processor upgrades to be included in edge messages.Notice that once more left memory and right memory can be two independent memory devices (as, the memory of single access type).Alternatively, right memory and left memory can be gone up at the logical partition in the single memory equipment (as the memory of dual port access type) and realize.

Figure 53 B is the legend according to a kind of embodiment of the first step of LDPC code element of the present invention-verification parallel decoding processing.This figure shows simply with respect to the left memory of edge messages and with respect to the right memory of edge messages, and how P code element engine processor and P verification engine processor are operated.In very first time section, when P code element engine processor just during the edge messages in update package is contained in the left memory of edge messages, P verification engine processor be the edge messages in update package is contained in the right memory of edge messages just.Then, P code element position engine processor and P verification engine processor are to the visit of these two memories alternately.During second time period, during edge messages in P code element engine processor update package is contained in the right memory of edge messages, P verification engine processor update package is contained in the edge messages in the left memory of edge messages.Notice that once more left memory and right memory can be two independent memory devices (as, the memory of single access type).Alternatively, right memory and left memory can be gone up at the logical partition in the single memory equipment (as the memory of dual port access type) and realize.

Notice equally, method described in the figure of front also can be in any suitable designed system and/or equipment (communication system, communications transmitter, communication sink, communication transceiver, and/or functional block described herein) carry out in, these systems and/equipment is in preceding existing description, and without departing from the spirit or scope of the invention.

And, notice various functions equally, system and/or device design, the method that reaches related embodiment described herein all can be carried out in log-domain, can use add operation to carry out multiplication moral conduct and use subtraction execution divide operations thus.

About the above-mentioned the present invention and the description of accompanying drawing, other modification and variation are conspicuous.Equally significantly, this other modification and variation can realize, and without departing from the spirit or scope of the invention.

Claims

1, a kind of decoder can be carried out LDPC position-verification parallel decoding, and this decoder comprises:

Symbol node calculator function piece, it uses a plurality of m bit symbols yardsticks to calculate a plurality of yardsticks;

The iterative decoding function blocks, it can use the edge messages of a plurality of a plurality of the piece nodes corresponding to minimum of a plurality of soft information initializings, to support the processing of position-verification parallel decoding in the decoding iteration of the default a plurality of execution sequences management of basis subsequently;

2, decoder according to claim 1, wherein:

After the iterative decoding function blocks was carried out final decoding iteration according to predetermined a plurality of execution sequences, the iterative decoding function blocks can be resequenced to a plurality of positions that according to predefined a plurality of execution sequences second piece node changing taken place; And

Should allow this iterative decoding function blocks to export the soft estimation of the code element position of ldpc coded signal according to an order corresponding to a plurality of of second piece node reorder, in this order, information bit be encoded in the ldpc coded signal at first.

3, decoder according to claim 1, wherein:

After this iterative decoding function blocks is carried out final decoding iteration according to predefined a plurality of execution sequences, this iterative decoding function blocks can be carried out an extra decoding iteration and not need execution sequence control, is so naturally resequenced in a plurality of positions that taken place to change according to predefined a plurality of execution sequences corresponding to second piece node; And

4, according to each described decoder in the claim 1 to 3, wherein:

5, decoder according to claim 4, wherein:

6, a kind of Wireless Telecom Equipment, this equipment comprises:

Radio-frequency front-end, it is used for receiving and the filtering continuous time signal, and this signal comprises that at least one has used the LDPC coding to carry out the information encoded position;

Analog to digital converter, it is used for the continuous time signal of this reception and filtering is sampled, thereby produces discrete-time signal and therefrom extract I, Q component;

Demodulator, the symbol mapped that it is used to receive I, Q component and carries out I, Q component, thus produce centrifugal pump modulated symbol sequence; And

LDPC position-verification code parallel decoder, it is used for the code element of centrifugal pump modulated symbol sequence is decoded, so that at least one information bit that is included in it is carried out best estimate;

Wherein, but this LDPC position-verification code parallel decoder initialization is supported the processing of position-verification parallel decoding corresponding to a plurality of edge messages of a plurality of piece nodes of minimum in the decoding iteration with a plurality of execution sequences management of being predetermined in subsequently basis;

7, Wireless Telecom Equipment according to claim 6, wherein:

This LDPC position-verification code parallel decoder comprises a plurality of engine processors;

8, a kind of method that is used to carry out LDPC position-verification parallel decoding, this method comprises:

Receive and the filtering continuous time signal, this signal comprises that at least one has used the LDPC coding to carry out the information encoded position;

Continuous time signal to this reception and filtering is sampled, thereby produces discrete-time signal and therefrom extract I, Q component;

Code element to centrifugal pump modulated symbol sequence is decoded, and to utilize the LDPC position-verification parallel decoding by predefined a plurality of execution sequence controls, at least one information bit that is included in it is carried out best estimate;

Wherein, LDPC position-verification parallel decoding is carried out in this decoding, comprising: in very first time section, upgrade corresponding to a plurality of edge messages of first piece node synchronously and upgrade a plurality of edge messages corresponding to the first check block node;

Wherein, LDPC position-verification parallel decoding is carried out in this decoding, comprising: in second time period, upgrade corresponding to a plurality of edge messages of second piece node synchronously and upgrade a plurality of edge messages corresponding to the second check block node;

9, a kind of method of carrying out LDPC position-verification parallel decoding is characterized in that this method comprises:

Wherein, this decoding initialization is corresponding to a plurality of edge messages of a plurality of piece nodes of minimum, supports the processing of position-verification parallel decoding in the decoding iteration with a plurality of execution sequences management of being predetermined in subsequently basis;

Wherein, a plurality of edge messages are corresponding to a plurality of edges, and these a plurality of edges will be connected with a plurality of check block node communications ground corresponding to a plurality of piece nodes in the LDPC piece bipartite graph of LDPC coding, and ldpc coded signal produces by this LDPC coding;

Wherein, after carrying out final decoding iteration, resequenced in a plurality of positions that according to predefined a plurality of execution sequences second piece node changing taken place according to predetermined a plurality of execution sequences; And

Wherein, should allow to export the soft estimation of the code element position in the centrifugal pump modulated symbol sequence to the rearrangement of carrying out corresponding to a plurality of positions of second piece node according to an order, in this order, at least one the information bit original adoption LDPC that is contained in wherein encodes.

10, a kind of method of carrying out LDPC position-verification parallel decoding, this method comprises:

Wherein, after carrying out final decoding iteration according to predetermined a plurality of execution sequences, carry out an extra decoding iteration and do not need execution sequence control, so naturally resequenced in a plurality of positions that taken place to change according to predefined a plurality of execution sequences corresponding to second piece node; And

Wherein, the rearrangement of carrying out corresponding to a plurality of positions of second piece node is allowed to export according to an order the soft estimation of the code element position in the centrifugal pump modulated symbol sequence, in this order, at least one information bit that is contained in has wherein adopted LDPC to encode at first.