CN102314396A

CN102314396A - Method and device for accessing bytes by taking a block as base flash

Info

Publication number: CN102314396A
Application number: CN2010102244411A
Authority: CN
Inventors: 洪俊雄; 何信义; 李祥邦
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2010-07-06
Filing date: 2010-07-06
Publication date: 2012-01-11
Anticipated expiration: 2030-07-06
Also published as: CN102314396B

Abstract

The invention discloses a method and device for accessing bytes by taking a block as a base flash. In the technology, the requirement that data bytes stored in a flash memory every time need to be updated after a sector erasure operation can be avoided by using a one-erasing and multiple-programming progressive index structure to manage data in the flash memory. A data structure stored in an addressable sector of an array comprises index data, state data and bytes of the data so that a logic address is mapped to the sector, and one-erasing and multiple-programming program management can be used. The result is as follows: a great deal of write-in operation can be carried out at a given sector before one sector erasing operation. Therefore, flash can be used for accessing bytes at high speed.

Description

Block is the method and apparatus of the byte access of basic flash memory

Technical field

The invention relates to flash memory technology, particularly about the high speed of flash memory devices, random-access data management technique.

Background technology

Electrically programmable erasable read-only memory (EEPROM) and flash memory comprise the storage unit of Charge Storage between passage and field-effect transistor grid.Stored electric charge can influence transistorized threshold voltage, and threshold voltage can change and can be used for the sensing designation data according to stored electric charge.Wherein a kind of very habitual charge storage memory cells is called as a floating gate memory cell.In a floating gate memory cell, it can store charge in the conductive material layer between passage and the grid.Another kind of charge storage memory cells kenel is called as a charge capturing storage unit, and it can use a dielectric layer to replace floating grid.

Noun as used herein " write " be meant the operation that changes transistor threshold voltage, and be to be used for comprising the operation that increases and reduce transistor threshold voltage.In electrically programmable erasable read-only memory (EEPROM) and flash device; Write operation at first involves an erase step; All storage unit in one storage compartments are set to erase status; Carry out a programming step afterwards again, storage unit selected in this storage compartments is set to programming state.Noun as used herein " programming " then be meant and in a flash memory, utilize the then operation carried out of the mode of a byte of a byte; Noun as used herein " wipe " then be meant because the relation of flash memory cell configuration the operation of normally carrying out with the section or the mode of block.Therefore, in flash memory, for the single byte of programming, write operation must be wiped bigger section in this storage array earlier, and is whole section storage data again again.

Storage unit in an electrically programmable erasable read-only memory (EEPROM) device can utilize a byte then the mode of a byte wipe and irrelevant with other data byte.Yet in order to want the then erase mode of a byte of activation one byte, the storage density of this electrically programmable erasable read-only memory (EEPROM) is relatively low.

Electrically programmable erasable read-only memory (EEPROM) and flash memory devices are normally as different application.Generally speaking, because its higher density, flash memory is more economical than electrically programmable erasable read-only memory (EEPROM) in the mass data storing application facet.And electrically programmable erasable read-only memory (EEPROM) is that then the reading and writing data of a byte is more suitable carrying out a byte to small amount of data, for example is that storing state data or configuration data etc. need to change frequently or similar data etc.

Include electrically programmable erasable read-only memory (EEPROM) and flash memory in many electronic installations simultaneously, to satisfy the difference storage need for exhibition of difference in functionality in this device.Yet, use the storer of these two kinds of kenels to increase the cost and the complexity of this device simultaneously.

It is exactly that it has limited permanance that flash memory can produce a specific problem, and the number that the storage unit in this device can be kept wiping of its operability and reliability and/or program cycles is limited.Therefore, repeat and write single section constantly, or the section of minority, can cause some section after the short relatively time, to become aging also defectiveness.

Different " mean consumption " technology is suggested to prolong the life-span of flash memory.The number of times that a kind of mean consumption scheme is to use each section of record to be wiped free of.This counter is used to adjust data then and is mapped in other section, with its consumption of balance.Can consult United States Patent (USP) the 6th, 000,006,5,485,595 and 5,341, No. 339 patents.

Though usage counter can prolong the life-span of flash memory devices, yet limited read/write endurance issues still can limit the application of flash memory at more number of times programming of needs and erase operation.

Another kind of mean consumption scheme is to write the provider location that not having in the flash memory devices used with Updating Information, rather than covers Data Position originally again.Section erase operation number in the time of so can reducing the given write operation in the flash memory devices.Can consult United States Patent (USP) the 5th, 845,313 and 6,115, No. 785 patents.

For the physical location change of trace data, can use programmable mapping table or address translation table.Programmable mapping table stores by the indicated logical address of an external system and comprises the map information between the flash memory devices physical address of valid data.In order correctly to follow the trail of the physical location of valid data, this programmable mapping table must be updated when operation.

Be held in order to ensure valid data, this map information must be held when interrupting power supply.Yet,, store this map information can reduce this device in flash memory life-span because this programmable image address translation tables is upgraded constantly.Because the erasing speed that flash memory is slow relatively so can seriously influence the performance of the device that uses flash memory.This programmable image address translation tables perhaps can alternatively be stored in another non-volatile memory circuits in this device.Yet, also can increase the cost and the complexity of this device.

Therefore need provide a kind of flash memory devices its go for need be as the Performance Characteristics of the high speed byte access of electrically programmable erasable read-only memory (EEPROM), and also can utilize lower cost and complexity and solve endurance issues simultaneously.

Summary of the invention

The present invention is the method that discloses a kind of operation one flash memory, and it is applicable to the high speed bytes store.The method comprises a plurality of sections of the data storage cell that has sector address in this flash memory of arrangement to store data structure separately; Wherein a data structure is arranged to the byte (or data set of other N bit wide) of storage data; It is by the identification of logical address institute, and comprises an index field and a data field position.Through wiping this index field and this data structure of initialization is come in this data field position.The logical address of the byte of these data reflection to the sector address of the section of storage one data structure of these data.The byte that writes these data has a logical address and particular section matching addresses; A particular section address in this data field position of this this data structure of programming; Wherein the line segment of the particular word pitch width in this data storage cell and this data field position is corresponding, and in this data structure of programming corresponding byte wide line segment to store the byte of these data.In order to respond a logical address to read the byte of these data, the index field in this data structure is used for distinguishing the line segment of this particular word pitch width that stores available data.This available data is provided and responds a read operation.

In one embodiment; This data structure comprises that an index field comprises a localizer field and has a cell stores M position (for example 28); In section, have sequence of addresses, and comprise a data field position, it comprises the line segment of the M byte wide of arranging in regular turn (for example 28 bytes).Each of this order M position, address can be corresponding with of M byte wide line segment in the identical address order.Last of M position has been programmed one that corresponds to this M byte wide line segment of most recently used in the data field position in this localizer field.

Among the described herein embodiment, provide an index field to comprise a localizer field and store the M position, and this data field position comprises the M byte wide line segment of arranging according to sequence of addresses according to sequence of addresses.When each data storage cell stores a single position, then the localizer field comprises M data storage unit.When storing in the localizer field that a primary data storage cell is programmed and remaining data storage cell when in this localizer field, still keeping wiping; First of the sequence of addresses of this this byte wide line segment of localizer field sensing; When this first of this storage and a deputy storage unit is programmed and remaining data storage cell when in this localizer field, still keeping wiping; This localizer field point to this byte wide line segment sequence of addresses the two; And when all these M positions in this localizer field all were programmed, this localizer field was pointed to last person of the sequence of addresses of this byte wide line segment.

Among the described herein embodiment, this data structure provides an index field, and it comprises a state position of this data structure, and all storage unit in the index field are at erase status after initialization.This state position comprises at least K-1 position arranges according to sequence of addresses, and present one of state is carried out in K of indication when this data structure of initialization.According to an example described herein, an original state wherein in this state position all K-1 positions all be wiped free of.Be programmed for a primary data storage cell and remaining data storage cell of this state position when being wiped free of at one first state when this state position of storage;, and all be programmed for being programmed when this first and one deputy one or more data storage cell that stores this state position and remaining data storage cell of this state position when being wiped free of at one second state a final state all these K-1 for this state position.

To the use in the data handling system, the address translation table can store the logical address that the data byte of the storage unit of section in this flash memory is videoed.A plurality of data structure described herein can be initialised in the section in storage unit separately, and according to the logical address of address translation tables with its reflection to correspondence.State position in the index field is used for the state of management data structures to keep the correct of address translation table.

Under the situation that all byte wide line segments in a specific data structure all are used; Present byte in the data structure can be copied to a new data structure, and this address translation tables can be used for upgrading so that old data structure is videoed to new data structure.Management is copied to a program in the new data structure with present byte and comprises this state position of renewal.For example, the state position can comprise 4 positions, and can be used for representing 5 states.By the original state of state position indication is to represent this data structure to be initialised and do not have logical address to be mapped to this data structure.By first state of state position indication is that the new data structure of representing logical address to video is selected and is fit to be used for replace old data structure.By second state of state position indication is that representative writes present data byte to new data structure from source data structure (or other data structure) and accomplishes.The third state by the indication of state position is to represent the program of wiping to begin to reinitialize old data structure.By the four condition of state position indication be represent one wipe old data structure program accomplished, and the extremely new data structure of reflection is effective.

One flash memory can comprise in the program that block border is wiped distributes first and second block, and each block comprises L section, in L logical address of this flash memory.In this program; Comprise of this first and second block of wiping this L section that comprises this particular section in this data structure of particular section initialization; And, stored data in the data structure of the section of this first block are moved to the data structure in this second block when in this data structure in this first block during the write operation of position, M N bit data territory experience (for example this data structure is full).

In addition, the present invention also discloses a kind of flash memory, comprises a plurality of sections of the data storage cell with sector address, have logic with according to said method storage data structure in this flash memory, to carry out reading and write operation of byte mode.This device also comprises a data processor; It is integrated on the identical chip with this flash memory; Or can this flash memory of access in a computer system; And comprise and to comprise the instruction of the said method that can on a flash memory, carry out described herein by the instruction of this data processor execution.These can be by the performed instruction of this data processor, can be stored in this flash memory or other can be by this data processor institute access part.

The present invention also discloses a kind of machine-readable data storage device; Comprise a machine-readable data storing media; Storage can be by the instruction of processor execution, and this processor has the function of access one storage array, and this storage array comprises a plurality of sections of the data storage cell with sector address.This instruction comprises the logic of carrying out said method.

Technology described herein adds that to the operation of byte wide reference value is to help understanding.This program can be from writing a byte (for example 8) sometimes, writes any N bit wide data set (for example 16 or 32) sometimes and produce, and has understanding prior art and suitably adjusting the situation of size of the data field position of this data structure.

In addition, noun as used herein " section " or " block " be meant one group or array data storage unit.These nouns be not be used for limiting one group or array data storage unit must be strictly corresponding with the actual section of flash memory, though in can described herein program will " section " or " block " can have its advantage with the actual section of flash memory is corresponding.

Technology use described herein is wiped one-time programming progressive index structure repeatedly and is managed the data in the flash memory devices, can avoid carrying out the demand that the section erase operation just must upgrade afterwards at the data byte that will be stored in the flash memory devices at every turn.Be stored in byte that data structure in the addressable section of this array comprises index data, status data and these data for the logical address section so far of videoing, it can use wipes one-time programming program management repeatedly.Consequently, can, a given section carry out the write operation of larger amt before need carrying out a section erase operation.So flash memory can be used as the usefulness of high speed byte access.

The object of the invention, characteristic, and embodiment, graphic being described of can in the chapters and sections of following embodiment, arranging in pairs or groups.

Description of drawings

The present invention is defined by the claim scope.These and other purpose, characteristic, and embodiment, graphic being described of can in the chapters and sections of following embodiment, arranging in pairs or groups, wherein:

Figure 1A shows the concise and to the point block schematic diagram of a computer system, and it is applicable to the usefulness of the data placement of the flash memory devices that uses technology described herein.

Figure 1B shows the block of the stored data structure of flash memory that the high speed byte access is used or the data placement of section.

Fig. 2 is shown in the data array in the example block, and it comprises a plurality of sections.

Fig. 3 shows the reflection example of a logical address, and it is the mapping that in the logical address of 128 bytes and flash memory devices physical address space, has a block of 128 sections.

Fig. 4 is shown in the interior data array of data structure of a section of an example data storage unit.

The synoptic diagram of translating between Fig. 5 display entity address space and the logical address space.

Fig. 6 is the process flow diagram of a write operation according to an embodiment of the invention, and it is to store byte to a specific logic address that Updates Information.

Fig. 7 be shown in operation the time programme in this index field one be wiped free of data storage cell example.

Fig. 8 is the process flow diagram of a read operation according to an embodiment of the invention, and it is the data that read specific logic address.

Fig. 9 is the process flow diagram of an editing operation according to an embodiment of the invention.

Figure 10 is the process flow diagram of a conversion operations 1000 according to an embodiment of the invention, and it is when the editing operation of Fig. 9, to change to be stored in the data in the status indicator field.

Figure 11 shows according to the interclass graph of a relation of different software in one embodiment of the invention flash memory devices.

Figure 12 shows according to the present invention the interclass graph of a relation of different software in the one second embodiment flash memory devices.

[main element symbol description]

100: computer system

112: bus sub

114: processor

116: network interface

118: telecommunication network

120: flash memory devices

122: user's interface input media

125: block

128: section

130: user's interface output unit

200: the primary data zone

210: write records area

230: write the record data

300: logical address space

310: the physical address space

520: the address translation table

1110: low order quickflashing application programming interfaces

1120: intelligent quickflashing application programming interfaces

1130: user's program code

1200: byte read-write mode zone

1210: flash memory devices access mode zone

Embodiment

The following Fig. 1 of embodiment of the invention collocation is described in detail to Figure 12.

Figure 1A shows the concise and to the point block schematic diagram of a computer system 100; It is applicable to use technology described herein comprise the usefulness of block for storage subsystem 120 data placements of basic flash memory devices, it for example is the usefulness of the compatible flash memory devices data placement of SPI (SPI) that this flash memory devices can be.Computer system 100 comprises at least one processor 114 usually, and it sees through bus sub 112 and links up with many peripheral units.These peripheral units can comprise extra flash memory devices (not shown), user's interface input media 122, user's interface output unit 130 and a network interface subsystem 116.These input-output devices can allow user and computer system 100 interactions.Network interface subsystem 116 is as the interface that offers with external network, comprise an interface with telecommunication network 118, and the corresponding interface device that sees through in telecommunication network 118 and other computer system couples.Computer system and communication that telecommunication network 118 can comprise many interconnection connect.It can be the mechanism of wired connection, optical fiber connection, wireless connections or out of Memory transmission that these communications connect.The telecommunication network 118 of one of them embodiment is the Internets, but telecommunication network 118 can be any suitable computer network in other embodiment.

User's interface input media 122 can comprise keyboard; Indicator device for example is a mouse, and trajectory track device, Trackpad or figure flat board, scanner, Touch Screen, acoustic control input media for example are input medias of voice recognition system, microphone or other kenel or the like.Generally speaking, use this noun " input media " be that representative is hoped to comprise institute and might be used for input information entering computer system 100 or the device kenel or the mode of telecommunication network 118.

User's interface output unit 130 can comprise for example voice output or the like of demonstration subsystem, printer, facsimile recorder or non-Visual Display.This shows that subsystem can comprise for example LCD of iconoscope (CRT), flat display apparatus, a projection arrangement, and other produces the mechanism of vision imaging etc.This demonstration subsystem also can comprise provides for example voice output of non-Visual Display.Generally speaking, use this noun " output unit " be representative hope to comprise might be used for from computer system 100 or the device kenel or the mode of other machine output information.

Storage subsystem 120 flash memory devices 120 store basic programming and data structure; It provides the function described in some embodiment here; Comprise the address mapping of logic to entity and the instruction of translating, and be used for the instruction (meeting is in following description) of data placement in these storage subsystem 120 flash memory devices 120.These software modules are normally carried out by processor 114, and basic programming and data structure can be stored in flash memory or other the memory storage.In addition, this storage subsystem 120 can comprise other storage device, comprises that random-access memory (ram) with save command or data when program is carried out, can take memory storage, disk drive system etc.

This storage subsystem 120 can comprise the machine-readable data storage device; Comprise the stored instruction of machine-readable data storing media that storage can processor be carried out; This handles utensil has access to comprise the ability of the storage array of a plurality of data segments storage unit, and wherein these instructions comprise the logic that can carry out program described herein.

In illustrative embodiment, processor 114 execution commands are to carry out the many operations that comprise that flash memory devices is outer described herein.Alternatively, this flash memory devices comprises that a processor or the controller of other kenel are with the control data management and carry out many operations described herein.For example, this controller can be to use the state machine that special function logic circuit that industry knows constitutes.In the embodiment that substitutes, this controller comprises general purpose processor, and it can be applied on the same integrated circuit, to carry out the computer program of this flash memory devices 120 of control.And in another embodiment, the combination of general purpose processor and special function logic circuit can be used for implementing this controller.

Bus sub 112 provides a mechanism that elements different in the computer system 100 and subsystem can be linked up as needed each other.Though the bus sub 112 that is shown in graphic is unified buss, the alternate embodiment of bus sub 112 can be used multiple trunk.In certain embodiments, data, address and the command signal between flash memory devices 120 and bus sub 112 can utilize serial mode to be applied on the shared line SPI that for example can use industry to know.

Shown in Figure 1B, a flash memory can have a plurality of physical blocks, and it comprises block 0125-0 to block K 125-K, utilizes the data of above-mentioned Technical arrangements with storage.Block 0125-0 to each block among the block K 125-K can independent wiping in other block.The size of this block can be looked the different of embodiment with number and changed.For example, in certain embodiments, the size of each block can be 2KB, 4KB, 8KB or 16KB.Alternatively also can use other block size.

As described above, this flash memory also can comprise extra block storing the logical and physical address reflection and the instruction of translating, and as above-mentioned with data allocations in the instruction of block 0125-0 to block K 125-K.

Instruction comprises from the logical address of the specified flash memory devices 120 of computer system 100 and flash memory devices 120 block 0125-0 to the reflection between the physical address of block K 125-K.

Each comprises one or more sections to block 0125-0 to block K 125-K.For example, the block of a 4KB can comprise the section of 128 32 bytes.In these 128 sections each can comprise the data structure that stores a byte data.128 logical addresses, 128 sections in the block so far of can videoing.As following described, sector address is videoed to the specific logic address of data byte, and is applicable to the data structure of storage as byte access.

The data structure of describing herein in the given section of the data storage cell in the example comprises an index field and a data field position.This index field comprises the localizer line segment of a particular word pitch width in the data field position so far, and this data field position is to be used for storing the logical address that this data byte is videoed.In an embodiment, one of section index field also comprise storage data the status indicator field to indicate the state of this section.In the described herein example, the section state maintains in the border of block, and indicates the state of section in the block, and for example whether the section in a given block is work (working), inoperative (being wiped free of), pollution or temporary transient data at present.Therefore, all data structures in this block must have identical state.Alternatively, the section state can maintain in the section boundaries.In addition, in certain embodiments, each block can use an independent status indicator, and is not contained in the index field of data structure of each section.

When write operation; Eraseable memory unit in index field be programmed with upgrade this localizer so far in the data field position line segment of byte wide be wiped free of that, and the line segment of this byte wide be wiped free of that in the specific data storage cell of wiping be programmed to store the reflection logical address of this data byte.

For the purpose of clear, in the following example, this noun " programming " be meant the data value in the storage unit is changed to logic " 0 " and operation, and " wipe " and be meant the data value in the storage unit is changed to logic " 1 " and operation.With programming and the pairing data of erase status also can be respectively 1 and 0.In addition, in multi-level cell memory, programming can be assumed to be a plurality of values.Yet; As before described; This noun " programming " typically refer in flash memory the then operation that storage unit is carried out for the basis of a storage unit; And because the cause of flash memory cell configuration, " wipe " be meant the operation of being carried out for the basis in a big way in the flash memory, in the scope that can in a given array structure, effectively carry out.Therefore, according to the configuration of flash memory cell, programming in certain embodiments and wiping comprises minimizing respectively and increases threshold voltage.

The size of this data field position must a block or section carry out the frequency of erase operation and the logical address number of the given block of flash memory devices so far of can videoing between do to accept or reject (following will the discussion), and therefore can look the difference of embodiment and change.

This flash memory devices also can comprise a plurality of inoperative blocks or section, and it can Update Information to store every now and then as a preparation unit when the data field position in a present data structure is full.

Fig. 2 shows the data array in the block, it comprise a plurality of from section 0 section to section M.In an embodiment, section 0 perhaps can be wiped to each section of section M independently.And in the described herein example, section cannot be wiped independently, but erase operation is the usefulness of in block border, carrying out with as the high speed byte access in this array segment.Shown in Figure 1B, data structure is placed in addressable section, and comprises that an index zone stores index field and position, storage data territory is come in a data area.

Data structure in section 0 comprises an index field 200-0, and it comprises the localizer line segment of a particular word pitch width among the 202-0 of data field position so far, and it stores the data byte of counterlogic address.This localizer is represented a series of programming and eraseable memory unit among this index field 200-0.

When having the write operation of videoing to a byte of the logical address of section 0 data storage cell; Obliterated data storage unit in this index field is programmed the line segment that points to a particular word pitch width among the data field position 202-0 so far with the localizer that upgrades index field 200-0; It stores the data byte of counterlogic address, and the line segment of this byte wide be wiped free of that in the specific data storage cell of wiping be programmed to store the reflection logical address of this data byte.

In this illustrative example; Data storage cell in index field is programmed with sequence of addresses in order to respond write command separately; First beginning of the data storage cell in the index field of first write operation; Be second of second write operation then, still keep wiping until be programmed storage unit data storage cell afterwards recently.Similarly; The line segment of the byte wide in the data field position for example is that the mode of sequence of addresses writes according to one; The first byte wide line segment from first write operation begins; Be the second byte wide line segment of second write operation then, until the byte wide line segment after being programmed still keeps wiping (or empty) recently.

In alternate embodiment, for the data storage cell of write command in index field that responds separately is programmed in regular turn, and the byte wide line segment in the data field position also writes in regular turn, and both orders can be with different shown in Fig. 2.For example, the data storage cell in the index zone can be from the final data storage unit starting program in the index field of first write operation, by that analogy.

Through writing the byte wide line segment that Updates Information and be wiped free of to the 202-0 of data field position; Rather than utilize an erase operation directly it to be covered, be used for upgrading localizer and data storage cell and need do not experience the program of wiping with the data storage cell to index field that stores the updating data byte that is programmed.So can in a programming operation, compare, only need the block of a decimal or the erase operation of section, and can increase the endurance of flash memory effectively with the number of write operation.

Because Update Information is the empty sections that writes in the data field position, and it is full that this data field position finally can become.Therefore; In the block 1 section 0 to the stored data structure of section of section M otherwise the time use the then then mode of a block of section or block of a section, again reflection to block 0 in section 0 in the data structure of the section institute mapping of section M.This noun " frequently " be meant once in a while, and do not need rule or regularly or with the time interval that equates carry out.

The data that are stored in index field 200-0 status indicator field except use distinguish the state of section work in this block 1 or inoperative, and the data in the status indicator field are used to also confirm that this section that Updates Information is by layout and correctly be stored in the new block.These following Fig. 9 that can arrange in pairs or groups describe in more detail.

Fig. 3 shows the video reflection example of the block with section-0 to section-127 to the flash memory devices 120 physical address spaces 320 of a 302-0 to 302-127 of logical address group in logical address space 300.In this illustration, each logical address in the logical address space 300 is mapped to the section of 32 bytes of data storage cell in the corresponding physical address space 320.Therefore, logical address 0000000 (reference number 302-0) is mapped to section 0304-0, and logical address 0000001 (reference number 302-1) is mapped to section 1304-1, by that analogy.

In this example, each section of data storage cell comprises the index field of one 4 bytes and the data field position of one 32 bytes, and is used for storing the data of 8 (1 bytes) of institute counterlogic address.Therefore, in this example, in the data field position of a given section of data storage cell, can become and support 32 single byte write operations to institute counterlogic address before full in the data field position.

Fig. 4 is the data placement among the display block 0304-0 more.As shown in Figure 4, the section 0304-0 of data storage cell stores the data structure that comprises index field 400 and data field position 410.In this illustration, the data of index field 400 metas 0～27 constitute and are used for a particular word pitch width line segment of stored logic address 0000000 (reference number 302-0) 8 bit data of videoing in a localizer 420 to the data field position 410.The data of the position 28～31 in the index field constitute a status indicator field 430; One state of its this section of indication; The mode that in this example, is the basis with a block keeps, and indicates the common state (following meeting is described in more detail) of all section section-0 to sections-127.

As shown in Figure 4, position 0～27 data constitute a localizer 420 and come to be used in the position, recognition data territory 410 particular section of stored logic address 0000000 (reference number 302-0) 8 bit data of videoing.For example; As far as the application of every one storage unit, if the data of index field meta 0 are programmed, and the storage unit of all the other all positions 1～27 is wiped free of; This localizer 420 can point to section d0, and it is first section of the sequence of addresses in the data field position 410.If the data of index field meta 0～1 are programmed, and the storage unit of all the other all positions 2～27 is wiped free of, and this localizer 420 can point to section d1, and it is second section of the sequence of addresses in the data field position 410.Also can use alternatively technology to come arranging data to think that which particular section of localizer 420 identifications can use.In addition, in the embodiment of multiple position storage unit, a data storage cell can store two bits or above localizer.

The synoptic diagram of translating between Fig. 5 display entity address space and the logical address space.Logical address is to use an address translation table 520 that it is mapped to corresponding block.As far as a specific logical address, these address translation tables 520 identifications block and section of the corresponding data storage cell of logical address therewith provide the block that corresponds to logical address.The localizer of index field that is stored in the data structure of corresponding data storage unit is read then with identification and stores the section in the data field position of this logical address data.

The use of localizer has been got rid of at flash memory devices 120 and has been Updated Information or demand that just must scheduler translation tables 520 after the work section in this block is changed at every turn, and correct tracking that can the activation valid data.Because address translation table 520 does not need to upgrade constantly, it can be stored in the flash memory devices 120.When operation, address translation table 520 can be extracted in the storer of higher access speed, for example the DRAM of Fig. 1 processor or SRAM.

Fig. 6 is process flow diagram by processor 114 performed write operations 600 according to an embodiment of the invention, and it is storage data byte or other N bit data section to a specific logic address.Like process flow diagram shown here; Should be appreciated that many steps can be combined; Carry out abreast or carry out and can not influence the effect being desired to reach with different orders, in some cases, only rearranging of different step can just can be reached identical effect adjusting some step in the lump; And in some cases, different step rearranges only can be satisfied just in some condition and can reach identical effect.So rearrange and will be apparent to those skilled in the art.

In order to respond the write command of storage data byte to a specific logic address, in step 610, the address translation table of discussing before using decides the corresponding so far block or the section of the data storage cell of specific logic address.

In step 615, the localizer of index field that is stored in the data structure of corresponding data storage unit is read to store with decision then wipes section to store this data byte in this data field position.

In step 620, if not comprising, this data field position do not wipe section, then this data field position is full.Under situation like this, this operation 600 proceeds to square 630, wherein for this reason section store this data structure the structure that Updates Information by layout.This editing operation meeting is explained at following collocation Fig. 9.

Wipe section if this data field position comprises, then this operation 600 proceeds to square 640.In step 640, the obliterated data storage unit in index field is programmed to upgrade this localizer and so far is wiped free of section, and this Updates Information and is written into this and is wiped free of section.This operation 600 stops at step 650 then.

Fig. 7 is shown in the example of obliterated data storage unit in this index field of programming when operating.As shown in Figure 7, position 0～27 is used for storing localizer, and position 28～31 is used for storing a status indicator field, a state (following meeting is described in more detail) of its this section of indication or block.In this example, to be configured to indicate section be work to the status indicator of each section in this block, and its all positions are programmed to " 00000 ".

As shown in Figure 7; In order to respond one first write operation, this localizer upgrades through storage unit to the logical zero of program bit 1, when second write operation; The storage unit of program bit 2 is to logical zero, till 28 positions of all in this localizer field all are programmed to logical zero by that analogy.In this programming process, need not carry out erase operation.Though the given byte in this localizer field in programming process by access repeatedly; But because in this byte, do not change to the words of erase status if there is storage unit to need to programme certainly; One programming process is to carry out that byte reads or other similar step is wiped preventing in advance, so need not carry out erase operation.

In alternate embodiment, can use and the data storage cell in the index field of programming of the different order shown in Fig. 7.For example, in order to respond first write operation, the order starting program of the last position 27 that the data storage cell in the index zone can be in the data storage cell of localizer, by that analogy.

Fig. 8 is process flow diagram by processor 114 performed read operations 800 according to an embodiment of the invention, and it is the data that read specific logic address.

In order to respond a reading order that reads these specific logic address data, in step 810, the address translation table of discussing before using decides the corresponding so far block or the section of the data storage cell of specific logic address.

In step 820, the localizer of index field that is stored in the data structure of corresponding data storage unit is read with decision and stores (at last) in the data field position of this logical address data section of working.The data that are stored in this work section are read and export in step 830 then.

As before one of this block of the layout group that Updates Information frequently, and write to and before be the block of inoperative was discussed.

Fig. 9 is process flow diagram by processor 114 performed editing operations 900 according to an embodiment of the invention.This operation 900 can become when expiring in the data field position of the data structure in data storage cell one section of a given block or other is activated any time.

For more clearly for the purpose of the following discussion explanation, the work block before operation 900 beginnings is called " block A ", and the inoperative block before operation 900 beginnings is called " block B ".The minimum cell group that is wiped free of when employed block can be the erase operation to used flash memory in this program.The section that is distributed in each block and the number of data structure can be to any number that is applicable to a preset use pattern from 1.

In step 910, be stored in data in the active section in the block A data field position and be read and think and video to the logical address group layout one of the block A group that Updates Information.This group that Updates Information comprises the valid data of videoing to the logical address crowd of block A.

In step 920, this group that Updates Information writes in the data field position of block B section.In step 930, the address translation indumentum is upgraded so that logical address group is videoed to block B again.In step 940, block A is wiped free of.In certain embodiments, the block A erase operation in step 940 can't carry out after the reflection again of step 930 at once, but when the resource that for example is processor 114 is not carried out other operation, just carries out.

As described above, the data in the status indicator field are used to guarantee that this group that Updates Information before had been in the block of inoperative by layout and existence correctly.

Figure 10 is process flow diagram by processor 114 performed conversion operations 1000 according to an embodiment of the invention.It is the data that when the editing operation 900 of Fig. 9, change in the status indicator field that is stored in block A and all data structures of block B.

As shown in Figure 10; The position that when editing operation 900 beginning, is used for storing the data storage cell in the work block A condition identification field is in a programming state (0000), and the position that is used for storing the data storage cell in the inoperative block B status indicator field is in an erase status (1111).

B is selected when block; And before the group that Updates Information is written into the data field position of block B, in step 1010 block B section the data storage cell of all 28 positions be programmed with the data in the block B status indicator field from " 1111 " change to " 0111 ".Through mode like this just the data in the block B status indicator field change, before the group that Updates Information was written into block B, the data in this status indicator field can be with determining whether that taking place for example is the interrupt event that power supply disappears.

Afterwards, the data in step 1020 block A data structure are written in the initialization data structure of block B.Afterwards in step 1030, whether this program decision this write and accomplish.After the group that will Update Information writes in the data field position of block B (step 1020 and 1030), the data storage cell of step 1040 block B status indicator field meta 29 be programmed with the data in the block B status indicator field oneself " 0111 " change to " 0011 ".Data in the status indicator field are used to guarantee to comprise among the block B group that Updates Information of logical address group.Afterwards, can carry out the data structure erase operation of block A safely, and this logical address of videoing again.When this program of wiping begins, can be to carry out or when processor has available resource, carry out at once, the data in the status indicator field of step 1041 block B section are updated to " 0001 ".Afterwards, the erase operation of block A can be in step 1050 beginning, and this program waits to accomplish up to step 1060 and wipes.

Because the status indicator field of block A is within block, the data of the erase operation (step 1050 is to 1060) of this block A in also can the erase status identification field, it can change to " 1111 " (inoperative) with the data in the block A condition identification field.After the erase operation of this block A, the data storage cell of step 1070 block B status indicator field meta 31 be programmed with the data in the status indicator field of block B section from " 0001 " change to " 0000 " (work).

In the process flow diagram of this conversion operations 1000, with block B status indicator field from " 1111 " conversion of (inoperative) to " 0000 " (work) involves the programming that has been wiped free of storage unit in this status indicator field.This technology has been eliminated the demand of just necessary obliterated data storage unit when at every turn needing to change the status indicator field.Consequently, the data of status indicator field can be stored in block B, and do not need to store dividually.

In alternate embodiment, what the position that must be programmed when changing the data of status indicator field can be with shown in Figure 10 is different.

As above viewed, in certain embodiments, the block A erase operation in step 1050 does not need to carry out, but when the resource that for example is processor 114 is not carried out other operation, just carries out at once.

Figure 11 shows according to the interclass graph of a relation of different software in one embodiment of the invention flash memory devices 120.User's program code 1130 comprises that logic is to provide logical address and order to read and to write data flash memory devices 120 so far.

These intelligent quickflashing application programming interfaces (API) 1120 are that a software module comprises logic carrying out logic-physical address reflection and to translate, and logic read and write flash memory devices 120 so far with management data are to carry out different operating described herein.These intelligent quickflashing application programming interfaces (API) 1120 are translated order and are provided instruction to low order quickflashing application programming interfaces (API) 1110 from user's program code 1130.These intelligent quickflashing application programming interfaces (API) 1120 also use the address translation table that the logical address of user's program code 1130 is translated into corresponding physical address, and it offers low order quickflashing application programming interfaces (API) 1110 software modules then.

These low order quickflashing application programming interfaces (API) 1110 are that a software driver is specially adapted to and flash memory devices 120 collocation work.These low order quickflashing application programming interfaces (API) 1110 comprise that logic is to carry out actual reading and programming data and section instruction and the physical address that flash memory devices 120 so far provided by intelligent quickflashing application programming interfaces (API) 1120 with response of erasing.

This flash memory devices 120, low order quickflashing application programming interfaces (API) 1110 and intelligent quickflashing application programming interfaces (API) 1120 are with the then read-write of the mode co-simulation flash memory devices 120 of a byte of a byte described herein.

This flash memory devices 120 can use commercial flash memory devices commonly used to implement, for example the MX25L512CMOS serial quickflashing of Wang Hong company.Consequently; The mode that these intelligent quickflashing application programming interfaces (API) 1120 provide a simulation byte described herein to follow a byte is carried out the ability of the read-write of flash memory devices 120, does not move and do not need to write again the preceding block of erasing of must carrying out earlier of these devices.

In Figure 11, these intelligent quickflashing application programming interfaces (API) the 1120th are arranged between user's program code 1130 and low order quickflashing application programming interfaces (API) between 1110.

Figure 12 shows according to the present invention the interclass graph of a relation of different software in the one second embodiment flash memory devices 120, and wherein flash memory devices 120 comprises byte read-write mode zone 1200 and one flash memory devices accessing zone 1210.

In Figure 12, the reading and writing data of the mode of a byte is followed in the byte read-write mode zone 1200 in these intelligent quickflashing application programming interfaces (API) 1120 operating flash memory storages 120 with an emulation byte described herein.In addition; These low order quickflashing application programming interfaces (API) 1110 operating flash storage access mode region 1210 with a byte then a byte or a page then the mode of a page flash memory devices 120 is carried out data read or programme, and with a block then the mode of a block flash memory devices 120 is wiped.

In embodiment so, flash memory devices 120 can be simultaneously as an electrically programmable erasable read-only memory (EEPROM) and a flash memory.Consequently, flash memory devices 120 can replace branch other electrically programmable erasable read-only memory (EEPROM) and flash memory, and it has reduced system cost and complicacy.

Technology described herein can activation use block as the flash memory on basis among greater number information processing system.As an example, the read-write that technology described herein can the single byte data of emulation.More generally, technology described herein can be used for reading and writing uses block to be other size data in the flash memory on basis, and wherein the size of data of read-write is the size less than block.

The advantage of technology described herein comprises through being that basic flash memory replaces expensive low-density electrically programmable erasable read-only memory (EEPROM) with the block, can save the cost of system.Through implementing technology described herein, the read/write life-span of this flash memory can be increased 1000 times into surpassing traditional block access algorithm.

Though the present invention describes with reference to embodiment, right the present invention's creation is not subject to its detailed description.Substitute mode and revise pattern and in previous description, advise, and other substitute mode and modification pattern will be thought to reach by those skilled in the art.Particularly, all have and are same as member of the present invention in fact and combine and reach the identical result person in fact with the present invention, neither disengaging spiritual category of the present invention.Therefore, all these substitute modes and revise pattern system and be intended to drop on the present invention among enclose claim scope and category that equipollent defined thereof.

Claims

One kind the operation one flash memory method, comprise:

A plurality of sections of data storage cell of arranging to have in this flash memory sector address are arranged the N position of a data structure of one of these a plurality of sections with storage data, and are comprised an index field and a data field position to store data structure separately;

Through wiping this index field and this data structure of initialization is come in this data field position;

Through store in this index field of programming with this data field position in one a corresponding data storage cell of a specific N bit line segment; Write the N position of these data with a logical address, and in this data field position of this data structure of programming a specific N bit line segment to store the N position of these data; And

Have in this index field through this data structure of programming with this data field position in the corresponding another one of another different N bit line segment, the N that writes the data with this same logical address once more is arranged in this data structure, and this different N bit line segment of programming.
2. method according to claim 1 more comprises:

The sector address of these a plurality of sections of this logical address to the data storage cell of the N position of these data of videoing.
3. method according to claim 1, the N position of wherein reading these data in this data structure through a N bit line segment that reads in this data field position of distinguishing by this index field.
4. method according to claim 1; Wherein this index field comprises a localizer field and stores the M position in regular turn; And this data field position comprises in regular turn M the N bit line segment of arranging, and wherein last of M position has been programmed one of the nearest use of this M N bit line segment that corresponds in this data field position person in this localizer field.
5. method according to claim 1; Wherein this index field comprises a localizer field and stores the M position in regular turn; And this data field position comprises M the N bit line segment of arranging in regular turn; Wherein store that a primary data storage cell is programmed and remaining data storage cell when in this localizer field, still keeping wiping when this; This localizer field point to this N bit line segment sequence of addresses the first, when this first of this storage and deputy one or more data storage cell is programmed and remaining data storage cell when in this localizer field, still keeping wiping, the sequence of addresses of this this N bit line segment of localizer field sensing the two; And when all these M positions in this localizer field all were programmed, this localizer field was pointed to last person of the sequence of addresses of this N bit line segment.
6. method according to claim 1, wherein this data field position comprises M N bit line segment, comprising:

Through wiping an index field and a data field position, come another data structure in these a plurality of sections of initialization data storage unit, this another data structure comprises this index field and this data field position;

When position, the M in this data structure N bit data territory is about to experience write operation; Through the data storage cell in this index field of this corresponding other data structure of a specific N bit line segment in programming and this data field position of other data structure; The N that writes these data with this same logical address is arranged in this other data structure, and in this data field position of this other data structure of programming this specific N bit line segment to store the N position of these data.
7. method according to claim 1; Wherein this data structure comprises a state position; And this initialization comprises wipes this state position, and wherein this state position comprises K-1 position at least, and present one of state is carried out in K of indication when this data structure of initialization.
8. method according to claim 1; Wherein this data structure comprises a state position; And this initialization comprises wipes this state position; Wherein this state position comprises K-1 position at least; And present one of state is carried out in K of indication when this data structure of initialization; Comprise an original state wherein in this state position all data storage cells all be wiped free of; Wherein this K one first state of carrying out state is for being programmed when a primary data storage cell that stores this state position and remaining data storage cell of this state position when being wiped free of, and this K one second state that carries out state be for being programmed when this first and one deputy one or more data storage cell that stores this state position and remaining data storage cell of this state position when being wiped free of, and this K final state that carries out state is that all these K-1 of this state position are when all being programmed.
9. method according to claim 8; Wherein this original state is initialised and does not have the logical address reflection to this data structure; This second state is videoed for this data structure is selected; When one third state was accomplished for write the N bit data from source data structure or other source, a four condition was wiped this source data structure for beginning (if the words that have), and this final state is for wiping this source data structure when any completion and logical address are videoed to data structure.
10. method according to claim 1; Comprise and distribute first and second block; Each block comprises L section; In L logical address of this flash memory, and wherein comprise one of this first and second block of wiping this L section that comprises this particular section person in this data structure of particular section initialization.
11. method according to claim 1 comprises and distributes first and second block, each block comprises L section, and in L logical address of this flash memory, and wherein this data field position in this data structure of this section comprises M N position section, comprising:

Through wiping this second block, the data structure in this second block of initialization, and comprise:

When the position, M N bit data territory in this data structure in this first block is about to experience write operation, stored data in this first block are moved to the data structure in this second block.
12. a device comprises:

One storage array comprises a plurality of sections of the data storage cell with sector address;

The storage data structure is in the logic in a plurality of sections that store this data storage cell, and this data structure is arranged the N position of storage data, comprises an index field and a data field position in the data structure of one of these a plurality of sections;

Come the logic of this data structure of initialization through wiping this index field and this data field position;

Through store in this index field of programming with this data field position in one a corresponding data storage cell of a specific N bit line segment; Write the N position of these data with a logical address; And a specific N bit line segment is to store the N position of these data in this data field position of this data structure of programming; And have in this index field through this data structure of programming with this data field position in the corresponding another one of another different N bit line segment; The N that writes the data with this same logical address once more is arranged in this data structure, and the logic of this different N bit line segment of programming.
13. device according to claim 12, wherein at least a portion of the logic of this storage, this initialized logic and this logic that writes comprises a processor and is stored in this storage array the instruction that can be carried out by this processor.
14. device according to claim 12 more comprises:

Storer stores the group address of a logical address mapping table with these a plurality of sections of this logical address to this data storage cell of the N position of these data of videoing.
15. device according to claim 12 comprises that the N bit line segment through reading in this data field position of being distinguished by this index field reads the logic of the N position of these data in this data structure.
16. device according to claim 12; Wherein this index field comprises a localizer field and stores the M position in regular turn; And this data field position comprises in regular turn M the N bit line segment of arranging, and wherein last of M position has been programmed one of the nearest use of this M N bit line segment that corresponds in this data field position person in this localizer field.
17. device according to claim 12; Wherein this index field comprises a localizer field and stores the M position in regular turn; And this data field position comprises M the N bit line segment of arranging in regular turn; Wherein store that a primary data storage cell is programmed and remaining data storage cell when in this localizer field, still keeping wiping when this; This localizer field point to this N bit line segment sequence of addresses the first, when this first of this storage and deputy one or more data storage cell is programmed and remaining data storage cell when in this localizer field, still keeping wiping, the sequence of addresses of this this N bit line segment of localizer field sensing the two; And when all these M positions in this localizer field all were programmed, this localizer field was pointed to last person of the sequence of addresses of this N bit line segment.
18. device according to claim 12, wherein this data field position comprises M N bit line segment, comprising:

Through wiping this index field and a data field position, come the logic of another data structure of these a plurality of sections of initialization data storage unit, this another data structure comprises this index field and this data field position, and comprises:

When position, M N bit data territory is about to experience write operation in this data structure; Through the data storage cell in this index field of this corresponding other data structure of a specific N bit line segment in programming and this data field position of other data structure; The N that writes these data with this same logical address is arranged in this other data structure, and in this data field position of this other data structure of programming this specific N bit line segment with the logic of the N position that stores these data.
19. device according to claim 12; Wherein this data structure comprises a state position; And this initialization comprises wipes this state position, and wherein this state position comprises K-1 position at least, and present one of state is carried out in K of indication when this data structure of initialization.
20. device according to claim 12; Wherein this data structure comprises a state position; And this initialization comprises wipes this state position; Wherein this state position comprises K-1 position at least; And present one of state is carried out in K of indication when this data structure of initialization; Comprise an original state wherein in this state position all data storage cells all be wiped free of; Wherein this K one first state of carrying out state is for being programmed when a primary data storage cell that stores this state position and remaining data storage cell of this state position when being wiped free of, and this K one second state that carries out state be for being programmed when this first and one deputy one or more data storage cell that stores this state position and remaining data storage cell of this state position when being wiped free of, and this K final state that carries out state is that all these K-1 of this state position are when all being programmed.
21. device according to claim 20; Wherein this original state is initialised and does not have the logical address reflection to this data structure; This second state is videoed for this data structure is selected; When one third state was accomplished for write the N bit data from source data structure or other source, a four condition was wiped this source data structure for beginning (if the words that have), and this final state is for wiping this source data structure when any completion and logical address are videoed to data structure.
22. device according to claim 12; Comprise the logic of distributing first and second block; Each block comprises L section; In L logical address of this storage array, and wherein comprise one of this first and second block of wiping this L section that comprises this particular section person in this data structure of particular section initialization.
23. device according to claim 12; Comprise the logic of distributing first and second block, each block comprises L section, in L logical address of this storage array; And wherein this data field position in this data structure of this section comprises M N position section, comprising:

Through wiping this second block, the logic of the data structure in this second block of initialization, and comprise:

When position, M N bit data territory is about to experience write operation in this data structure in this first block, stored data in this first block are moved to the logic of the data structure in this second block.
24. a machine-readable data storage device comprises:

One machine-readable data storing media, storage can be by the instruction of processor execution, and this processor has the function of access one storage array, and this storage array comprises a plurality of sections of the data storage cell with sector address, and this instruction comprises:

The storage data structure is in the logic in a plurality of sections that store this data storage cell, and this data structure is arranged the N position of storage data, comprises an index field and a data field position in the data structure of one of these a plurality of sections;

Come the logic of this data structure of initialization through wiping this index field and this data field position;

Through store in this index field of programming with this data field position in one a corresponding data storage cell of a specific N position section; Write the N position of these data with a logical address; And a specific N position section is to store the N position of these data in this data field position of this data structure of programming; And have in this index field through this data structure of programming with this data field position in the corresponding another one of another different N bit line segment; The N that writes the data with this same logical address once more is arranged in this data structure, and this different N bit line segment of programming.