CN102735920A

CN102735920A - Multi-phase power parameter synchronous acquisition circuit

Info

Publication number: CN102735920A
Application number: CN2011100897210A
Authority: CN
Inventors: 吕治安; 曹传家
Original assignee: XIANGFAN JINDUN ELECTRICAL CO Ltd
Current assignee: XIANGFAN JINDUN ELECTRICAL CO Ltd
Priority date: 2011-04-11
Filing date: 2011-04-11
Publication date: 2012-10-17

Abstract

Disclosed is a multi-phase power parameter synchronous acquisition circuit used for synchronously acquiring multi-phase power parameters of an intelligent digital instrument and an intelligent measurement and control device. The circuit comprises an AD converter, a programmable device and a microcontroller MCU, wherein the AD converter is connected to the programmable device which is connected to the microcontroller MCU; the AD converter is composed of a serial AD converter I, a serial AD converter II, a serial AD converter III, a serial AD converter IV, a serial AD converter V, a serial AD converter VI and a serial AD converter VII; and the programmable device adopts an FPGA/CPLD. Parameters in multiple paths can be acquired simultaneously through the multiple serial AD converters and the programmable device FPGA/CPLD, and the acquisition of signals in one path and conversion of the acquired data can be carried out by one AD converter so as to realize interface with the microcontroller MCU. The multi-phase power parameter synchronous acquisition circuit of the invention has the advantages of accurate detection, simple structure, convenient use, reliable operation and optimized cost.

Description

Heterogeneous electrical energy parameter synchronous acquisition circuit

Technical field

The present invention relates to the data acquisition application circuit of a kind of intelligent digital instrument and intelligent measuring and control device, specifically a kind of heterogeneous electrical energy parameter synchronous acquisition circuit.

Background technology

In the three-phase electric energy parameter detecting instrument, need utilize AD converter to realize a parameter acquisition such as electric current, voltage, power, power factor (PF), frequency, neutral line current, electric energy usually.Generally speaking, can adopt the monolithic AD converter in turn measured parameter to be gathered in the detection system, signals collecting also just has time difference like this.In fact, measured signal numerical value is along with the time is changing, although AD converter speed is very fast, the acquisition time difference of different parameters is very little, also has difference after all, and this sampling time difference also just is directly connected to the accuracy of measured parameter.In the prior art; Because mostly AD converter is the form of parallel interface; Monolithic parallel interface AD converter can not accomplish accurately to gather in real time measured parameter, and multi-disc parallel interface AD converter has complex structure again, reliability is low, expense strengthens and the shortcoming of cost rising.

Summary of the invention

For overcoming the deficiency of prior art, goal of the invention of the present invention is to provide a kind of heterogeneous electrical energy parameter synchronous acquisition circuit, and it can accomplish accurately to gather in real time measured parameter effectively, greatly improves the reliability of parameter detecting.

For realizing above-mentioned purpose, the present invention is made up of AD converter, programming device and microcontroller MCU, and AD converter connects programming device, and programming device connects microcontroller MCU; AD converter is made up of serial A/D converter one, serial A/D converter two, serial A/D converter three, serial A/D converter four, serial A/D converter five, serial A/D converter six and serial A/D converter seven devices; Programming device adopts FPGA/CPLD.

Be respectively arranged with acquired signal input end, acquired signal output terminal, clock signal input terminal and chip selection signal input end on serial A/D converter one, serial A/D converter two, serial A/D converter three, serial A/D converter four, serial A/D converter five, serial A/D converter six and the serial A/D converter seven.

Programmable device FPGA/CPLD is provided with input end one, input end two, input end three, input end four, input end five, input end six, input end seven, clock signal control end and chip selection signal control end.

The acquired signal output terminal of serial A/D converter one, serial A/D converter two, serial A/D converter three, serial A/D converter four, serial A/D converter five, serial A/D converter six and serial A/D converter seven is connected input end one, input end two, input end three, input end four, input end five, input end six and the input end seven of programmable device FPGA/CPLD respectively.

The clock signal control end of programmable device FPGA/CPLD (11) connects the clock signal input terminal of serial A/D converter one, serial A/D converter two, serial A/D converter three, serial A/D converter four, serial A/D converter five, serial A/D converter six and serial A/D converter seven respectively; The chip selection signal control end of programmable device FPGA/CPLD connects the chip selection signal input end of serial A/D converter one, serial A/D converter two, serial A/D converter three, serial A/D converter four, serial A/D converter five, serial A/D converter six and serial A/D converter seven respectively.

The present invention compared with prior art owing to adopt the multi-disc serial A/D converter to connect the version of programmable device FPGA/CPLD, thereby gathers when having realized heterogeneous electrical energy parameter, has improved the accuracy of image data greatly; Clock signal control end owing to programmable device FPGA/CPLD is connected the clock signal input terminal and the chip selection signal input end of multi-disc serial A/D converter respectively with the chip selection signal control end simultaneously, thereby has realized the clock signal of multi-disc serial A/D converter and the control of chip selection signal; In addition because programmable device FPGA/CPLD connects microcontroller MCU, thereby realized intelligent monitoring, the greatly perfect science that detects data.Characteristics simple in structure, easy to use, reliable, cost optimization that the present invention also has.

Description of drawings

Accompanying drawing is a circuit structure block diagram of the present invention.

Embodiment

The present invention is described further from three aspects below in conjunction with accompanying drawing.

The first, ingredient of the present invention:

Circuit devcie of the present invention: comprise AD converter 1, programming device 2, microcontroller MCU3.

The building block of AD converter 1: comprise serial A/D converter 1, serial A/D converter 25, serial A/D converter 36; Serial A/D converter 47, serial A/D converter 58, serial A/D converter 69; Serial A/D converter 7 10, acquired signal input end 12, acquired signal output terminal 13; Clock signal input terminal 14, chip selection signal input end 15.

Programming device 2: comprise input end 1, input end 2 17, input end 3 18, input end 4 19, input end 5 20, input end 6 21, input end 7 22, clock signal control end 23, chip selection signal control end 24.

Microcontroller MCU3: comprise parallel data bus line 25, MCU chip selection signal 26, MCU read signal 27, MCU write signal 28.

The second, three of FPGA/CPLD programming device 2 major functions: the one, the interface of system and microcontroller MCU3, microcontroller MCU3 can pass through interface reading and writing data.The 2nd, for AD converter 1 provides control signal, control AD converter 1 is accomplished data acquisition.The 3rd, each serial data that the logical organization through inside will collect converts parallel data to.

Three, signal acquisition process and circuit theory:

Three-phase voltage, electric current, neutral line current signal measured in the circuit are connected respectively to signal input part 12, and get into AD converter; When microcontroller MCU3 through parallel data bus line 25, MCU chip selection signal 26, MCU write signal 28 after programming device 2 is given an order; Programming device 2 produces the chip selection signal input end 15 that a useful signal is sent to AD converter on its chip selection signal control end 24; Carry out the conversion preparation to start AD converter; Programming device 2 produces 12 pulse signals continuously on its clock signal controlling end 23 then; And be sent to the clock signal input terminal 14 of AD converter; Each AD converter is changed the simulating signal of its input end respectively under the control of clock signal; And according to this each AD transformation result is sent to input end 1, input end 2 17, input end 3 18, input end 4 19, input end 5 20, input end 6 21, the input end 7 22 of programming device 2 respectively through its acquired signal output terminal 13, get into the inside of programming device 2; Programming device 2 converts the serial data that these get into according to this into parallel data, temporarily preserves in inside; Microcontroller MCU3 sends MCU chip selection signal 26 and MCU read signal 27, and the data that programming device 2 is preserved inside send microcontroller MCU3 to through parallel data bus line 25.So far, seven road electrical energy parameters are accomplished simultaneously the data acquisition of one whole.

Claims

1. heterogeneous electrical energy parameter synchronous acquisition circuit, it is made up of AD converter (1), programming device (2) and microcontroller MCU (3), it is characterized in that: AD converter (1) connects programming device (2), and programming device (2) connects microcontroller MCU (3); AD converter (1) is made up of serial A/D converter one (4), serial A/D converter two (5), serial A/D converter three (6), serial A/D converter four (7), serial A/D converter five (8), serial A/D converter six (9) and serial A/D converter seven (10) devices; Programming device (2) adopts FPGA/CPLD.

2. heterogeneous electrical energy parameter synchronous acquisition circuit according to claim 1 is characterized in that: be respectively arranged with acquired signal input end (12), acquired signal output terminal (13), clock signal input terminal (14) and chip selection signal input end (15) on serial A/D converter one (4), serial A/D converter two (5), serial A/D converter three (6), serial A/D converter four (7), serial A/D converter five (8), serial A/D converter six (9) and the serial A/D converter seven (10).

3. heterogeneous electrical energy parameter synchronous acquisition circuit according to claim 1 is characterized in that: programming device (2) is provided with input end one (16), input end two (17), input end three (18), input end four (19), input end five (20), input end six (21), input end seven (22), clock signal control end (23) and chip selection signal control end (24).

4. heterogeneous electrical energy parameter synchronous acquisition circuit according to claim 1 is characterized in that: the acquired signal output terminal (13) of serial A/D converter one (4), serial A/D converter two (5), serial A/D converter three (6), serial A/D converter four (7), serial A/D converter five (8), serial A/D converter six (9) and serial A/D converter seven (10) is connected the input end one (16) of programmable device FPGA/CPLD (11), input end two (17), input end three (18), input end four (19), input end five (20), input end six (21) and input end seven (22) respectively.

5. heterogeneous electrical energy parameter synchronous acquisition circuit according to claim 1 is characterized in that: the clock signal control end (23) of programming device (2) connects the clock signal input terminal (14) of serial A/D converter one (4), serial A/D converter two (5), serial A/D converter three (6), serial A/D converter four (7), serial A/D converter five (8), serial A/D converter six (9) and serial A/D converter seven (10) respectively; The chip selection signal control end (24) of programming device (2) connects the chip selection signal input end (15) of serial A/D converter one (4), serial A/D converter two (5), serial A/D converter three (6), serial A/D converter four (7), serial A/D converter five (8), serial A/D converter six (9) and serial A/D converter seven (10) respectively.