DE102005000809B4 - Integrated semiconductor memory with non-volatile storage of data - Google Patents

Abstract

Integrated semiconductor memory with non-volatile storage of data, - with a first memory cell array (SF1) with volatile memory cells (SZ) and non-volatile memory cells (WZ), - with a second memory cell array (SF2) with volatile memory cells (SZ), - with a control circuit (20 ) for controlling read and write access to one of the volatile and non-volatile memory cells (SZ, WZ) of the first memory cell array (SF1) and to one of the volatile memory cells (SZ) of the second memory cell array (SF2), - in which the control circuit (20 ) is designed in such a way that during an access to one of the volatile memory cells (SZ) of the second memory cell array (SF2) it allows write access to the at least one of the non-volatile memory cells of the first memory cell array for storing at least one data item, the at least one data item during operation of the integrated semiconductor memory identified operating parameters, in mi At least one of the non-volatile memory cells (WZ) of the first memory cell array is carried out.

Description

The present invention relates to an integrated semiconductor memory in which data can be stored nonvolatilely.

In semiconductor integrated memories, such as dynamic random access memory (DRAM) semiconductor memories, the failure rate in the first few hours of operation is relatively high. In order to be able to sort out defective components after production, the integrated semiconductor memories are stressed for a few hours of operation after completion of the manufacturing process. Within this short operating time, a large part of faulty components can be sorted out. It also shows that, statistically, the failure rate only increases again after a long period of operation, such as several years. In order to be able to analyze such long-term failures, it would be desirable if, during the operation of a semiconductor memory, operating parameters, such as the operating time or the number of specific events, such as memory accesses to a specific memory area, could be recorded permanently and permanently. The publication DE 100 35 598 A1 shows such a data store with access counter.

In a semiconductor memory with volatile memory cells, such as dynamic random access memory (DRAM) memory cells, the memory contents must be refreshed at the latest after expiration of a data retention time. In contrast to nonvolatile semiconductor memories, such as flash, ferroelectric random access memory (FERAM) or MRAM (magnetic random access memory) semiconductor memories, there is the problem with DRAM semiconductor memories that long-term production and test-relevant information such as test results, sort criteria, production-relevant Data, but also beyond operating parameters that occur during operation of the integrated semiconductor memory, can not be stored irreversibly and permanently.

In order to permanently store data in a DRAM semiconductor memory, electrical fuses (e-fuses) or laser fuses are therefore used. Laser fuses can only be programmed during the manufacture of the integrated semiconductor memory. Via e-fuses, data can also be stored permanently in the packaged state of a DRAM memory by programming the e-fuses by applying a programming voltage. A small field of e-fuses is generally still easy to evaluate. However, if larger amounts of data are to be stored permanently, a fuse array structure must be provided. Within the fuse array structure, the E-fuses, like the volatile DRAM cells in the memory cell array, are generally arranged in matrix form along column and row lines. To read the programming state of the individual e-fuses, a row / column decoder architecture is required. Due to the large space requirement for such circuits, large e-fuse memory areas are generally not integrated in semiconductor memory with volatile memory cells.

Furthermore, e-fuses have the disadvantage that they can only be programmed once. Thus, changes in data, such as occur in the operating parameters during the operating time, can not be stored changed in the same e-fuses.

The object of the present invention is to specify an integrated semiconductor memory in which it is possible to reliably store production and operating data over a relatively long period of time, with as few additional circuit components as possible being required for storing the production and operating data. A further object of the present invention is to specify a method with which, in the case of an integrated semiconductor memory, manufacturing and operating data can be stored reliably over a relatively long period of time, with as few additional circuit components as possible for storing the production and operating data.

The object concerning the integrated semiconductor memory is achieved by an integrated semiconductor memory having a first memory cell array with volatile memory cells and non-volatile memory cells, with a second memory cell array with volatile memory cells and with a control circuit for controlling access to one of the memory cells of the first and second memory cell array. According to the invention, the control circuit is designed in such a way that when accessing one of the volatile memory cells of the second memory cell array, it writes to at least one of the nonvolatile memory cells of the first memory cell array to store one of the datum determined in the current operation of the integrated semiconductor memory in the at least one of the nonvolatile ones Memory cells of the first memory cell array.

By using a memory cell array with both volatile and nonvolatile memory cells, the same drive circuits as row decoders, column decoders, and sense amplifiers can be used, which also serve to write information to the volatile memory cells and to read information from the volatile memory cells. As a result, the space requirement is significantly reduced, as additional storage space is to be provided only for the non-volatile memory cells. The date determined in the current operation of the integrated semiconductor memory may be, for example, an operating parameter which has occurred during a test operation of the integrated semiconductor memory. This can be, for example, a lot number or the name of a test program. However, it may also be an operating parameter that indicates an operating state of the semiconductor memory. This includes, for example, the number of accesses to a specific memory area or the operating temperature that has occurred during operation of the integrated semiconductor memory.

According to one development of the integrated semiconductor memory, the volatile memory cells of the first and second memory cell arrays are each designed such that, after a memory state has been stored in one of the volatile memory cells to preserve the stored memory state, the memory state must be refreshed at the latest after the expiration of a data retention period. The control circuit is designed such that, in order to maintain the stored memory state in one of the memory cells of the second memory cell array, it refreshes the memory state stored in one of the memory cells and thereby stores the datum determined in the current operation of the integrated semiconductor memory in one of the nonvolatile memory cells of the first memory cell array ,

In another embodiment of the integrated semiconductor memory, sense amplifiers are provided in the first and second memory cell arrays, each being connected to a bit line pair having a first and a second bit line. The volatile memory cells and the nonvolatile memory cells of the first memory cell array are each connected to a bit line pair. The volatile memory cells and the nonvolatile memory cells are each designed such that, when read out, they generate a potential difference between the first and the second bit line of the bit line pair (BLP) to which they are respectively connected. The sense amplifiers are each designed in such a way that when reading one of the volatile memory cells and one of the nonvolatile memory cells, they respectively evaluate the potential difference between the first and second bit lines of the bit line pair to which they are respectively connected and have a datum depending on the evaluated potential difference generate a first or second level.

According to one development of the integrated semiconductor memory, the nonvolatile memory cells can be selected for read and write access via addresses. The control circuit is designed such that it determines an address position of the last-described nonvolatile memory cell upon initial activation of the integrated semiconductor memory and stores the data determined in the current operation of the integrated semiconductor memory at the next higher address position following the address position last described.

In one embodiment of the integrated semiconductor memory, the nonvolatile memory cells are each designed as once irreversibly programmable components. The nonvolatile memory cells can also be designed in each case as an electrically programmable fuse or antifuse. According to another embodiment of the integrated semiconductor memory, the nonvolatile memory cells comprise at least one controllable resistor. The volatile memory cells are preferably designed in each case as random access memory cells.

A method for recording manufacturing and operating data of an integrated semiconductor memory envisages the use of an integrated semiconductor memory having a first memory cell array with nonvolatile memory cells and volatile memory cells and a second memory cell array with volatile memory cells, wherein the nonvolatile memory cells comprise first nonvolatile memory cells and second nonvolatile memory cells , wherein in the first non-volatile memory cells information for the configuration of the second non-volatile memory cells is stored. After starting up the integrated semiconductor memory, the memory states of the first nonvolatile memory cells are evaluated to obtain information for configuring the second nonvolatile memory cells. Subsequently, an address position of a last-described second nonvolatile memory cell in the first memory cell array is determined. Thereafter, a next higher address position following the address position of the second non-volatile memory cell described last is determined. The data determined in the current operation of the integrated semiconductor memory is stored in a second nonvolatile memory cell of the first memory cell array addressable via the selected next higher address position in a configuration in dependence on the evaluated memory state of the first nonvolatile memory cells, if one of the volatile memory cells of the second memory cell array is refreshed.

According to a development of the method for recording operating data of an integrated semiconductor memory, the stored data determined in the current operation of the integrated semiconductor memory is set by setting a bit in a register of the integrated semiconductor memory one of the second non-volatile memory cells read out.

Another embodiment of the method for operating an integrated semiconductor memory provides for operating the integrated semiconductor memory in a test operating state. In the test mode, each of the first and second nonvolatile memory cells is read out by applying a control signal to the integrated semiconductor memory.

Further embodiments of the integrated semiconductor memory for recording operating data and the method for recording operating data can be found in the dependent claims.

The invention will be explained in more detail below with reference to figures showing exemplary embodiments of the present invention. Show it:

1 an integrated semiconductor memory for storing operating data according to the invention,

2 a semiconductor memory chip with memory banks for storing operating data according to the invention,

3 a memory bank of an integrated semiconductor memory for storing operating data according to the invention,

4 a section of a memory cell array of a memory bank with volatile and nonvolatile memory cells according to the invention,

5A an address organization of a memory bank according to the invention,

5B an address organization of a memory area with nonvolatile memory cells according to the invention,

5C first nonvolatile memory cells according to the invention for storing configuration data,

6 a binary address search in a memory cell array with nonvolatile memory cells for finding a start address for storing operating data according to the invention,

7 a flowchart for storing operating data in nonvolatile memory cells according to the invention.

1 shows an integrated semiconductor memory 100 with a memory cell array 10 , Within the memory cell array 10 volatile and non-volatile memory cells are arranged in a first memory cell array SF1 and volatile memory cells in a second memory cell array SF2. As an example of a volatile memory cell, a DRAM memory cell SZ is shown in the second memory cell array SF2, which is arranged between a word line WL and a bit line BL. The DRAM memory cell includes a selection transistor AT and a storage capacitor SC. In the case of a read or write access, the memory cell is activated by the selection transistor AT being conductively controlled by a corresponding signal on the word line WL, so that the storage capacitor SC is connected to the bit line BL in a low-resistance manner.

For controlling read, write and precharge processes within the memory cell array 10 is a control circuit 20 intended. For controlling read and write accesses, control signals are applied to a control terminal S20. For selecting one of the memory cells of the first or second memory cell array, an address signal ADS is applied to an address terminal A30. The applied address has an x and a y address part. The address part X becomes a row decoder 70 and the address part Y becomes a column decoder 80 fed. On the basis of the x and y address of the address signal ADS, a memory cell SZ can be selected for a read or write access. For writing information, a data D is applied to a data terminal DQ. When reading a date D is generated at the data terminal DQ.

2 shows a semiconductor chip HC comprising memory banks B1, B2, B3 and B4. Inside the memory banks are, as in 1 shown, volatile and non-volatile memory cells in a first memory cell array SF1 and only volatile memory cells, such as DRAN memory cells, arranged in a second memory cell array SF2. In the 1 shown remaining circuit components, such as the control circuit 20 or the address register 30 are arranged between the memory banks, in the so-called spin region SP, of the semiconductor chip.

3 shows an enlarged view of a section of a memory bank. At the edge of the memory bank is the first memory cell array SF1, which contains the volatile and nonvolatile memory cells. Subsequently, second memory cell arrays SF2a, SF2b, SF2c and SF2d are arranged. The memory cell arrays are each separated by sense amplifier strips SAS in which sense amplifiers for amplifying the memory contents of a selected memory cell or for amplifying the voltage applied to the data terminal DQ Date to be registered in a selected memory cell.

4 shows a section A of the memory bank B from 3 , The bit lines BL are formed within the first memory cell array SF1 and the second memory cell array SF2a as Bitleitungswist. At crossing points of word lines WL and bit lines BL, true memory cells SZT or complement memory cells SZC are arranged. The bit lines are each connected in pairs to a sense amplifier SA. A bit line pair includes a true bit line BLT and a complement bit line BLC. Within the first memory cell array SF1, nonvolatile memory cells WZ are arranged between the true bit line BLT and the complement bit line BLC. In the second memory cell array SF2a only volatile memory cells are present. These are also arranged along word line WL and bit lines BLC and BLT. A true bit line BLT and a complement bit line BLC are also arranged here as a bit line pair and in each case connected to a sense amplifier SA. Along the true bit line BLT are true memory cells SZT and along the complement bit line BLC are complement memory cells SZC arranged.

For writing or reading information from the volatile memory cells or the nonvolatile memory cells, the sense amplifiers are each connected to the external data terminal DQ via a data bus LDQ. The sense amplifiers connected to the bit lines of the first memory cell array SF1 selectively store information in the volatile memory cells SZ or the nonvolatile memory cells WZ. The nonvolatile memory cells WZ are also assigned row and column addresses as well as the volatile memory cells. Advantageously, the nonvolatile memory cells as well as the volatile memory cells can be passed through the row and column decoders 70 and 80 choose. The nonvolatile memory cells include, for example, a programmable resistor. Depending on the programmed resistance value, a potential shift occurs on the bit lines of a bit line pair which is evaluated by the connected sense amplifier. The non-volatile memory cells may also be designed as MRAM, FeRAM or SRAM memory cells. For selecting one of the volatile and non-volatile memory cells and for reading and writing information from or into the volatile and non-volatile memory cells, the same drive circuits can be used. Thus, for the non-volatile memory cells no separate memory cell array needs to be provided with its own control logic.

5A shows a logical address space of a memory bank with x and y addresses X0, ..., X31 and Y0, ..., Y255. The low-order x address range includes the addresses X0,..., X15. The higher-order x address range includes the addresses X16,..., X31. Via the addresses can be selected word lines which are connected to the volatile memory cells in the first or second memory cell array. Nonvolatile memory cells within the first memory cell array can be selected via the addresses X _w 0,..., X _w 3.

The division of the address space into address areas associated with volatile memory cells and into address areas associated with nonvolatile memory cells may be via area definition or bit injection. In the area definition, nonvolatile memory cells with address values above a certain value can be addressed. Address values below this value are addressed by volatile memory cells. In the case of bit injection, an address bit at a specific position of a bit address is set to, for example, the logical value "1" in order to access the nonvolatile memory cells. The low order address bits then select a nonvolatile memory cell in the first memory cell array.

5B shows the address space of the nonvolatile memory cells. First non-volatile memory cells WZa are located in an address area KB, which is addressable via the addresses X _w 0 and the addresses Y0, ..., Y15. In the first nonvolatile memory cells, configuration data for configuring second nonvolatile memory cells WZb, in which the actual operating data are stored, can be stored. The second non-volatile memory cells WZb are located at the address positions X _w 0 and Y16, ..., Y255; X _w 1 and Y0, ..., Y255; X _w 2 and Y0, ..., Y255; X _w 2 and Y0, ..., Y255; X _w 3 and Y0, ..., Y255. In the second non-volatile memory cells WZb operating data of the integrated semiconductor memory are preferably stored.

5C shows a possible assignment of the first non-volatile memory cells WZa with configuration information. Shown are the first non-volatile memory cells WZa0, ..., WZa15 that can be selected via the addresses x _w 0, Y0,..., Y15. The memory cell WZa0 of the first nonvolatile memory cells contains information as to whether the operating data in the second nonvolatile memory cells are stored in a prefix mode. When storing an operating parameter in the prefix mode, several of the second nonvolatile memory cells are described when storing an operating parameter. Some of the second nonvolatile memory cells that store a given operating parameter are provided are used to store an identifier of the operating parameter. A storage of operating data in the prefix mode is particularly useful if within the memory area of the second non-volatile memory cells of 5B various operating parameters are stored. Another advantageous application of the prefix mode is when the occurrence of an error is logged within the non-volatile memory area. In addition to the occurrence of the actual error event can be, for example, the error address of a memory cell, the prevailing temperature at the occurrence of the error and store reference currents or reference voltages.

The memory cell WZa1 of the first nonvolatile memory cells of the configuration area contains information as to whether the memory area of the second nonvolatile memory cells should be used to store an operating parameter. A possible operating parameter is, for example, the operating life of the integrated semiconductor memory. For logging the operating time is a counter circuit on the integrated semiconductor memory 60 intended. The counter circuit 60 contains a register whose current counter reading is increased every six minutes, for example. The counter reading is at regular intervals from the control circuit 20 stored in the nonvolatile second memory cells of the first memory cell array SF1.

The memory cell WZa2 of the first nonvolatile memory cells within the configuration area contains information as to whether the operating parameter to be stored is to take place during background storage during operation of the integrated semiconductor memory, for example during a refresh operation of memory cells located in the second memory cell array SF2. There, as in 4 As shown, nonvolatile memory cells are arranged only in the first memory cell array SF1, the storage of operating parameters in the nonvolatile memory cells can take place in parallel with the refresh operation of the volatile memory cells of the second memory cell array SF2a.

When the memory cell WZa3 of the first nonvolatile memory cells is programmed, the second nonvolatile memory cells W2b of the first memory cell array can be externally written, or an external operating parameter can be selected for storage in the nonvolatile memory cells. Describing the non-volatile memory cells takes place in a so-called Appending mode. This means that non-volatile second memory cells already described can not be overwritten. Instead, the non-volatile second memory cell described last is determined and the next higher non-volatile second memory cell selected in the address space for the memory operation.

The memory cell WZa4 of the first nonvolatile memory cells within the configuration area indicates whether only read access to the nonvolatile second memory cells is permitted. If the read access is permitted, operating data can be read from the nonvolatile second memory cells WZb in an application. As an operating parameter can be, for example, from a temperature sensor 50 in 1 determine an operating temperature in a register 40 is cached. The operating temperature is out of the register 40 in a refresh process of volatile memory cells of the second memory cell array read and stored in the second nonvolatile memory cells of the first memory cell array.

If read access to the non-volatile memory cells is permitted, the operating temperature can be evaluated by a memory controller. The memory controller can then reduce the operating frequency of the semiconductor memory, for example, at a high operating temperature.

The memory state in the first nonvolatile memory cells WZa5 and WZa6 within the configuration area indicates whether the storage of an operating parameter within the nonvolatile second memory cells is to take place bit-by-byte or word-wise. In a byte or wordwise storage of an operating parameter, the information is encoded in several bits. By contrast, in the bit-wise storage, the information of the operating parameter to be stored is encoded in a single bit. If, for example, the operating time is to be stored bit-by-bit, one of the second nonvolatile memory cells WZb will be written at certain time intervals, for example every six minutes, as soon as a refresh operation for memory cells takes place within the second memory cell array.

At the beginning of the operating period, for example, the non-volatile second memory cell associated with the address X _w 0, Y16 is described as having a "1" level. Every six minutes later, a memory cell following the last-described non-volatile memory cell in the address space, that is, the memory cell associated with the address X _w 0, Y17 at the second memory, is written at the logical "1" level. If this type of storage is to be logged over a period of ten years, 876,000 non-volatile memory cells are required. Compared to typical 512 Mb DRAM Memory cells only need 0.163% of additional storage space.

The memory cells WZa6, ..., WZa14 of the first nonvolatile memory cells contain information about the number of logical memory areas into which the second nonvolatile memory cells are divided. Furthermore, the first non-volatile memory cells WZa6,..., WZa14 contain information about the operating parameters to be stored within a memory area. This makes it possible, for example, the logical address space of nonvolatile memory cells of 5B into two different areas, wherein in a first nonvolatile memory area the number of activations of sense amplifiers in a particular reader amplifier strip is logged over an operating period and in a second nonvolatile memory area the operating temperature is recorded over a longer period of time.

The memory cell WZa15 of the first nonvolatile memory cells contains information as to whether the memory capacity of the second nonvolatile memory cells has already been completely exhausted, since all second nonvolatile memory cells are already described with information data. For example, when the nonvolatile memory cell WZa15 is programmed to a logical "1" level, the available memory space is exhausted and logging of an operating parameter in the second nonvolatile memory cells is interrupted.

The memory state of the first non-volatile memory cells is determined either already during production or only during later operation of the integrated semiconductor memory. Thus, for example, the subsequent use of the second non-volatile memory cells for storing an operating parameter by preprogramming the first non-volatile memory cells in the configuration area can already be determined by the manufacturer. A specific area of the second nonvolatile memory cells WZb can be provided, for example, for logging the operating time of the integrated semiconductor memory.

If a memory area with non-volatile memory cells is first configured in an application, then, for example, the logging of the operating temperature can be started by a signaling bit in a register 21 , such as the mode register or the extended mode register. When the control circuit 20 detects the set bit in one of the two registers, for example, it selects a non-volatile memory area for recording the operating temperature and sets by programming the first non-volatile memory cells, the configuration of the second non-volatile memory cells independently. Preferably, access to the nonvolatile memory cells via the mode / extended mode register only allows access in appending mode, ie without overwriting already programmed nonvolatile memory cells. As a further restriction, it may be provided that the user of the integrated semiconductor memory can only read access to certain shared non-volatile memory areas in an application.

In addition to the possibility of accessing the nonvolatile memory cells by setting a bit in a mode register or an extended mode register, it is also possible to apply a characteristic test mode signal TM or one or more characteristic key bit sequences to the control terminal S20 of the control circuit 20 to access the nonvolatile memory cells. If, for example, the integrated semiconductor memory has failed in one application and is sent back to the manufacturer as a customer return, the manufacturer can read out the entire nonvolatile memory area via the characteristic key bit sequences. This makes it possible to draw conclusions about possible causes of failure of a memory module. It is also possible to store various manufacturing and test data such as trim modes, test program names, lot assignments and assignments to production machines in the nonvolatile memory cells via the test mode signal even before delivery of the component. Thus, a failed module can be assigned to a production period and a production line. On the basis of the knowledge of the production parameters, it is also often possible to draw conclusions about the cause of the failure in the case of a failed component.

When a memory area of second nonvolatile memory cells is continuously written continuously from low to high address positions, each time the semiconductor memory is booted within the memory area of the nonvolatile memory cells, the address position from which the storage of operating parameters can be continued during the following operating time is determined. This prevents that already described nonvolatile memory cells are overwritten.

6 shows the address space AB1 of the nonvolatile memory cells. In the example of 6 All nonvolatile memory cells which belong to an address y <143 have already been programmed by already storing operating data there. When the nonvolatile memory area is continuously continuously written from a low to a high address position, after the power-up of the semiconductor integrated memory, the address of the next free nonvolatile memory cell to be written is determined by a binary address search. In the following, the determination of a free memory cell will be described on the basis of its assigned y-address. If the nonvolatile address space has the address positions y = 0 to y = 255, the memory state of a nonvolatile memory cell at the address position y = 255 is examined at the beginning of the binary address search algorithm. In the example of 6 are stored in the nonvolatile memory cells associated with the address y = 255, no operating parameters. Subsequently, the address space is halved and carried out at the address position y = 127 an evaluation of the memory state of the associated non-volatile memory cells. Since the nonvolatile memory cells are described here, the next free nonvolatile memory cell must be in the address space between the addresses y = 127 to y = 255. After halving this address space, the address position y = 191 is examined. Since no operating parameter is stored at the memory cells at this address position, the last described nonvolatile memory cell must lie in the address space y = 127 to y = 191. By continuously halving the address intervals, the address y = 143, at which the last described non-volatile memory cell is located, is finally found. Thus, in the following, the logging of an operating parameter can be continued at the address position y = 144.

7 shows a flowchart for logging an operating parameter. In the example of 7 For example, in the manufacture of the integrated semiconductor memory, a non-volatile memory area has been provided in which the occurrence of an error event during the operating time of the integrated semiconductor memory is recorded. After starting up the semiconductor memory evaluates the control circuit 20 the first nonvolatile memory cells within the configuration area of the nonvolatile memory area. When the nonvolatile memory cell WZa15 has the logic state "0", the memory area is not fully described. In this case, the end address of the non-volatile memory area is determined by a binary address search. The control circuit 20 subsequently activates the event counter, in the example the occurrence of a specific error event. When the error occurs, an event register is programmed accordingly. The event register serves as a buffer. When volatile memory cells within the second memory cell array are refreshed, the current value of the event register can be stored in the nonvolatile memory cells of the first memory cell array. As long as the non-volatile memory cell WZa1 has the logical memory state "1", each time the error event occurs, a non-volatile memory cell in the first memory cell array is programmed when refreshing volatile memory cells in the second memory cell array. By a state change of the non-volatile memory cell WZa1 from the logical "1" state to the logic "0" state, the logging of the error event can be interrupted at any time.

LIST OF REFERENCE NUMBERS

10

Memory cell array

20

control circuit

21

Mode Register

30

address register

40

memory register

50

temperature sensor

60

Hour meter

70

row decoder

80

column decoder

AT

selection transistor

B

memory bank

BL

bit

BLP

bit line

D

date

DQ

data port

SA

sense amplifier

SAS

Wordline strips

SC

storage capacitor

SF

Memory cell array

SP

Spine-area

SZ

volatile memory cell

WL

wordline

WZ

non-volatile memory cell

X, Y

addresses

Claims (25)

Integrated semiconductor memory with nonvolatile storage of data, - with a first memory cell array (SF1) with volatile memory cells (SZ) and nonvolatile memory cells (WZ), - with a second memory cell array (SF2) with volatile memory cells (SZ), - with a control circuit ( 20 ) for controlling a read and a write access to one of the volatile and nonvolatile memory cells (SZ, WZ) of the first memory cell array (SF1) and to one of the volatile memory cells (SZ) of the second memory cell array (SF2), - in which the control circuit ( 20 ) is designed such that it, during an access to one of the volatile memory cells (SZ) of the second memory cell array (SF2), a write access to the at least one of the nonvolatile memory cells of the first memory cell array for storage at least one datum, which characterizes at least one operating parameter determined during operation of the integrated semiconductor memory, in at least one of the nonvolatile memory cells (WZ) of the first memory cell array. Integrated semiconductor memory according to claim 1 - wherein the volatile memory cells (SZ) of the first and second memory cell array are each formed such that after storing a memory state in one of the volatile memory cells to maintain the stored memory state of the memory state must be refreshed at the latest after expiration of a data retention period In which the control circuit ( 20 ) is designed such that, in order to maintain the stored memory state in one of the volatile memory cells of the second memory cell array (SF2), it refreshes the memory state stored in one of the memory cells and at least one datum characterizing the operating parameter in the at least one of the nonvolatile memory cells of the first memory cell Memory cell array stores. Integrated semiconductor memory according to one of Claims 1 or 2, in which a drive circuit (SA, SA) for carrying out a read or write access to one of the volatile memory cells (SZ) of the first memory cell array (SF1). 20 . 30 ), in which the nonvolatile memory cells (WZ) are each designed in such a way that, for carrying out a read or write access to one of the nonvolatile memory cells, the drive circuit (SA, 20 . 30 ), which is provided for carrying out the read or write access to one of the volatile memory cells (SZ) of the first memory cell array, is usable. Integrated semiconductor memory according to one of Claims 1 to 3, In which sense amplifiers (SA) are provided in the first and second memory cell arrays, each of which is connected to a bit line pair (BLP) having a first and a second bit line (BLT, BLC), In which the volatile memory cells (SZ) and the nonvolatile memory cells (WZ) of the first memory cell array (SF1) are each connected to a bit line pair, In which the volatile memory cells (SZ) and the nonvolatile memory cells (WZ) are respectively designed such that, when reading out, they generate a potential difference between the first and the second bit line of the bit line pair (BLP) to which they are respectively connected, - Wherein the sense amplifiers (SA) are each designed such that when reading one of the volatile memory cells (SZ) and one of the nonvolatile memory cells (WZ) each have the potential difference between the first and second bit line of the bit line pair, to which they are respectively connected , evaluate and, depending on the evaluated potential difference, generate the at least one datum (D) characterizing the operating parameter with a first or second level. Integrated semiconductor memory according to one of claims 1 to 4, - with first of the nonvolatile memory cells (WZa), - second of the nonvolatile memory cells (WZb), - in which the control circuit ( 20 ) is designed such that it evaluates the memory state of the first of the non-volatile memory cells (WZa), - in which the control circuit ( 20 ) is designed such that, depending on the memory state of the first of the nonvolatile memory cells (WZa), stores the at least one datum characterizing the operating parameter in the at least one of the second of the nonvolatile memory cells (WZb) with an operating parameter identifier, on the basis of which during operation of the integrated semiconductor memory can distinguish operating parameters from other operating parameters determined during operation of the integrated semiconductor memory. Integrated semiconductor memory according to Claim 5, in which the control circuit ( 20 ) is designed such that it interrupts the storage of the at least one datum characterizing the operating parameter in one of the second of the nonvolatile memory cells (WZb) as a function of the memory state of the first of the nonvolatile memory cells (WZa). Integrated semiconductor memory according to one of Claims 5 or 6, in which the control circuit ( 20 ) is designed such that it accesses the second of the non-volatile memory cells (WZb) in read-only fashion as a function of the memory state of the first of the nonvolatile memory cells (WZa). Integrated semiconductor memory according to one of Claims 5 to 7, in which the control circuit ( 20 ) is designed such that, depending on the memory state of the first of the nonvolatile memory cells (WZa), stores the at least one datum characterizing the operating parameter in bitwise, bytewise or wordwise manner into the second of the nonvolatile memory cells (WZb). Integrated semiconductor memory according to one of Claims 5 to 8, in which the control circuit ( 20 ) is adapted to assign the second of the nonvolatile memory cells (WZb) to different memory areas depending on the memory state of the first one of the nonvolatile memory cells (WZa), and in a first one of the second memory cells different memory areas a first date that identifies a determined during operation of the integrated semiconductor memory operating parameters, and in a second of the various memory areas a second date that identifies a determined during operation of the integrated semiconductor memory second operating parameter stores. Integrated semiconductor memory according to one of Claims 1 to 9, - in which the non-volatile memory cells (WZ) can be selected for read and write access via addresses (X, Y), - in which the control circuit ( 20 ) is designed such that it determines an address position of the last-described night volatile memory cell (WZ) upon initial activation of the integrated semiconductor memory and stores the at least one datum characterizing the operating parameter at the next higher address position following the address position last described. Integrated semiconductor memory according to one of Claims 1 to 10, - having a register ( 40 ) for temporarily storing the at least one datum characterizing the operating parameter, - in which the control circuit ( 20 ) is designed in such a way that, when the memory state of one of the volatile memory cells (SZ) of the second memory cell array (SF2) is refreshed, the register ( 40 ) for temporarily storing the at least one datum characterizing the operating parameter and storing the buffered datum characterizing the operating parameter in one of the nonvolatile memory cells (WZ) of the first memory cell array (SF1). Integrated semiconductor memory according to one of Claims 1 to 11, in which the register ( 40 ) for temporarily storing the at least one datum characterizing the operating parameter is formed as a register for storing an operating temperature of the integrated semiconductor memory. Integrated semiconductor memory according to one of Claims 1 to 12, in which the control circuit ( 20 ) is designed such that it changes the storage state of the nonvolatile memory cells (WZ) of the first memory cell array (SF1) as a function of the operating time of the integrated semiconductor memory. Integrated semiconductor memory according to one of claims 1 to 13, wherein the non-volatile memory cells (WZ) are each formed as a single irreversibly programmable components. Integrated semiconductor memory according to one of claims 1 to 14, wherein the non-volatile memory cells are each formed as an electrically programmable fuse or antifuse. Integrated semiconductor memory according to one of Claims 1 to 15, in which the nonvolatile memory cells (WZ) comprise at least one controllable resistor (SR). Integrated semiconductor memory according to one of Claims 1 to 16, in which the volatile memory cells are each designed as random access memory cells (SZ). A method for operating an integrated semiconductor memory, comprising a first memory cell array (SF1) with nonvolatile memory cells (WZ) and volatile memory cells (SZ) and a second memory cell array (SF2) with volatile memory cells (SZ), wherein the nonvolatile memory cells (WZ) first non-volatile Memory cells (WZa) and second non-volatile memory cells (WZb), wherein in the first non-volatile memory cells (WZa) information for the configuration of the second non-volatile memory cells (WZb) is stored, comprising the following steps: Evaluating memory states of the first nonvolatile memory cells (WZa), Subsequently determining an address position of a last-described second nonvolatile memory cell (WZb) in the first memory cell array (SF1), Subsequently selecting a next higher address position following the address position of the second nonvolatile memory cell last described, Subsequently storing at least one datum characterizing an operating parameter determined during operation of the integrated semiconductor memory, in a second nonvolatile memory cell (WZb) of the first memory cell array (SF1) which can be addressed via the selected next higher address position, in a configuration in dependence on the evaluated memory state of the first non-volatile memory cells (WZa) when one of the volatile memory cells (SZ) of the second memory cell array (SF2) is refreshed. A method of operating a semiconductor integrated memory according to claim 18, comprising the step of: setting a bit in the first nonvolatile memory cells (WZa0) for storing the at least one operating parameter indicative date in the second nonvolatile memory cells (WZb) with an operating parameter identifier based on which distinguishes at least one datum characterizing the operating parameter from other data characterizing other operating parameters determined during operation of the integrated semiconductor memory. Method for operating a semiconductor integrated memory according to one of Claims 18 or 19, comprising the following step: Setting a bit in the first nonvolatile memory cells (WZa4) to configure the second nonvolatile memory cells (WZb) for read only access. A method of operating an integrated semiconductor memory according to any one of claims 18 to 20, comprising the following step: Setting a bit in the first nonvolatile memory cells (WZa5) for configuring the second nonvolatile memory cells (WZb) for a bitwise, bytewise or wordwise storage of the at least one datum characterizing the operating parameter. A method of operating a semiconductor integrated memory according to any one of claims 18 to 21, comprising the following step: Setting a bit sequence in the first nonvolatile memory cells (WZa8,..., WZa14) for dividing the second nonvolatile memory cells (WZ) into at least one first memory area for storing a first data characterizing a first operating parameter determined during operation of the integrated semiconductor memory, and in at least one second memory area for storing a second datum, which identifies a second operating parameter determined during operation of the integrated semiconductor memory. Method for operating an integrated semiconductor memory according to one of Claims 18 to 22, comprising the following step: reading out the stored data characterizing the operating parameter from the one of the second nonvolatile memory cells (WZb) by setting a bit in a register ( 21 ) of the integrated semiconductor memory. A method of operating a semiconductor integrated memory according to any one of claims 18 to 23, comprising the following steps: Operating the integrated semiconductor memory in a test mode, - Reading each of the first and second non-volatile memory cells (WZa, WZb) in the test mode by applying a control signal (TM) to the integrated semiconductor memory. Method for operating an integrated semiconductor memory according to one of Claims 18 to 24, comprising the following steps: - Providing an integrated semiconductor memory with a counting unit ( 60 ) for detecting an operating time of the integrated semiconductor memory, - incrementing the counting unit ( 60 ) for detecting the operating time of the integrated semiconductor memory at a defined time interval during the operation of the integrated semiconductor memory, - after the counting unit has been incremented ( 60 ) each storing a first logic state in one of the second nonvolatile memory cells, wherein the one of the second nonvolatile memory cells with respect to one of the second nonvolatile memory cells, which has been described last with the first logical state, is addressable via a next higher address.

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