US20020181275A1 - Data register and access method thereof - Google Patents
Data register and access method thereof Download PDFInfo
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- US20020181275A1 US20020181275A1 US10/134,101 US13410102A US2002181275A1 US 20020181275 A1 US20020181275 A1 US 20020181275A1 US 13410102 A US13410102 A US 13410102A US 2002181275 A1 US2002181275 A1 US 2002181275A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/0081—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
Definitions
- the present invention relates to a non-volatile storage element to be integrated on a semiconductor chip, more particularly to a register that employs MTJ (Magnetic Tunnel Junction) elements used in an MRAM (Magnetic Random Access Memory), as well as a data storing method and a data reading method to be employed for the register.
- MTJ Magnetic Tunnel Junction
- MRAM Magnetic Random Access Memory
- a register block 20 is a circuit block used to store data temporarily.
- the register block 20 as shown in FIG. 4, is composed of a flip-flop circuit formed with a combination of NAND circuits 40 a and 40 b .
- the register block stores “0” or “1” data according to the combination of signals entered to the input lines S and R.
- a latching circuit/register built in a logic chip loses data stored therein when the power supply is turned off. This is because data is stored in such a volatile storage element as a capacitor or a static latch. Consequently, the use of a non-volatile storage elements is very advantageous for many system application programs.
- non-volatile semiconductor memory chips such as flash memories.
- any of the existing semiconductor chip manufacturing processes cannot incorporate such a non-volatile storage element as a flash memory in a logic chip. Consequently, none of the logic chips provided in existing computer systems and used for application programs has such the non-volatile data storing function.
- the register of the present invention includes a register block for storing data; a data writing block provided with a non-volatile storage element enabled to store the data; and a data restoring block for reading data from the data writing block.
- the data storing method of the present invention includes a step of outputting a high level signal from one of first and second logic circuits according to the data output from the register block; the high level signal turning on one of two pairs of switches connected to the first and second logic circuits, respectively, and writing data in the two storage elements with polarity according to which of the first and second pairs of switches is turned on.
- the data reading method of the present invention includes a step of generating, with current mirror circuit, a differential signal according to the resistance values of the first and second storage elements, amplifying the differential signal, and holding the amplified differential signal.
- a logic chip including the present invention is preferably configured so as to include magnetic tunnel junction (MTJ) elements, which are non-volatile storage elements.
- MTJ magnetic tunnel junction
- the logic chip can be designed and manufactured easily and the manufacturing cost can be reduced.
- data can be stored in them even after the power is turned off.
- such non-volatile storage elements having MTJ elements are constructed so as to consume no power when power to the logic chip is turned off.
- FIG. 1 is a block diagram of a register of the present invention
- FIG. 2 is a structure of an MTJ element
- FIG. 3 is a circuit diagram including a pair of cross-coupled CMOS inverters used to hold data
- FIG. 4 is a circuit diagram used for a general register block.
- FIG. 1 is a block diagram of the register of the present invention.
- the register 10 is provided with a conventional register block 20 , as well as a data writing block 12 for storing the data transferred from the register block 20 temporarily and a data restoring block 14 for restoring data from the data writing block 12 .
- the register 10 functions as a single bit register or a single bit latch.
- a general multi-bit register has the above blocks for each bit.
- the data writing block 12 is provided with MTJ (Magnetic Tunnel Junction) elements 16 a and 16 b , which are non-volatile storage elements.
- the MTJ elements 16 a and 16 b are used as memory cells of an MRAM (Magnetic Random Access Memory).
- the general MTJ element 16 a is structured as a combined layer composed of a free layer 26 , which is formed with a ferromagnetic material, a tunneling barrier 28 , and a pinned layer 30 , which is formed with a ferromagnetic material.
- the magnetizing direction in the pinned layer 30 is fixed.
- the magnetizing direction in the free layer 26 can be changed according to the direction of an external magnetic field.
- the value of the data to be stored is distinguished between “0” and “1” according to how the magnetizing directions in the pinned layer 30 and in the free layer 26 are combined.
- the resistance of the MTJ element is low, thereby the data value becomes “0”.
- the resistance of the MTJ element is high, thereby the data value becomes “1”.
- the data writing block 12 includes an AND circuit 22 b for receiving data from the register block 20 ; a NOT circuit 24 a for inverting the data value; and an AND circuit 22 a for receiving data from the NOT circuit 24 a.
- the data writing block 12 comes to include two logic circuits (the united logic circuit and the AND circuit 22 b ).
- each of the AND circuits 22 a and 22 b receives a signal via the data write (DW) line.
- the levels of the signals output from the AND circuits 22 a and 22 b are fixed at “Low” while a “Low” signal is entered to the data write (DW) line.
- the two MTJ elements 16 a and 16 b are connected to each other via a switch T 5 .
- the two MTJ elements 16 a and 16 b are composed so that the magnetizing directions in their pinned layers are opposite to each other.
- the pinned layers are disposed so as to face each other with the switch T 5 therebetween as shown with the arrows the figure.
- Switches T 1 to T 4 are connected to the MTJ elements 16 a and 16 b . Those switches T 1 to T 4 are used together with the above switch T 5 so as to form an electrical path of the data writing block 12 . For example, when the switches T 1 , T 3 , and T 5 are turned on, the switch T 1 , the MTJ element 16 a , the switch T 5 , the MTJ element 16 b , and the switch T 3 are connected serially, thereby an electrical path is formed.
- the data restoring block 14 includes MTJ elements 16 c and 16 d.
- the MTJ elements 16 c and 16 d are resistors of the MTJ elements 16 a and 16 b . Although they are shown separately for siimplicity in FIG. 1, 16 a and 16 c are physically one single MTJ element as shown in FIG. 2, so are 16 b and 16 d.
- the data restoring block 14 is also provided with a switch T 8 for receiving a signal (Data Restore: DSR) via the data restore line; a NOT circuit 24 b; and a switch T 7 for receiving a signal from the NOT circuit 24 b.
- a “Low” signal is entered to the data restore line, the switches T 7 and T 8 are turned on, thereby the switches T 6 , T 9 , and T 10 are turned on automatically.
- the switches T 6 , T 9 , and T 10 are included in the data restoring block 14 .
- the switches T 9 and T 10 shown in FIG. 1 are included in a current mirror circuit.
- a differential signal (a different between signal levels of the nodes ML and MR) is output to a node between a pair of the MTJ elements 16 c and 16 d .
- Data is distinguished between “0” and “1” according to the value of this differential signal.
- the amplifier/latching circuit (AMP & Latch) 18 connected to the nodes ML and MR amplifies and holds the differential signal.
- Two cross-coupled CMOS inverters 32 a and 32 b are used to hold the data whose value is decided by the differential signal.
- FIG. 3 shows such circuit configuration for holding data. In the circuit, the two cross-coupled CMOS inverters CMOSFETs 32 a and 32 b work together so as to hold the data.
- the switches T 1 to T 7 used for the data writing block 12 and the data restoring block 14 are all n-type MOSFETs.
- the switches T 8 to T 10 are p-type MOSFETs.
- the register I/O lines are used to enter data to the register block 20 .
- a signal is entered to a data write line/data restore line, the data writing block 12 /data restoring block 14 begins to work.
- both of the data writing block 12 and the data restoring block 14 go idle upon a “Low” signal and a “High” signal received by the data write line and data restore line respectively.
- the register 10 sends/receives signals via the register I/O lines; the data writing block 12 and the data restoring block 14 are not started up at this time.
- a clock signal used as a timing signal for the operation of the register 10 is also included in the I/O signals to/from the register 10 .
- the data stored in the register block 20 always appears on the node RO shown the figure.
- both nodes DL and DR shown in FIG. 1 are fixed at “Low” by the AND circuits 22 a and 22 b. In FIG. 1, both nodes DL and DR are fixed at “Low” respectively, thereby the switches T 1 to T 4 are all turned off.
- the register 10 then outputs a “High” signal onto the DW line, thereby turning on the switch T 5 so as to write data.
- the level of either the node DL or node DR becomes “High” due to the written data.
- the level of the node DR becomes “High”.
- the level of the node DL becomes “High”.
- the arrow shown in FIG. 1 denotes the magnetizing direction in the pinned layer 30 of each of the MTJ elements 16 a and 16 b .
- the magnetizing directions in the pinned layers 30 of the MTJ elements 16 a and 16 b connected to each other via the switch T 5 are opposite to each other.
- the data writing block 12 thus writes true “1” and complement “0” data items in the pair of the MTJ elements 16 a and 16 b . For example, when the level of the node DL is “High”, the switches T 1 , T 3 , and T 5 are turned on.
- a current flows from the switch T 1 to the left MTJ element 16 a , the switch T 5 , the right MTJ element 16 b , and the switch T 3 .
- the direction of the magnetic field generated by the current is the same as that of the magnetization in the pinned layer 30 of the left MTJ element 16 a and opposite to that of the magnetization in the pinned layer 30 of the right MTJ element 16 b .
- the magnetizing directions become identical in both of the pinned layer 30 and in the free layer of the left MTJ element 16 a and opposite to each other in those layers of the right MTJ element 16 b .
- each conventional MRAM employs a matrix structure
- a grid address is specified with a write word line and a bit line to flow and the current in the free layer. This is why switches are needed so as to switch among addresses to be specified more easily.
- the method is different from that of the conventional MRAM, since the storage element is not matrix-structured with write word lines and bit lines. And, this is why write word lines are omitted from the storage element in the register of the present invention.
- memory arrays are matrix-structured as described above and an MTJ element is disposed at each cross point.
- data is written at a cross point only when it is selected by a vertical bit line and a horizontal word line. A current is then flown in the write word line in addition to the bit line.
- the pair of the MTJ elements 16 a and 16 b shown in FIG. 1 are connected to each other via the switch T 5 and the magnetizing directions in their pinned layers 30 are opposite to each other so as to face the switch T 5 respectively as shown in FIG. 1.
- each storage element in the register of the present invention is composed by omitting write word lines of each MTJ element of the conventional MRAM.
- pinned layers 30 are shown in the MTJ elements 16 a , 16 b in the data writing block 12 and resistors are shown in the MTJ elements 16 c and 16 d in the data restoring block 14 so as to simplify the description for the operation principle, the reference symbols 16 a and 16 c are physically a single element as shown in FIG. 2, so are 16 b and 16 d .
- the pair of MTJ elements 16 c and 16 d in the data restoring block 14 is used as resistors for a current mirror circuit (composed of the switches T 9 and T 10 ) in the above embodiment of the present invention.
- the level of the DW signal is kept at “Low”.
- the DRS signal level is “High” at first, then shifted to “Low”.
- the switches T 7 and T 8 are turned on.
- the switches T 6 , T 9 , and T 10 are also actuated, thereby the current mirror circuit is enabled and the same value current flows in both of the switches T 9 and T 10 .
- a differential signal is then output to the nodes ML and MR of the pair of the MTJ elements 16 c and 16 d respectively.
- the differential signal appeared on the nodes ML and MR respectively is amplified in the amplifier/latching circuit 18 and held there.
- data decided by a potential difference between the nodes ML and MR is amplified by the amplifier/latching circuit 18 and held there.
- the potentials of the nodes ML and MR are decided by the resistance values of the MTJ elements 16 c and 16 d . Concretely, the potentials are decided by the data items written in the MTJ elements 16 a and 16 b.
- the register block 20 fetches the data from the amplifier/latching circuit 18 with use of the DRS signal.
- the data restoration is completed by the above process. After this, the “Low” DRS signal level is returned to “High”, thereby the current mirror circuit is turned off.
- Table 1 below shows the signal state at each node and how data is stored in each MTJ element in the series of above processes.
- TABLE 1 RO High Low DR High Low DL Low High MTJ element 16a “1” data “0” data MTJ element 16b “0” data “1” data ML High Low MR Low High CL High Low CR Low High
- MTJ elements can be mounted on the subject logic chip in the latter half stage of the semiconductor manufacturing process of metallic layers. Consequently, this manufacturing process of MTJ storage elements, which is simple and requires less cost, can also apply to other existing non-volatile storage elements to be employed for flash memories that require designing of transistors separately from that of logic circuits.
- the present invention therefore enables non-volatile storage elements to be mounted on any conventional logic chip.
- Non-volatile storage elements can be employed for a wide variety of devices from respective single latching registers to multiple-bit registers. Storing data in a register with no power consumption will be useful for restoring an operating environment to before-power-off one. A non-volatile storing function to be changed by the electricity of a logic chip will thus come to be used very widely. The function can also change a logic function flexibly.
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Abstract
Description
- The present invention relates to a non-volatile storage element to be integrated on a semiconductor chip, more particularly to a register that employs MTJ (Magnetic Tunnel Junction) elements used in an MRAM (Magnetic Random Access Memory), as well as a data storing method and a data reading method to be employed for the register.
- A
register block 20 is a circuit block used to store data temporarily. Theregister block 20, as shown in FIG. 4, is composed of a flip-flop circuit formed with a combination ofNAND circuits - In the
register block 20, when a “High” level signal is entered to the input line S and a “Low” level signal is entered to the input line R, the level of the Q2 line becomes “High” and that of the Q1 line becomes “Low”. When a “High” level signal is entered to the input line R and a “Low” level signal is entered to the input line S, the level of the Q1 line becomes “High” and that of the Q2 line becomes “Low”. The levels of the input lines S and R are decided by the data written in the register in such way. When a “High” signal is entered to each of the input lines S and R concurrently, the data entered to theregister block 20 is held. Generally, when a “Low” signal is entered to each of the input lines S and R concurrently, the state of theregister block 20 cannot be estimated, so that “Low” signals are never entered to the input lines S and R concurrently. - Conventionally, a latching circuit/register built in a logic chip loses data stored therein when the power supply is turned off. This is because data is stored in such a volatile storage element as a capacitor or a static latch. Consequently, the use of a non-volatile storage elements is very advantageous for many system application programs.
- There are also non-volatile semiconductor memory chips such as flash memories. However, none of designing and development has been made for any logic chip provided with built-in non-volatile storing functions. This is because the logic chip, when it is provided with an internal non-volatile memory such as a flash memory, is more complicated than the conventional semiconductor logic chip. In addition, any of the existing semiconductor chip manufacturing processes cannot incorporate such a non-volatile storage element as a flash memory in a logic chip. Consequently, none of the logic chips provided in existing computer systems and used for application programs has such the non-volatile data storing function.
- Under such circumstances, it is an object of the present invention to provide a register provided with functions for storing data into non-volatile storage elements, as well as a data storing method and a data reading method to be employed for the register.
- In order to achieve the above object, the register of the present invention includes a register block for storing data; a data writing block provided with a non-volatile storage element enabled to store the data; and a data restoring block for reading data from the data writing block.
- The data storing method of the present invention includes a step of outputting a high level signal from one of first and second logic circuits according to the data output from the register block; the high level signal turning on one of two pairs of switches connected to the first and second logic circuits, respectively, and writing data in the two storage elements with polarity according to which of the first and second pairs of switches is turned on.
- The data reading method of the present invention includes a step of generating, with current mirror circuit, a differential signal according to the resistance values of the first and second storage elements, amplifying the differential signal, and holding the amplified differential signal.
- A logic chip including the present invention is preferably configured so as to include magnetic tunnel junction (MTJ) elements, which are non-volatile storage elements. Thereby the logic chip can be designed and manufactured easily and the manufacturing cost can be reduced. In addition, because the logic chip uses non-volatile storage elements, data can be stored in them even after the power is turned off. Preferably, such non-volatile storage elements having MTJ elements are constructed so as to consume no power when power to the logic chip is turned off.
- FIG. 1 is a block diagram of a register of the present invention;
- FIG. 2 is a structure of an MTJ element;
- FIG. 3 is a circuit diagram including a pair of cross-coupled CMOS inverters used to hold data; and
- FIG. 4 is a circuit diagram used for a general register block.
- Hereunder, the preferred embodiment of the present invention for the register, the data storing method, and the data reading method will be described with reference to the accompanying drawings.
- FIG. 1 is a block diagram of the register of the present invention. As shown in FIG. 1, the
register 10 is provided with aconventional register block 20, as well as adata writing block 12 for storing the data transferred from theregister block 20 temporarily and adata restoring block 14 for restoring data from thedata writing block 12. In FIG. 1, theregister 10 functions as a single bit register or a single bit latch. A general multi-bit register has the above blocks for each bit. - The
data writing block 12 is provided with MTJ (Magnetic Tunnel Junction)elements MTJ elements - The
general MTJ element 16 a, as shown in FIG. 2, is structured as a combined layer composed of afree layer 26, which is formed with a ferromagnetic material, atunneling barrier 28, and a pinnedlayer 30, which is formed with a ferromagnetic material. The magnetizing direction in thepinned layer 30 is fixed. The magnetizing direction in thefree layer 26 can be changed according to the direction of an external magnetic field. The value of the data to be stored is distinguished between “0” and “1” according to how the magnetizing directions in thepinned layer 30 and in thefree layer 26 are combined. For example, when the magnetizing directions in thepinned layer 30 and in thefree layer 26 are identical, the resistance of the MTJ element is low, thereby the data value becomes “0”. When the magnetizing directions are opposite to each other, the resistance of the MTJ element is high, thereby the data value becomes “1”. - The
data writing block 12 includes anAND circuit 22 b for receiving data from theregister block 20; aNOT circuit 24 a for inverting the data value; and anAND circuit 22 a for receiving data from theNOT circuit 24 a. When theNOT circuit 24 a and theAND circuit 22 a are united into a logic circuit, thedata writing block 12 comes to include two logic circuits (the united logic circuit and theAND circuit 22 b). In addition, each of theAND circuits AND circuits - The two
MTJ elements MTJ elements - Switches T1 to T4 are connected to the
MTJ elements data writing block 12. For example, when the switches T1, T3, and T5 are turned on, the switch T1, theMTJ element 16 a, the switch T5, theMTJ element 16 b, and the switch T3 are connected serially, thereby an electrical path is formed. And, when the switches T2, T4 and T5 are turned on, the switch T2, theMTJ element 16 b, the switch T5, theMTJ element 16 a, and the switch T4 are connected serially, thereby another electrical path is formed. In FIG. 1, when a current flow from left to right in the switch T5, the magnetizing directions in both pinned and free layers in theMTJ element 16 a are identical, thereby “0” data is written in theMTJ element 16 a. However, the magnetizing direction in the pinned layer is opposite to that in the free layer in theMTJ element 16 b, thereby “1” data is written in theMTJ element 16 b. On the contrary, when a current flows from right to left in the switch T5, the magnetizing directions are identical in both pinned and free layers in theMTJ element 16 b, thereby “0” data is written in theMTJ element 16 b. However, the magnetizing directions in both pinned and free layers in theMTJ element 16 a are opposite to each other, thereby “1” data is written in theMTJ element 16 a. In any of the above cases, either True or Complement data is written in each of theMTJ elements - When a “High” level signal is output from the
AND circuit 22 a, the switches T1 and T3 are turned on. When a “High” level signal is output from theAND circuit 22 b, the switches T2 and T4 are turned on. The switch T5 is turned on when a “High” level signal is entered to the data write line. - The
data restoring block 14 includesMTJ elements MTJ elements MTJ elements - The
data restoring block 14 is also provided with a switch T8 for receiving a signal (Data Restore: DSR) via the data restore line; aNOT circuit 24 b; and a switch T7 for receiving a signal from theNOT circuit 24 b. When a “Low” signal is entered to the data restore line, the switches T7 and T8 are turned on, thereby the switches T6, T9, and T10 are turned on automatically. The switches T6, T9, and T10 are included in thedata restoring block 14. The switches T9 and T10 shown in FIG. 1 are included in a current mirror circuit. When all the switches in thedata restoring block 14 are turned on, a differential signal (a different between signal levels of the nodes ML and MR) is output to a node between a pair of theMTJ elements cross-coupled CMOS inverters - The switches T1 to T7 used for the
data writing block 12 and thedata restoring block 14 are all n-type MOSFETs. The switches T8 to T10 are p-type MOSFETs. - The register I/O lines are used to enter data to the
register block 20. When a signal is entered to a data write line/data restore line, thedata writing block 12/data restoring block 14 begins to work. - Next, the operation of the
register 10 will be described. While theregister 10 is operating, both of thedata writing block 12 and thedata restoring block 14 go idle upon a “Low” signal and a “High” signal received by the data write line and data restore line respectively. In this state, theregister 10 sends/receives signals via the register I/O lines; thedata writing block 12 and thedata restoring block 14 are not started up at this time. A clock signal used as a timing signal for the operation of theregister 10 is also included in the I/O signals to/from theregister 10. The data stored in theregister block 20 always appears on the node RO shown the figure. When the DW line level is fixed at “Low”, however, both nodes DL and DR shown in FIG. 1 are fixed at “Low” by the ANDcircuits - The
register 10 then outputs a “High” signal onto the DW line, thereby turning on the switch T5 so as to write data. At the same time, the level of either the node DL or node DR becomes “High” due to the written data. For example, when a “High” signal is output from theregister block 20, the level of the node DR becomes “High”. When a “Low” signal is output from theregister block 20, the level of the node DL becomes “High”. - The arrow shown in FIG. 1 denotes the magnetizing direction in the pinned
layer 30 of each of theMTJ elements MTJ elements data writing block 12 thus writes true “1” and complement “0” data items in the pair of theMTJ elements left MTJ element 16 a, the switch T5, theright MTJ element 16 b, and the switch T3. The direction of the magnetic field generated by the current is the same as that of the magnetization in the pinnedlayer 30 of theleft MTJ element 16 a and opposite to that of the magnetization in the pinnedlayer 30 of theright MTJ element 16 b. In this case, the magnetizing directions become identical in both of the pinnedlayer 30 and in the free layer of theleft MTJ element 16 a and opposite to each other in those layers of theright MTJ element 16 b. When a “Low” signal is output from theregister block 20, “0” data is written in theleft MTJ element 16 a and “1” data is written in theright MTJ element 16 b. When the level of the node DR is “High”, the switches T2, T4, and T5 are turned on. The combination of the magnetizing directions thus becomes opposite to that of the above example. The data to be stored in thedata writing block 12 is thus decided by whether the DL line is driven to “High” or the DR line is driven to “High”. As described above, data can be rewritten easily in the pair of theMTJ elements - Because each conventional MRAM employs a matrix structure, a grid address is specified with a write word line and a bit line to flow and the current in the free layer. This is why switches are needed so as to switch among addresses to be specified more easily. When in writing operation in the register of the present invention, however, the method is different from that of the conventional MRAM, since the storage element is not matrix-structured with write word lines and bit lines. And, this is why write word lines are omitted from the storage element in the register of the present invention.
- In a general MRAM that includes MTJ elements, memory arrays are matrix-structured as described above and an MTJ element is disposed at each cross point. In such the MTJ element, data is written at a cross point only when it is selected by a vertical bit line and a horizontal word line. A current is then flown in the write word line in addition to the bit line. On the contrary, the pair of the
MTJ elements layers 30 are opposite to each other so as to face the switch T5 respectively as shown in FIG. 1. And, because theMTJ elements - In the above embodiment, pinned layers30 are shown in the
MTJ elements data writing block 12 and resistors are shown in theMTJ elements data restoring block 14 so as to simplify the description for the operation principle, thereference symbols MTJ elements data restoring block 14 is used as resistors for a current mirror circuit (composed of the switches T9 and T10) in the above embodiment of the present invention. - When non-volatile data is to be read from the
register 10, the level of the DW signal is kept at “Low”. The DRS signal level is “High” at first, then shifted to “Low”. When the signal level is shifted from “High” to “Low” such way, the switches T7 and T8 are turned on. Then, the switches T6, T9, and T10 are also actuated, thereby the current mirror circuit is enabled and the same value current flows in both of the switches T9 and T10. - A differential signal is then output to the nodes ML and MR of the pair of the
MTJ elements circuit 18 and held there. In other words, data decided by a potential difference between the nodes ML and MR is amplified by the amplifier/latchingcircuit 18 and held there. The potentials of the nodes ML and MR are decided by the resistance values of theMTJ elements MTJ elements - Data is then held in the circuit shown in FIG. 3. The amplified potential of the node ML appears at the node ML′ while the amplified potential of the node MR appears at the node MR′. The potentials of the nodes ML′ and MR′ then appear at the nodes CL and CR respectively when the n-
type MOSFETs - In order to enter data to the
register 10, theregister block 20 fetches the data from the amplifier/latchingcircuit 18 with use of the DRS signal. The data restoration is completed by the above process. After this, the “Low” DRS signal level is returned to “High”, thereby the current mirror circuit is turned off. - Table 1 below shows the signal state at each node and how data is stored in each MTJ element in the series of above processes.
TABLE 1 RO High Low DR High Low DL Low High MTJ element 16a “1” data “0” data MTJ element 16b “0” data “1” data ML High Low MR Low High CL High Low CR Low High - MTJ elements can be mounted on the subject logic chip in the latter half stage of the semiconductor manufacturing process of metallic layers. Consequently, this manufacturing process of MTJ storage elements, which is simple and requires less cost, can also apply to other existing non-volatile storage elements to be employed for flash memories that require designing of transistors separately from that of logic circuits. The present invention therefore enables non-volatile storage elements to be mounted on any conventional logic chip.
- Non-volatile storage elements can be employed for a wide variety of devices from respective single latching registers to multiple-bit registers. Storing data in a register with no power consumption will be useful for restoring an operating environment to before-power-off one. A non-volatile storing function to be changed by the electricity of a logic chip will thus come to be used very widely. The function can also change a logic function flexibly.
- While a description has been made for methods for storing and reading data in/from the register of the present invention, the present invention is not limited only for the uses. For example, the MTJ elements may be replaced with GMR (Giant Magnetoresistive) elements. And, obviously many modifications and variations of the present invention are possible without departing from the spirit of the invention.
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Claims (16)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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JP2001130652 | 2001-04-27 | ||
JP2001-130652 | 2001-04-27 | ||
JP2001199556A JP4282919B2 (en) | 2001-04-27 | 2001-06-29 | register |
JP2001-199556 | 2001-06-29 |
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US20020181275A1 true US20020181275A1 (en) | 2002-12-05 |
US6639834B2 US6639834B2 (en) | 2003-10-28 |
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US10/134,101 Expired - Lifetime US6639834B2 (en) | 2001-04-27 | 2002-04-26 | Data register and access method thereof |
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JP (1) | JP4282919B2 (en) |
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2002
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Also Published As
Publication number | Publication date |
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JP4282919B2 (en) | 2009-06-24 |
JP2003016773A (en) | 2003-01-17 |
US6639834B2 (en) | 2003-10-28 |
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