US20040183604A1

US20040183604A1 - High frequency signal source and method of generating same using dielectric resonator oscillator (DRO) circuit

Info

Publication number: US20040183604A1
Application number: US10/766,730
Authority: US
Inventors: Danny Ammar; Conrad Jordan
Original assignee: Xytrans Inc
Current assignee: Reveal Imaging LLC
Priority date: 2002-05-29
Filing date: 2004-01-28
Publication date: 2004-09-23
Also published as: WO2003103147A1; US20030222725A1; AU2003221879A1; US6714089B2

Abstract

A high frequency signal source and method of generating a high frequency signal is disclosed. An output signal is generated from a dielectric resonator oscillator and mixed with an output signal from a voltage controlled oscillator having a predetermined tuning range and part of a phase locked loop circuit to sum the frequencies for creating a final output frequency. A portion of the final output frequency is coupled into the phase locked loop circuit that is phase locked to a reference signal from a crystal reference oscillator. The voltage controlled oscillator has a tuning range that is used to compensate for the dielectric resonator oscillator initial frequency error and drift over temperature and aging while the balance of the bandwidth is used to provide the tuning range on the local oscillator output. The phase locked loop circuit is phase locked to the reference crystal oscillator that is used to compensate for any initial dielectric resonator oscillator frequency errors because of manufacturing and for any drift because the temperature changes or aging.

Description

RELATED APPLICATION

This application is based upon prior filed copending provisional application Serial No. 60/383,959 filed May 29, 2002.[0001]

FIELD OF THE INVENTION

This invention relates to communication systems, and more particularly, this invention relates to high frequency signal sources using dielectric resonator oscillators (DRO's) used for producing a local oscillator signal.

BACKGROUND OF THE INVENTION

In communication circuits, the Local Oscillator (LO) signal must exhibit low phase noise, corresponding to the random phase instability of a signal, to meet the signal requirements of the digital modulation scheme used in a communications system. The signal also must maintain acceptable bit error rate (BER) requirements. Any circuit that generates the local oscillator signal should have a wide tuning range for multiple channel selection, and a minimal frequency drift over temperature to maintain the transceiver locked into a selected channel. It should provide enough power to drive directly a mixer for up or down frequency conversion as required in modern, high frequency communications systems.

Free running Dielectric Resonator Oscillators (DRO) are attractive, high frequency microwave sources because of their high Q, low phase noise, good output power and a relatively high stability of operation versus temperature. These type of oscillators represent a good compromise of cost, size, and performance compared to alternative prior art signal sources, such as cavity oscillators or multiplied crystal oscillators. Dielectric resonator oscillators, however, do not have any controllable tuning range, and they exhibit frequency drift versus temperature and aging. Also, these devices have always required manual tuning to achieve the desired frequency accuracy.

Voltage controlled Dielectric Resonator Oscillators (DRO) are similar devices that are also attractive microwave sources because of their high Q, low phase noise, good output power and high stability versus temperature. These devices also represent a fair compromise of cost, size, and performance compared to cavity oscillators and multiplied crystal oscillators. Drawbacks of voltage controlled dielectric resonator oscillators are limited electronic tuning range and have a reduced Q because of varactor pulling. They also exhibit frequency drift versus temperature and aging. As a result, these dielectric resonator oscillators have always required manual tuning to achieve the desired frequency accuracy.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a high frequency signal source and method using a Dielectric Resonator Oscillator (DRO) circuit that overcomes the disadvantages of the prior art described above.

It is another object of the present invention to provide a high frequency signal source using a digitally compensated, frequency accurate, free running dielectric resonator oscillator circuit that overcomes the disadvantages of the prior art.

The present invention provides a novel and unobvious signal source using a digitally compensated, frequency accurate, free running dielectric resonator oscillator that resolves the shortcomings of traditional free running dielectric resonator oscillators. The circuit of the present invention provides a wide frequency tuning range, requires no manual tuning, and eliminates frequency drift over temperature and aging. The present invention can be used for generating a low cost, stable, and high frequency local oscillator source for terrestrial and satellite communications.

The high frequency signal source of the present invention generates a high frequency local oscillator signal using a free running dielectric resonator oscillator, which is compensated by a Phase Locked Loop (PLL), Voltage Controlled Oscillator (VCO), thus, eliminating the requirement for manual tuning of the dielectric resonator oscillator. The circuit of the present invention automatically compensates for dielectric resonator oscillator frequency drift over temperature and aging, and achieves a wide frequency tuning range without compromising phase noise performance. It eliminates manufacturing complexity, tuning and the costs associated with a voltage controlled dielectric resonant oscillator currently used by many skilled in the art. It also self-compensates for frequency drift caused by mechanical or printed circuit board (PCB) variation over temperature.

In accordance with the present invention, the high frequency signal source includes a dielectric resonator oscillator having an output signal. A mixer receives the output signal from the dielectric resonator oscillator. A phase locked loop circuit has a voltage controlled oscillator with a predetermined tuning range operatively connected to the mixer such that the mixer receives an output frequency from a voltage controlled oscillator and sums the output frequencies for creating a summed output frequency. A portion of the summed output frequency is fed as a coupled signal into the phase locked loop circuit that is phase locked to a reference signal, wherein a higher output frequency accuracy with low phase noise is achieved without manual tuning and a portion of the tuning range of the voltage controlled oscillator compensates for any dielectric resonator oscillator initial frequency error and drift over temperature and aging.

In yet another aspect of the present invention, a crystal reference oscillator is operatively connected to the phase locked loop circuit and provides a stable reference signal thereto. A filter is operatively connected to the mixer and filters the summed output frequency and eliminates unused side bands. The filter includes a high side filter that filters the upper side band of the summed output frequency and provides a final output frequency. A low side filter is operatively connected to the phase locked loop circuit and filters the lower side band of the summed output frequency and provides a coupled signal to the phase locked loop circuit.

An amplifier is operatively connected to the mixer and amplifies the summed output frequency. A divider circuit can be positioned within the phase locked loop circuit and divide the coupled signal by a factor “N”, respectively. A phase locked loop chip can have registers that are programmed for dividing the coupled signal and reference signal by a divide ratio “M” and “N”. A microcontroller is connected to the phase locked loop chip and can program the divide ratio between “M” and “N”.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, features and advantages of the present invention will become apparent from the detailed description of the invention which follows, when considered in light of the accompanying drawings in which: [0013]
FIG. 1 is a partial, schematic circuit diagram of a prior art, free running dielectric resonator oscillator. [0014]
FIG. 2 is a block diagram of a phased locked loop dielectric resonator oscillator frequency synthesizer that generates a high frequency signal. [0015]
FIG. 3 is a block diagram of a high frequency signal source of the present invention using a self-tuned dielectric resonator oscillator frequency synthesizer. [0016]
FIG. 4 is a block diagram of another embodiment of the high frequency signal source of the present invention using a self-tuned dielectric resonator oscillator frequency synthesizer.[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. [0018]
The present invention provides a novel and unobvious high frequency signal source using a digitally compensated, frequency accurate, free running dielectric resonator oscillator that resolves the shortcomings of traditional free running dielectric resonator oscillators. The circuit of the present invention provides a wide frequency tuning range, requires no manual tuning, and eliminates frequency drift over temperature and aging. The present invention can be used for generating a low cost, stable, and high frequency local oscillator source for terrestrial and satellite communications. [0019]
The high frequency signal source of the present invention generates a high frequency local oscillator signal using a free running dielectric resonator oscillator, which is compensated by a Phase Locked Loop (PLL), Voltage Controlled Oscillator (VCO), thus, eliminating the requirement for manual tuning of the dielectric resonator oscillator. The circuit automatically compensates for dielectric resonator oscillator frequency drift over temperature and aging, and achieves a wide frequency tuning range without compromising phase noise performance. It eliminates manufacturing complexity, tuning and cost of a voltage controlled, dielectric resonant oscillator currently as used by many skilled in the art. It also self-compensates for frequency drift caused by mechanical or printed circuit board (PCB) variation over temperature. [0020]
For purposes of background, a brief explanation of a common dielectric resonator oscillator will be explained, followed by a more detailed description of the present invention. [0021]
As known to those skilled in the art, there are essentially four different classes of free running dielectric resonator oscillators that are used by circuit designers for high frequency signal sources and associated circuits. These oscillators include reaction, transmission, parallel feedback and reflection dielectric resonator oscillators. The reflection dielectric resonator oscillator is the most commonly used in communication systems. This type of dielectric resonator oscillator uses a negative resistance in which the dielectric resonator is placed near a terminated microstrip line that is connected to the input of an unstable amplifier, such as a field effect transistor (FET). Near its resonant frequency, the dielectric resonator reflects power back to the amplifier, causing an oscillation build-up between the two components that is tapped. [0022]
As known to those skilled in the art, dielectric resonator oscillators that are stabilized have become very practical and useful devices ever since the development of high dielectric constant, high Q, low loss temperature compensated ceramic materials. Usually, the dielectric resonator oscillator includes a dielectric resonator having a “puck” or other resonant element as known to those skilled in the art. A field effect transistor (FET) is coupled to an impedance matching network. The resonant structure or “puck” is contained in a resonator cavity, which could be formed by different structures, such as a metallic cylinder, and positioned near one or more microstrips. The “puck” is sometimes positioned on a base and, in many prior art examples, the structures include manual tuning screws that are mounted for selective movement into a cavity such that the “puck,” a resonant “disk” or other resonant element is positioned a fractional or other wavelength distance away from one or more microstrip lines and at an appropriate height thereto. [0023]
FIG. 1 shows a prior art reflection dielectric resonator oscillator circuit [0024] 10. Two major elements in this circuit 10 are the dielectric resonator 12 and the field effect transistor (FET) amplifier 14. The dielectric resonator 12, which is made of high Q material, defines the Q of the circuit and locks the frequency. At present, commercially available dielectric resonators exhibit Q_oas high as 10,000 at 10 GHz, and a dielectric constant between 34 and 40. As for the amplifier, GaAs field effect transistors have ben found to be suitable amplifiers for high frequency dielectric resonator oscillator circuits because they naturally exhibit a very high F_t, a good loop gain and enough output power in the Ku-band and up to 25 GHz.
FIG. 1 illustrates that the [0025] dielectric resonator 12 contains the puck 12 a or other resonant element and is positioned a distance “d” from a desired 50 ohm microstrip transmission line 16 that is terminated with a resistor R1 to ground. The field effect transistor 14 includes the normal source (S), drain (D) and gate (G) that are connected to the impedance matching network 18. The gate (G) is controlled by a select signal line SS1 19 or other control line that is operative with a microcontroller or other circuit controller 20. A drain-source connection pad (DS) 19 a is operatively connected to the field effect transistor 14, together with appropriate other components, including various resistors R2 and R3 and capacitors C1 and C2 that are in a “pie” n configuration with a coil inductor L1. Capacitor C3 is operatively connected to the dielectric resonator oscillator output and provides filtering for the signal. Resistor R3 is connected to the supply voltage of the drain Vdd as indicated in FIG. 1. Other matching network components 19 b as indicated by rectangular blocks are included as chosen by those skilled in the art.
The position of the [0026] dielectric resonator 12 relative to the transmission line 16 determines the stability, output power and phase noise of the overall oscillator. Adjusting the distance “d” in FIG. 1 increases or decreases the amount of coupling. A higher coupling provides more output power and robustness of oscillation build-up. This higher coupling, however, reduces the load Q and therefore, the phase noise performance. A lower coupling will improve phase noise, but it reduces the output power and may cause the dielectric resonator oscillator to fail to oscillate. The phase relationship of the resonator element (“puck”) 12 a to the active devices, such as the field effect transistor 14 and/or other components, is equally critical to create an oscillation build-up in an efficient manner. The electrical length (θ), representing the physical distance between the field effect transistor 14 and the plane of reference for the puck 12 a determines how fast and stable the build-up will occur, driving both output power and phase noise performance.
In traditional dielectric resonator oscillator circuits, the electrical layout is only one aspect of the oscillator design. Mechanical aspects also influence the performance of this local oscillator. The size and height of the cavity used for containing the [0027] puck 12 a have loading effects on the local oscillator, which can reduce the phase noise performance and create unwanted frequency drift over temperature. As a rule of thumb, the cavity should be at least three pucks high and three pucks wide, in order to have reasonable thermal and loading effects. The height requirement is one of the reasons that circuit designers prefer to position a dielectric resonator on a “stand-off” to aid in ensuring that the housing and the printed circuit board on which the dielectric resonator usually rests does not adversely affect the performance of the resonator.
The lack of mechanical integrity for the material of the printed circuit board also causes local oscillators to drift over temperature and create long-term aging effects, especially if the cavity is resting on the printed circuit board. Although the printed circuit board material, such as the Rogers 4003 Board by Rogers Corporation, as known to those skilled in the art, is hard enough to allow only minimum variations, frequency drift due to aging still occurs. In most of these prior art circuits, the fine-tuning and adjustment of the dielectric resonator oscillator is set by manually turning a tuning screw to increase the dielectric resonator resonant frequency as it closes the electrical field above the puck. This provides as much as 60 MHz of tuning range. Tuning this frequency with a tuning screw, however, is achieved at the expense of reduction in both unloaded Q and temperature stability. [0028]
Some prior art dielectric resonator oscillator circuit designs, on the other hand, have locked the frequency to a reference signal using a phase locked loop circuit. As illustrated in FIG. 2, an example of a dielectric resonator oscillator circuit is operatively connected to a [0029] coupler 32 at its output. A portion of the output signal from the dielectric resonator oscillator 30 is coupled into a phase locked loop circuit 34, which receives an external reference signal, such as from a crystal oscillator 36. The coupled output signal is typically divided down within divider circuit 38 before passing into a phase locked loop chip 40 that may include other divide circuits and a phase detector, as known to those skilled in the art. Any programmable divider circuits in the phase locked loop circuit can be used in a feedback loop to divide the coupled output signal by a factor “N” and also divide any reference signal generated by the crystal oscillator 36 by a factor “M,” such that outputs are equal to a common phase comparison frequency using techniques known to those skilled in the art.
In this typical phase locked loop dielectric resonator oscillator circuit of FIG. 2, the [0030] dielectric resonator oscillator 30 is phase locked to a reference crystal oscillator 36 to control the frequency drift. Although this design addresses some of the frequency drift issues, it does not adequately address the need for manual tuning of the dielectric resonator oscillator 30 during manufacture to set it to the desired frequency. It also has a limited tuning range, typically about 10 MHz.
It is evident that the more traditional dielectric resonator oscillator designs suffer from the following shortcomings: [0031]
1. Frequency drift versus temperature and aging; [0032]
2. Frequency drift caused by printed circuit board and mechanical variations versus temperature; [0033]
3. Manual tuning and adjustments as required to set the dielectric resonator resonant frequency at the desired output; [0034]
4. Reduced temperature stability caused by frequency tuning with a tuning screw; [0035]
5. Manual tuning of the puck position to achieve optimum performance; [0036]
6. Manual tuning of the field effect transistor amplifier to achieve high output power; and [0037]
7. A very limited electronic tuning range. [0038]
The present invention provides a unique circuit structure and method of designing and building a high frequency signal source that uses frequency accurate, free running dielectric resonator oscillator. The present invention generates a high frequency local oscillator signal while resolving all the shortcomings of traditional dielectric resonator oscillators. The design provides a wide frequency tuning range, requires no manual tuning, and eliminates frequency drift over temperature and aging. [0039]
FIG. 3 is a block diagram showing major circuit components of the present invention and showing a high [0040] frequency signal source 50 that uses frequency accurate dielectric resonator oscillator. The signal source 50 of the present invention requires no manual tuning of the dielectric resonator oscillator 52, yet achieves a high output frequency accuracy, low phase noise, and no drift over temperature.
As illustrated, a free running [0041] dielectric resonator oscillator 52 is formed as a structure known to those skilled in the art, and includes a field effect transistor 53, and any matching networks as may be necessary. The oscillator 52 outputs a signal at a frequency F_DROinto a mixer 54 that also receives an output signal generated from a voltage controlled oscillator 56 as indicated by the signal F_FCO. The mixer 54 outputs a summed frequency F_DRO+F_VCOthrough a bandpass filter 58 and into an amplifier 60, where the frequency is amplified and output as a final local oscillator high frequency signal F_LO.
A portion of the final frequency signal used for the local oscillator signal is coupled [0042] 62 from a coupler into a divider circuit 64 that is part of a phase locked loop circuit 66, including a phase locked loop chip 68 that receives an external reference signal from a crystal reference oscillator 70. The phase locked loop chip 68 can include internal divide circuits that are separate from the divider circuit 64 and can be formed by chip registers 68a contained in the phase locked loop chip 68 and controlled by a microcontroller 72.
The divide circuits in [0043] chip 68 can also divide the reference signal by a factor “M.” It is, thus, possible to establish a ratio between “N” and “M” such that various output signals can be made equal to desired multiples of the reference frequency supplied by the external crystal reference 70. The output from the phase locked loop chip 68 passes through a loop filter 74, which typically is a low-pass filter that passes signals only below an established cut-off frequency for the phase locked loop circuit 66. An error signal is typically a varying DC level signal that is used to control the frequency of the voltage controlled oscillator.
The phase detector as part of the phase locked loop chip includes the two input signals as the external reference signal from the [0044] crystal reference 70 and the output from the coupler that is “divided-down.” The circuit design, as shown in FIG. 3, allows the high frequency signal source 50 using the frequency accurate dielectric resonator oscillator to require no manual tuning and achieve a high output frequency accuracy, low phase noise and no drift over temperature.
As an example, if the desired local oscillator frequency is 9.5 GHz, the free running [0045] dielectric resonator oscillator 52 is used to generate about 8 GHz, and the remaining 1.5 GHZ is provided by the voltage controlled oscillator 56. A low cost voltage controlled oscillator, running at 1.5 GHz provides up to 150 MHz tuning range. A portion of this tuning range is used to compensate for the dielectric resonator oscillator initial frequency error and drift over temperature and aging, and the rest is used to provide some tuning range on the local oscillator output.
The phase locked [0046] loop circuit 66 is phase locked to the reference crystal oscillator 70 and used to compensate for any initial dielectric resonator oscillator frequency errors due to manufacturing and for any drift due to temperature changes or aging. The major phase locked loop circuit function is usually available on a single chip, as noted before, with any necessary phase detector function and signal divider/multiplier functions incorporated therein. The output of the dielectric resonator oscillator 52 is mixed with the voltage controlled oscillator 56 output signal to create the desired summed output frequency. The output of the mixer is filtered to eliminate the unused lower or upper side bands. The signal is amplified and ready to be used as an local oscillator source signal.
Part of the summed frequency is coupled from the [0047] coupler 62 as a coupled signal to operate the phase locked loop circuit. The coupled signal is divided down in frequency by a factor of 4 to 8 to generate a lower frequency. The phase locked loop chip 68 can further divide the coupled output by a factor “N” to make the divided output equal to the reference clock frequency. As noted before, the phase locked loop chip 68 also has the ability to divide the reference frequency clock signal generated by the crystal reference oscillator 70 by a factor “M” to align the divided local oscillator frequency with the reference signal frequency. The microcontroller 72 programs the phase locked loop chip registers 68a with the desired divide ratios (“M” and “N”).
The [0048] microcontroller 72 also optimizes the dielectric resonator oscillator output signal by adjusting the field effect transistor gate bias. The crystal oscillator frequency is usually between 10 to 100 MHz. The choice of the crystal is critical because the frequency source output phase noise and spur level is a direct multiplication of the reference frequency source phase noise and spur level. The loop filter bandwidth is typically between 1 and 3 KHz.
FIG. 4 illustrates another embodiment of the present invention. In this design, the summed output frequency of the [0049] mixer 52 is filtered by a high side filter 58 a and a low side filter 58 b parallel thereto into respective upper (F_DRO+F_VCO) and lower (F_DRO−F_VCO) side bands. The upper side band is used to generate a final output frequency as the local oscillator output frequency, while the lower side band is used to form the coupled signal frequency and feed the phase locked loop circuit 66. A major advantage of this embodiment is that it provides a lower frequency for the phase locked loop circuit to divide in order to equal the reference clock frequency. The design eliminates the necessity for an external divider chip and allows direct use of the phase locked loop internal divider, which results in less complexity.
The dielectric resonator oscillator, the voltage controlled oscillator, the phase locked loop chips, and the reference crystal oscillator are assembled using standard surface mount methods. The “puck” is placed in its location defined by a trace on the board. A housing cover, without a tuning screw is placed over the dielectric resonator oscillator. On “turn-on,” the microcontroller optimizes the gate bias for the dielectric resonator oscillator field effect transistor amplifier and writes the divide ratios for the phase locked loop chip. The phase locked loop input, which is a coupled portion of the local oscillator signal is then compared to the reference clock phase. The error signal is used to generate a voltage control signal that is used to compensate the voltage controlled oscillator output frequency. [0050]
This process is accomplished at initial “power-up” and on a continuous basis over the life of this frequency synthesizer forming the high frequency signal source of the present invention. As the dielectric resonator oscillator frequency drifts over time and temperature, the phase locked loop circuit senses this drift at the local oscillator output and corrects for it by adjusting the voltage controlled oscillator output. In addition to compensating for the dielectric resonator oscillator drift, the voltage controlled oscillator is used to provide some amount of local oscillator frequency tuning. Assuming that about 50 MHz of the voltage controlled oscillator tuning range is used for dielectric resonator oscillator compensation, there should at least be 100 MHz of available for tuning the local oscillator frequency range. [0051]
Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the invention is not to be limited to the specific embodiments disclosed, and that the modifications and embodiments are intended to be included within the scope of the dependent claims. [0052]

Claims

That which is claimed is:

1. A high frequency signal source comprising:

a dielectric resonator oscillator having an output signal;

a mixer that receives the output signal from the dielectric resonator oscillator; and

a phase locked loop circuit having a voltage controlled oscillator with a predetermined tuning range and operatively connected to said mixer such that said mixer receives an output signal from the voltage controlled oscillator and sums the output frequencies from the dielectric resonator oscillator and voltage controlled oscillator for creating a summed output frequency, wherein a portion of the summed output frequency is fed as a coupled signal into the phase locked loop circuit that is phase locked to a reference signal to compensate for dielectric resonator oscillator frequency errors due to manufacturing and for any drift due to temperature changes or aging, wherein a higher output frequency accuracy with low phase noise is achieved without manual tuning and a portion of the tuning range of the voltage controlled oscillator compensates for any dielectric resonator oscillator initial frequency errors and drift over temperature and aging.

2. A high frequency signal source according to claim 1, and further comprising a crystal reference oscillator operatively connected to the phase locked loop circuit for providing a stable reference signal thereto.

3. A high frequency signal source according to claim 1, and further comprising a filter operatively connected to the mixer for filtering the summed output frequency and eliminating unused side bands.

4. A high frequency signal source according to claim 1, wherein said filter further comprises a high side filter for filtering the upper side band of the summed output frequency and provides a final output 5 signal, and a low side filter operatively connected to the phase locked loop circuit for filtering the lower side band of the summed output frequency to provide a coupled signal to the phase locked loop circuit.

5. A high frequency signal source according to claim 1, and further comprising an amplifier operatively connected to said mixer for amplifying the summed output frequency.

6. A high frequency signal source according to claim 1, and further comprising a divider circuit positioned within said phase locked loop circuit for dividing the coupled signal by a factor “N”.

7. A high frequency signal source according to claim 1, and further comprising a phase locked loop chip having registers that are programmed for dividing the coupled signal and reference signal by a divide 5 ratio between “M” and “N”, respectively.

8. A high frequency signal source according to claim 7, and further comprising a microcontroller operatively connected to said phase locked loop chip for programming the divide ratio between “M” and “N”.

9. A high frequency signal source comprising:

a dielectric resonator oscillator having a field effect transistor and an output signal;

a mixer that receives the output signal from the dielectric resonator oscillator;

a phase locked loop circuit having a phase locked loop chip and a voltage controlled oscillator with a predetermined tuning range and operatively connected to said mixer such that the mixer receives an output signal from the voltage controlled oscillator and sums the output signals for creating a summed output frequency, wherein a portion of the summed output frequency is fed as a coupled signal into the phase locked loop chip that is phase locked to a reference signal to compensate for dielectric resonator oscillator frequency errors due to manufacturing and for any drift due to temperature changes or aging, wherein a higher output frequency accuracy with low phase noise is achieved without manual tuning and a portion of the tuning range of the voltage controlled oscillator is used to compensate for any dielectric resonator oscillator initial frequency errors and drift over temperature and aging; and

a microcontroller operatively to said field effect transistor of the dielectric resonator oscillator and phase locked loop chip for determining a divide ratio between “M” and “N” for the coupled signal and reference signal respectively and adjusting gate bias on the field effect transistor.

10. A high frequency signal source according to claim 9, and further comprising crystal reference oscillator operatively connected to the phase locked loop chip for providing a stable reference signal thereto.

11. A high frequency signal source according to claim 9, and further comprising a filter operatively connected to the mixer for filtering the summed output frequency and eliminating unused side band signals.

12. A high frequency signal source according to claim 11, wherein said filter further comprises a high side filter for filtering the upper side band of the summed output frequency and providing a final output signal, and a low side filter operatively connected to the phase locked loop circuit for filtering the lower side band of the summed output frequency and providing a coupled signal to the phased lock loop chip.

13. A high frequency signal source according to claim 9, and further comprising an amplifier operatively connected to said mixer for amplifying the summed output frequency.

14. A high frequency signal source according to claim 9, and further comprising a divider circuit positioned within said phase locked loop circuit and connected to said phase locked loop chip for dividing the coupled signal by a factor “N”.

15. A high frequency signal source according to claim 9, wherein said phase locked loop chip includes registers that are programmed for dividing the coupled signal and reference signal by a divide ratio between “M” and “N”, respectively.

16. A method of generating a high frequency signal comprising the steps of:

mixing an output signal generated from a dielectric resonator oscillator with an output signal from a voltage controlled oscillator having a predetermined tuning range and part of a phase locked loop circuit to sum the frequencies for creating a summed output frequency; and

coupling a portion of the summed output frequency as a coupled signal into the phase locked loop circuit that is phase locked to a reference signal to compensate for dielectric resonator oscillator frequency errors due to manufacturing and for any drift due to temperature changes or aging, wherein a higher output frequency accuracy with lower phase noise is achieved without manual tuning and a portion of the tuning range of the voltage controlled oscillator compensates for any dielectric resonator oscillator initial frequency errors and drift over temperature and aging.

17. A method according to claim 16, and further comprising the step of filtering the summed output frequency before coupling to aid in eliminating unused side bands.

18. A method according to claim 17, and further comprising the step of filtering the summed output frequency within a high side filter that filters the upper side band of the summed output frequency for providing a final output frequency and filtering the summed output frequency of the summed signal within a low side filter that filters the lower side band to provide a signal to the phased lock loop circuit.

19. A method according to claim 17, and further comprising the step of filtering within a bandpass filter.

20. A method according to claim 16, and further comprising the step of amplifying the signal before coupling.

21. A method according to claim 16, and further comprising the step of dividing the coupled signal by a factor “N”.

22. A method according to claim 16, and further comprising the step of dividing the coupled signal within a divider circuit.

23. A method according to claim 16, and further comprising the step of dividing the coupled signal within registers contained within a phase locked loop circuit chip.