US20120179942A1 - Memory system - Google Patents
Memory system Download PDFInfo
- Publication number
- US20120179942A1 US20120179942A1 US13/426,696 US201213426696A US2012179942A1 US 20120179942 A1 US20120179942 A1 US 20120179942A1 US 201213426696 A US201213426696 A US 201213426696A US 2012179942 A1 US2012179942 A1 US 2012179942A1
- Authority
- US
- United States
- Prior art keywords
- memory
- erase operations
- exhaustion level
- self
- threshold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/16—Protection against loss of memory contents
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/008—Reliability or availability analysis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
Definitions
- the present invention relates to a memory system.
- a flash memory has such characteristics that data is not erased even if it is powered off, and it has a structure suitable for high integration, and used in information apparatuses such as a mobile phone and a digital camera.
- Types of Flash EEPROM nonvolatile memory are mainly an NOR type and an NAND type.
- NOR type a read rate is high, the number of read operations is about 10 13 , and it is used as an instruction code storage.
- the NOR type has a small effective bandwidth for writing, and therefore not suitable for file recording.
- NAND type although an access rate is low compared to the NOR type, high integration is allowed, a large number of bits can be stored or erased at the same time is large, and written data can be captured in burst and programming is allowed in page units having many bits.
- the NAND type memory has a large effective bandwidth, and is used for a memory card, a USB memory, a memory of a mobile phone, a memory of a portable music player, and the like. Recently, it is also considered as a replacement of a hard disk (hereinafter referred to as an HDD).
- an HDD hard disk
- An HDD is equipped with a Self-Monitoring, Analysis and Reporting Technology (commonly known as SMART), which is a self-diagnosis function intended for early detection of a failure of the HDD itself and failure prediction, and thereby can notify a user of failure rate.
- SMART Self-Monitoring, Analysis and Reporting Technology
- Many of currently manufactured HDDs have this SMART, and predict a failure rate from items including a temperature, an operating time, a spin-up time, the number of alternate sectors (spare areas in which a sector causing bad data is arranged), and the like.
- an NAND type flash memory is also considered to need reliability equivalent to HDDs, it requires a self-diagnosis function like SMART.
- reason of failure in the NAND type flash memory is different from that of the HDDs. Due to characteristics of recoding media of HDDs, they have no limit on the number of write operations, but is susceptible to heat. Further, since they are machine components, there is a problem of aged deterioration of mechanical operation. On the other hand, the NAND type flash memory has little machine components, but consideration should be given to a failure caused by bad data due to an excessive number of store/erase operations. Therefore, a new criterion of system lifetime is needed in consideration of the number of store/erase operations specific to the NAND type flash memory.
- a limit on the number of store/erase operations of the NAND type flash memory will be described.
- high voltage is applied between a substrate and a gate such that electrons are injected and released into a floating gate. If this is performed many times, gate oxide film around the floating gate is deteriorated, and if it is left as is for a long time, the electrons injected into the floating gate get out therefrom, and data is destroyed. In other words, as the number of write operations increases, retention characteristics degrade.
- the number of write operations of current flash memories is about 10 5 , which is less than that of other nonvolatile memories.
- wear leveling is performed in which the number of erase operations is counted and a threshold value is set for each block, and physical address translation is performed between a block whose number of erase operations is large and a block whose number of erase operations is small, so that the numbers of store/erase operations are averaged.
- a storage device which determines a memory state of a flash memory or the like, including: a memory having a main memory area and a spare memory area; display means; and processing means, wherein, when the number of rewrite operations in each address of the main memory area reaches a specified number, information stored in the address is transferred to the spare memory area; and when a remaining capacity of the spare memory area reaches a specified remaining capacity, the display means is driven to notify an operator or the like of a time to replace the memory (see, for example, Japanese Patent Laid-Open No. 2000-181805).
- an end of memory lifetime for writing is determined to be reached and the memory is replaced in a state where the number of write operations in the spare memory area is still small. Therefore, the memory cannot be efficiently used.
- An object of the present invention is to provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used.
- a memory system includes: a first memory in which data can be electrically written/erased; a second memory which counts the number of erase operations of the first memory and retains the number of erase operations and a maximum number of erase operations of the first memory; and a controller which is connected to be given a self-diagnosis command from an outside through a connection interface, and which retrieves the number of erase operations and the maximum number of erase operations from the second memory based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the outside through the connection interface.
- a memory system includes: a first memory in which data can be electrically written/erased; a second memory which monitors an amount of writing and an amount of reading with respect to the first memory, and retains the amount of writing, the amount of reading, and a limiting amount of writing based on a capacity of the first memory and a limiting number of write operations; and a controller which is connected to be given a self-diagnosis command from an outside through a connection interface, and which retrieves the amount of writing, the amount of reading, and the limiting amount of writing from the second memory based on the self-diagnosis command and outputs the amount of writing, the amount of reading, and the limiting amount of writing to the outside through the connection interface.
- a memory state such as an exhaustion level can be determined, and a memory can be efficiently used.
- FIG. 1 is a schematic configuration diagram of a memory system according to a first embodiment of the present invention
- FIG. 2 is a diagram which illustrates operations of each unit associated with exhaustion level calculation and alarm notification
- FIG. 3 is a diagram which shows one example of backup alarm display
- FIG. 4 is a diagram which shows a flow of exhaustion level calculation and notification to a user
- FIG. 5 is a schematic configuration diagram of a memory system according to a second embodiment of the present invention.
- FIG. 6 is a diagram which illustrates each unit associated with exhaustion level calculation and alarm notification
- FIG. 7 is a diagram which shows one example of backup alarm display
- FIG. 8 is a diagram which shows a flow of exhaustion level calculation and notification to a user
- FIG. 9 is a schematic configuration diagram of a memory system according to a third embodiment of the present invention.
- FIG. 10 is a diagram which illustrates each unit associated with exhaustion level calculation and alarm notification
- FIG. 11 is a diagram which shows one example of backup alarm display
- FIG. 12 is a diagram which shows a flow of exhaustion level calculation and notification to a user
- FIG. 13 is a schematic configuration diagram of a memory system according to a fourth embodiment of the present invention.
- FIG. 14 is a diagram which shows one example of backup alarm display
- FIG. 15 is a diagram which shows a flow of exhaustion level calculation and notification to a user
- FIG. 16 is a schematic configuration diagram of a memory system according to a fifth embodiment of the present invention.
- FIG. 17 is a diagram which shows one example of backup alarm display
- FIG. 18 is a diagram which shows a flow of exhaustion level calculation and notification to a user
- FIG. 19 is a graph which shows a relationship between the number of erase operations and data retention period
- FIG. 20 is a diagram which shows one example of backup alarm display.
- FIG. 21 is a graph which shows an ideal frequency of use.
- the FeRAM 2 has a counter (not shown), and for wear leveling, counts the number of erase operations in each block of the NAND type flash memory 1 as well as retaining a total of the number of erase operations. In addition, it retains a maximum number of erase operations and a threshold of exhaustion level of the NAND type flash memory 1 . The exhaustion level will be described later.
- the maximum number of erase operations is obtained here from (limiting number of store/erase operations in each block of the NAND type flash memory 1 ) ⁇ (total number of blocks of the NAND type flash memory 1 ).
- FeRAM 2 also has a function as a cache for high-speed reading/writing of the NAND type flash memory 1 .
- the controller 3 has the connection interface 31 , a processing unit (MPU) 32 , a FeRAM controller 33 , and a memory controller 34 .
- the FeRAM controller 33 controls transferring data retained by the FeRAM 2
- the memory controller 34 controls transferring data to the NAND type flash memory 1 .
- the memory controller 34 includes an error correction circuit (ECC) 35 .
- ECC error correction circuit
- the memory controller 34 can detect this error and correct it to a correct value.
- wear leveling is performed such that the number of store/erase operations in each block is averaged.
- a self-diagnosis command is regularly issued from the computer 4 to this memory system.
- the processing unit 32 receives the self-diagnosis command through the connection interface 31 , and performs control to output a total of the number of erase operations, a maximum number of erase operations, and a threshold of exhaustion level which are retained by the FeRAM 2 to the computer 4 through the connection interface 31 .
- the computer 4 calculates an exhaustion level of the NAND type flash memory 1 based on the total of the number of erase operations and the maximum number of erase operations.
- the exhaustion level is a ratio of the total of the number of erase operations to the maximum number of erase operations.
- the exhaustion level and a backup alarm are displayed on the display unit 5 as shown in FIG. 3( a ) so that a user is notified of them.
- the exhaustion level is calculated and displayed in percentage here.
- an alarm sound is emitted from the speaker 6 to give notification to the user.
- the user can optionally display the exhaustion level on the display unit 5 . If the exhaustion level is less than or equal to the threshold, the exhaustion level is displayed as shown in FIG. 3( b ).
- various representations may be used as a notification to a user. For example, it goes without saying that a circle graph, a line graph, various words and colors, and other indications can be used.
- FIG. 4 shows a process flow of calculation of an exhaustion level of the NAND type flash memory 1 and notification of the exhaustion level to a user.
- Step S 1 The processing unit 32 accepts a self-diagnosis command issued by the computer 4 .
- Step S 2 A total of the number of erase operations, the maximum number of erase operations, and a threshold of exhaustion level are retrieved from the FeRAM 2 and outputted to the computer 4 .
- Step S 3 The exhaustion level is calculated by the computer 4 .
- Step S 4 Whether or not the calculated exhaustion level is greater than the threshold is determined. If it is less than or equal to the threshold, the process is terminated. If it is greater than the threshold, the process proceeds to step S 5 .
- Step S 5 A backup alarm sound is emitted from the speaker 6 .
- Step S 6 The exhaustion level and a backup alarm are displayed on the display unit 5 .
- the step S 5 of emitting an alarm sound and the step S 6 of displaying an alarm may be replaced with each other.
- the exhaustion level is calculated from the total of the number of erase operations.
- an exhaustion level may be calculated from the number of erase operations in each block and a maximum number of erase operations.
- the numbers of rewrite operations are evenly distributed among blocks by wear leveling so that the number of rewrite operations with respect to a whole memory area is increased.
- a notification of an exhaustion level of the NAND type flash memory 1 can be provided to a user at any time. Backup is recommended when the exhaustion level exceeds a predetermined threshold and comes close to the end of a system lifetime, so that data loss can be prevented before it happens.
- a memory state such as an exhaustion level can be determined, and a memory can be efficiently used.
- FIG. 5 shows a schematic configuration of a memory system according to the second embodiment of the present invention.
- This memory system is configured to further include a timer 7 in addition to the memory system of the first embodiment shown in FIG. 1 .
- the timer 7 measures an energization time of this memory system. The measured energization time is retained in the FeRAM 2 .
- a self-diagnosis command is regularly issued from the computer 4 to this memory system.
- the processing unit 32 receives the self-diagnosis command through the connection interface 31 , and performs control to output a total of the number of erase operations, a maximum number of erase operations, and an energization time, and a remaining lifetime which are retained by the FeRAM 2 to the computer 4 through the connection interface 31 . The remaining lifetime will be described later.
- the computer 4 calculates an exhaustion level of the NAND type flash memory 1 based on the total of the number of erase operations and the maximum number of erase operations. Further, it calculates the remaining lifetime from the exhaustion level and the energization time.
- the exhaustion level is a ratio of the total of the number of erase operations to the maximum number of erase operations.
- the exhaustion level is calculated and displayed in percentage, and the remaining lifetime is calculated and displayed in units of days.
- an alarm sound may be emitted from the speaker 6 to give notification to the user.
- the user can optionally display the exhaustion level and the remaining lifetime on the display unit 5 .
- FIG. 8 shows a process flow of calculation of an exhaustion level and a lifetime of the NAND type flash memory 1 and notification of them to a user.
- Step S 11 The processing unit 32 accepts a self-diagnosis command issued by the computer 4 .
- Step S 12 A total of the number of erase operations, the maximum number of erase operations, an energization time, and a threshold of a remaining lifetime are retrieved from the FeRAM 2 and outputted to the computer 4 .
- Step S 13 The exhaustion level and the remaining lifetime are calculated by the computer 4 .
- Step S 14 Whether or not the calculated remaining lifetime is less than the threshold is determined. If it is greater than or equal to the threshold, the process is terminated. If it is less than the threshold, the process proceeds to step S 15 .
- Step S 15 A backup alarm sound is emitted from the speaker 6 .
- Step S 16 The exhaustion level, the remaining lifetime, and a backup alarm are displayed on the display unit 5 .
- the exhaustion level is calculated from the total of the number of erase operations.
- an exhaustion level may be calculated from the number of erase operations in each block and a maximum number of erase operations.
- the numbers of rewrite operations are evenly distributed among blocks by wear leveling so that the number of rewrite operations with respect to a whole memory area is increased.
- a notification of an exhaustion level of the NAND type flash memory 1 can be provided to a user at any time. Backup is recommended when the exhaustion level exceeds a predetermined threshold and comes close to the end of a system lifetime, so that data loss can be prevented before it happens. Further, a remaining lifetime is displayed, so that the user can replace a memory system in an efficient way.
- a memory state such as a remaining lifetime can be determined, and a memory can be efficiently used.
- FIG. 9 shows a schematic configuration of a memory system according to the third embodiment of the present invention.
- the memory system has a configuration similar to the first embodiment shown in FIG. 1 .
- an exhaustion level is calculated from a maximum number of erase operations and a total of the number of erase operations.
- an exhaustion level is calculated from an amount of writing into the NAND type flash memory 1 and an amount of reading therefrom.
- the FeRAM 2 has a management table of a capacity of access to the NAND type flash memory 1 , which retains an amount of writing, an amount of reading, and a threshold of an exhaustion level. In addition, it retains a limiting amount of writing of the NAND type flash memory 1 .
- a limiting amount of writing is defined as (a limiting number of store/erase operations in each block of the NAND type flash memory 1 ) ⁇ (a total capacity of the NAND type flash memory 1 ), multiplied by an efficiency of saving data as a weight, wherein the efficiency of saving data is an amount of erasing of the NAND type flash memory with respect to an amount of writing from the computer 4 , and is predicted by simulation.
- the limiting amount of writing may have a margin to allow a minimum backup, startup, shutdown, and the like.
- a self-diagnosis command is regularly issued from the computer 4 to this memory system.
- the processing unit 32 receives the self-diagnosis command through the connection interface 31 , and performs control to output an amount of writing, an amount of reading, a limiting amount of writing, and a threshold of exhaustion level which are retained by the FeRAM 2 to the computer 4 through the connection interface 31 .
- the computer 4 calculates an exhaustion level of the NAND type flash memory 1 based on the amount of writing, the amount of reading, and the limiting amount of writing.
- the exhaustion level (%) can be calculated as (amount of writing+amount of reading ⁇ “x”)/limiting amount of writing ⁇ 100, wherein “x” is derived from the number of read operations by which read disturb occurs. For example, in a case where read disturb is caused by 10 4 read operations, it is assumed that refresh occurs once with respect to an amount of reading which is a block capacity x 10 4 , and thus “x” can be set to 10 ⁇ 4 .
- the exhaustion level and a backup alarm are displayed on the display unit 5 as shown in FIG. 11 so that a user is notified of them.
- an alarm sound may be emitted from the speaker 6 to give notification to the user.
- the user can optionally display the exhaustion level on the display unit 5 .
- FIG. 12 shows a process flow of calculation of an exhaustion level of the NAND type flash memory 1 and notification of the exhaustion level to a user.
- Step S 21 The processing unit 32 accepts a self-diagnosis command issued by the computer 4 .
- Step S 22 A limiting amount of writing, an amount of reading, an amount of writing, and a threshold of exhaustion level are retrieved from the FeRAM 2 and outputted to the computer 4 .
- Step S 23 The exhaustion level is calculated by the computer 4 .
- Step S 24 Whether or not the calculated exhaustion level is greater than the threshold is determined. If it is less than or equal to the threshold, the process is terminated. If it is greater than the threshold, the process proceeds to step S 25 .
- Step S 25 The exhaustion level and a backup alarm are displayed on the display unit 5 .
- the numbers of rewrite operations are evenly distributed among blocks by wear leveling so that the number of rewrite operations with respect to a whole memory area is increased.
- a notification of an exhaustion level of the NAND type flash memory 1 can be provided to a user at any time. Backup is recommended when the exhaustion level exceeds a predetermined threshold and comes close to the end of a system lifetime, so that data loss can be prevented before it happens. Further, since refresh is also taken into account, the exhaustion level can be obtained more precisely.
- a memory state such as an exhaustion level can be determined, and a memory can be efficiently used.
- an exhaustion level is calculated using an amount of writing and an amount of reading in the present embodiment, an exhaustion level may be obtained from an amount of writing without use of an amount of reading.
- FIG. 13 shows a schematic configuration of a memory system according to the fourth embodiment of the present invention.
- the memory system has a configuration similar to the first embodiment shown in FIG. 1 .
- the memory system according to the first embodiment calculates an exhaustion level from the maximum number of erase operations and a total of the number of erase operations, and determines whether or not to display an alarm based on the exhaustion level, the number of error bits is considered in addition to an exhaustion level in the present embodiment.
- the FeRAM 2 has a counter (not shown), and counts the number of erase operations of the NAND type flash memory 1 and retains a total of the number of erase operations. In addition, it retains a maximum number of erase operations and a threshold of exhaustion level of the NAND type flash memory 1 .
- the maximum number of erase operations is obtained here from (limiting number of store/erase operations in each block of the NAND type flash memory 1 ) ⁇ (total number of blocks of the NAND type flash memory 1 ).
- the number of error bits in each block is managed, and the number of error bits in a block having a maximum number of error bits and a threshold of the number of error bits are retained. Since in the NAND type flash memory 1 , wear leveling is performed such that the number of write operations in each block is averaged, the number of error bits to be retained may be the number of error bits in any block.
- a self-diagnosis command is regularly issued from the computer 4 to this memory system.
- the processing unit 32 receives the self-diagnosis command through the connection interface 31 , and performs control to output a total of the number of erase operations, a maximum number of erase operations, the number of error bits, and each threshold which are retained by the FeRAM 2 to the computer 4 through the connection interface 31 .
- the computer 4 calculates an exhaustion level of the NAND type flash memory 1 based on the total of the number of erase operations and the maximum number of erase operations.
- this exhaustion level is greater than or equal to a predetermined threshold and the number of error bits is greater than or equal to a predetermined threshold
- the exhaustion level, a backup alarm, and a message to the effect that many errors have occurred are displayed on the display unit 5 as shown in FIG. 14( a ) so that a user is notified of them.
- FIG. 14( b ) only the exhaustion level and the backup alarm may be displayed.
- a degree of forcing of a backup alarm to be displayed may be increased in a stepwise manner depending on the case of “exhaustion level>threshold” or the case of “exhaustion level>threshold && the number of bits>threshold”.
- an alarm sound may be emitted from the speaker 6 to give notification to the user.
- FIG. 15 shows a process flow of calculation of an exhaustion level of the NAND type flash memory 1 and notification of the exhaustion level to a user.
- Step S 31 The processing unit 32 accepts a self-diagnosis command issued by the computer 4 .
- Step S 32 A total of the number of erase operations, the maximum number of erase operations, the number of error bits, and thresholds are retrieved from the FeRAM 2 and outputted to the computer 4 .
- Step S 33 The exhaustion level is calculated by the computer 4 .
- Step S 34 Whether or not the calculated exhaustion level is greater than a predetermined threshold and whether or not the number of error bits is greater than a predetermined threshold are determined. If both the exhaustion level and the number of error bits are greater than their thresholds, the process proceeds to step S 35 . If at least one of them is less than or equal to its threshold, the process is terminated.
- Step S 35 The exhaustion level and a backup alarm are displayed on the display unit 5 .
- the exhaustion level is calculated from the total of the number of erase operations.
- an exhaustion level may be calculated from the number of erase operations in each block and a maximum number of erase operations.
- the number of error bits in each block of the NAND type flash memory 1 may be monitored and retained in the FeRAM 2 , the number of blocks in which the number of error bits exceeds a predetermined threshold may be obtained by the computer 4 , and a degree of forcing of a backup alarm to be displayed may be increased in a stepwise manner according to the obtained number of blocks.
- the numbers of rewrite operations are evenly distributed among blocks by wear leveling so that the number of rewrite operations with respect to a whole memory area is increased.
- a notification of an exhaustion level of the NAND type flash memory 1 can be provided to a user at any time. Backup is recommended when the exhaustion level exceeds a predetermined threshold and comes close to the end of a system lifetime, so that data loss can be prevented before it happens. Further, since the number of error bits is also taken into account, timing for backup can be obtained more precisely.
- a memory state such as an exhaustion level can be determined, and a memory can be efficiently used.
- FIG. 16 shows a schematic configuration of a memory system according to the fifth embodiment of the present invention.
- This memory system is configured to further include a time counter 36 provided in the memory controller 34 of the memory system of the first embodiment shown in FIG. 1 .
- the time counter 36 measures times required for storing/erasing in the NAND type flash memory 1 (which are referred to as “t PROG ” and “t ERASE ” respectively).
- the measured “t PROG ” hu “t ERASE ” are retained in the FeRAM 2 .
- a verify operation for verifying whether data has been written or not is performed after data is stored (erased). If data has been incorrectly written, store (erase)/verify operations are repeated so that correct data is written.
- t PROG (“t ERASE ”) increases. In the present embodiment, these “t PROG ” and “t ERASE ” are taken into account in addition to an exhaustion level.
- a self-diagnosis command is regularly issued from the computer 4 to this memory system.
- the processing unit 32 receives the self-diagnosis command through the connection interface 31 , and performs control to output a total of the number of erase operations, a maximum number of erase operations, a storing time (“t PROG ”), an erasing time (“t ERASE ”), and each threshold which are retained by the FeRAM 2 to the computer 4 through the connection interface 31 .
- the computer 4 calculates an exhaustion level of the NAND type flash memory 1 based on the total of the number of erase operations and the maximum number of erase operations.
- the exhaustion level is greater than or equal to a predetermined threshold, and the storing time (“t PROG ”) and the erasing time (“t ERASE ”) are greater than or equal to respective predetermined thresholds, the exhaustion level, a backup alarm, and an error are displayed on the display unit 5 as shown in FIG. 17( a ) so that a user is notified of them. As shown in FIG. 17( b ), only the exhaustion level and the backup alarm may be displayed.
- a degree of forcing of a backup alarm to be displayed may be increased in a stepwise manner depending on the case of “exhaustion level>threshold” or the case of “exhaustion level>threshold && “t PROG ”/“t ERASE ”>threshold”. Further, an alarm sound may be emitted from the speaker 6 to give notification to the user.
- FIG. 18 shows a process flow of calculation of an exhaustion level of the NAND type flash memory 1 and notification of the exhaustion level to a user.
- Step S 41 The processing unit 32 accepts a self-diagnosis command issued by the computer 4 .
- Step S 42 A total of the number of erase operations, the maximum number of erase operations, a storing/erasing time (“t PROG ”/“t ERASE ”), and thresholds are retrieved from the FeRAM 2 and outputted to the computer 4 .
- Step S 43 The exhaustion level is calculated by the computer 4 .
- Step S 44 Whether or not the calculated exhaustion level is greater than a predetermined threshold and whether or not the storing/erasing time (“t PROG ”/“t ERASE ”) is greater than a predetermined threshold are determined. If both the exhaustion level and the storing/erasing time (“t PROG ”/“t ERASE ”) are greater than their thresholds, the process proceeds to step S 45 . If at least one of them is less than or equal to its threshold, the process is terminated.
- Step S 45 The exhaustion level and a backup alarm are displayed on the display unit 5 .
- the exhaustion level is calculated from the total of the number of erase operations.
- an exhaustion level may be calculated from the number of erase operations in each block and a maximum number of erase operations.
- the numbers of rewrite operations are evenly distributed among blocks by wear leveling so that the number of rewrite operations with respect to a whole memory area is increased.
- a notification of an exhaustion level of the NAND type flash memory 1 can be provided to a user at any time. Backup is recommended when the exhaustion level exceeds a predetermined threshold and comes close to the end of a system lifetime, so that data loss can be prevented before it happens. Further, since a time required for the verify operation is also taken into account, timing for backup can be obtained more precisely.
- a memory state such as an exhaustion level can be determined, and a memory can be efficiently used.
- a notification of a data retention period may be provided to a user.
- a data retention period based on the number of erase operations is determined from characteristics of the NAND type flash memory, and is retained in the FeRAM 2 .
- the data guarantee period passes over a line of five years, and therefore the computer 4 displays the data guarantee period and a backup alarm on the display unit 5 as shown in FIG.
- an ideal frequency of use which is determined from a maximum energization time and a limiting number of store/erase operations as shown in FIG. 21 may be compared with a user's frequency of use, and a notification that the memory has been used to an excessive degree may be provided to the user when the user's frequency of use exceeds the ideal frequency of use.
- the number of erase operations in each block, a maximum number of erase operations, a present energization time, and a maximum energization time are retained in the FeRAM 2 , and are outputted to the computer 4 when a self-diagnosis command is accepted.
- the number of write operations are varied depending on blocks, because an amount of writing is increased due to initialization and the like in an early use stage, or the numbers of write operations are not yet completely distributed in an even manner among blocks by wear leveling. For this reason, an alarm is not displayed even if an ideal frequency of use is exceeded when a total of the number of erase operations is small, and an alarm is displayed, for example, when the total of the number of erase operations becomes half or more of the limiting number of store/erase operations.
- an exhaustion level based on a total of the number of erase operations is calculated, but an exhaustion level based on an amount of writing and an amount of reading may be calculated as described in the third embodiment.
- the nonvolatile memory 2 in the memory system of the above described embodiments may be an MRAM, a PRAM, or an RRAM instead of the FeRAM. Or, it may be composed of a DRAM or SRAM, which is a volatile memory. However, if it is composed of a volatile memory, management information needs to be saved in the NAND type flash memory 1 , which is a nonvolatile memory, each time the memory system is powered off.
- a self-diagnosis command may be issued every time the computer 4 is started up.
Abstract
To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used.
The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.
Description
- This application is a continuation application of and claims the benefit of priority under 35 U.S.C. §120 for U.S. Ser. No. 12/513,860, filed May 7, 2009, pending, which is a National Stage application of PCT/JP2007/072898, filed Nov. 28, 2007, and claims benefit of priority under 35 U.S.C. §119 from JP 2006-322868, filed Nov. 30, 2006, the entire contents of each of which are incorporated herein by reference.
- The present invention relates to a memory system.
- In recent years, semiconductor memories have been used in various areas such as a main storage of a large-scale computer, a personal computer, a home electric appliance, a mobile phone, and the like. Particularly, a flash memory has such characteristics that data is not erased even if it is powered off, and it has a structure suitable for high integration, and used in information apparatuses such as a mobile phone and a digital camera.
- Types of Flash EEPROM nonvolatile memory are mainly an NOR type and an NAND type. As for the NOR type, a read rate is high, the number of read operations is about 1013, and it is used as an instruction code storage. However, the NOR type has a small effective bandwidth for writing, and therefore not suitable for file recording. As for the NAND type, although an access rate is low compared to the NOR type, high integration is allowed, a large number of bits can be stored or erased at the same time is large, and written data can be captured in burst and programming is allowed in page units having many bits. Therefore, the NAND type memory has a large effective bandwidth, and is used for a memory card, a USB memory, a memory of a mobile phone, a memory of a portable music player, and the like. Recently, it is also considered as a replacement of a hard disk (hereinafter referred to as an HDD).
- One problem in a case where the NAND type flash memory is as a replacement of an HDD is a problem of system lifetime. An HDD is equipped with a Self-Monitoring, Analysis and Reporting Technology (commonly known as SMART), which is a self-diagnosis function intended for early detection of a failure of the HDD itself and failure prediction, and thereby can notify a user of failure rate. Many of currently manufactured HDDs have this SMART, and predict a failure rate from items including a temperature, an operating time, a spin-up time, the number of alternate sectors (spare areas in which a sector causing bad data is arranged), and the like.
- If an NAND type flash memory is also considered to need reliability equivalent to HDDs, it requires a self-diagnosis function like SMART. However, reason of failure in the NAND type flash memory is different from that of the HDDs. Due to characteristics of recoding media of HDDs, they have no limit on the number of write operations, but is susceptible to heat. Further, since they are machine components, there is a problem of aged deterioration of mechanical operation. On the other hand, the NAND type flash memory has little machine components, but consideration should be given to a failure caused by bad data due to an excessive number of store/erase operations. Therefore, a new criterion of system lifetime is needed in consideration of the number of store/erase operations specific to the NAND type flash memory.
- A limit on the number of store/erase operations of the NAND type flash memory will be described. For writing (storing/erasing) in a flash memory, high voltage is applied between a substrate and a gate such that electrons are injected and released into a floating gate. If this is performed many times, gate oxide film around the floating gate is deteriorated, and if it is left as is for a long time, the electrons injected into the floating gate get out therefrom, and data is destroyed. In other words, as the number of write operations increases, retention characteristics degrade. The number of write operations of current flash memories is about 105, which is less than that of other nonvolatile memories. Therefore, if it is used as a replacement of an HDD, it is considered that data may be destroyed due to the limit of the number of store/erase operations, causing a trouble of the system. As a measure against such a limit on the number of store/erase operations, wear leveling is performed in which the number of erase operations is counted and a threshold value is set for each block, and physical address translation is performed between a block whose number of erase operations is large and a block whose number of erase operations is small, so that the numbers of store/erase operations are averaged.
- Limit on the number of store/erase operations affects not only writing but also reading. During reading from the NAND type flash memory, high voltage is repeatedly applied to a non-selected cell (in view of block units, all pages except a target to be read), causing read disturb in which electrons enter in the floating gate through the gate oxide film and thus change a threshold voltage of a cell so that data is destroyed. In addition, during use, the gate oxide film is degraded due to storing/erasing, and accordingly read disturb occurs more frequently. Recently, NAND type flash memories have been developed to have more advanced multivalued memorization in which more than one bit information is stored in one cell, and therefore the effect of the read disturb seems to be larger. To prevent such read disturb, it is required to perform rewriting in (refresh) a block whose number of read operations is large so as to return a threshold voltage to its original state, which affects the number of store/erase operations.
- There has been proposed a storage device which determines a memory state of a flash memory or the like, including: a memory having a main memory area and a spare memory area; display means; and processing means, wherein, when the number of rewrite operations in each address of the main memory area reaches a specified number, information stored in the address is transferred to the spare memory area; and when a remaining capacity of the spare memory area reaches a specified remaining capacity, the display means is driven to notify an operator or the like of a time to replace the memory (see, for example, Japanese Patent Laid-Open No. 2000-181805). However, in such a storage device, an end of memory lifetime for writing is determined to be reached and the memory is replaced in a state where the number of write operations in the spare memory area is still small. Therefore, the memory cannot be efficiently used.
- An object of the present invention is to provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used.
- A memory system according to one aspect of the present invention includes: a first memory in which data can be electrically written/erased; a second memory which counts the number of erase operations of the first memory and retains the number of erase operations and a maximum number of erase operations of the first memory; and a controller which is connected to be given a self-diagnosis command from an outside through a connection interface, and which retrieves the number of erase operations and the maximum number of erase operations from the second memory based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the outside through the connection interface.
- Further, a memory system according to one aspect of the present invention includes: a first memory in which data can be electrically written/erased; a second memory which monitors an amount of writing and an amount of reading with respect to the first memory, and retains the amount of writing, the amount of reading, and a limiting amount of writing based on a capacity of the first memory and a limiting number of write operations; and a controller which is connected to be given a self-diagnosis command from an outside through a connection interface, and which retrieves the amount of writing, the amount of reading, and the limiting amount of writing from the second memory based on the self-diagnosis command and outputs the amount of writing, the amount of reading, and the limiting amount of writing to the outside through the connection interface.
- According to the present invention, a memory state such as an exhaustion level can be determined, and a memory can be efficiently used.
-
FIG. 1 is a schematic configuration diagram of a memory system according to a first embodiment of the present invention; -
FIG. 2 is a diagram which illustrates operations of each unit associated with exhaustion level calculation and alarm notification; -
FIG. 3 is a diagram which shows one example of backup alarm display; -
FIG. 4 is a diagram which shows a flow of exhaustion level calculation and notification to a user; -
FIG. 5 is a schematic configuration diagram of a memory system according to a second embodiment of the present invention; -
FIG. 6 is a diagram which illustrates each unit associated with exhaustion level calculation and alarm notification; -
FIG. 7 is a diagram which shows one example of backup alarm display; -
FIG. 8 is a diagram which shows a flow of exhaustion level calculation and notification to a user; -
FIG. 9 is a schematic configuration diagram of a memory system according to a third embodiment of the present invention; -
FIG. 10 is a diagram which illustrates each unit associated with exhaustion level calculation and alarm notification; -
FIG. 11 is a diagram which shows one example of backup alarm display; -
FIG. 12 is a diagram which shows a flow of exhaustion level calculation and notification to a user; -
FIG. 13 is a schematic configuration diagram of a memory system according to a fourth embodiment of the present invention; -
FIG. 14 is a diagram which shows one example of backup alarm display; -
FIG. 15 is a diagram which shows a flow of exhaustion level calculation and notification to a user; -
FIG. 16 is a schematic configuration diagram of a memory system according to a fifth embodiment of the present invention; -
FIG. 17 is a diagram which shows one example of backup alarm display; -
FIG. 18 is a diagram which shows a flow of exhaustion level calculation and notification to a user; -
FIG. 19 is a graph which shows a relationship between the number of erase operations and data retention period; -
FIG. 20 is a diagram which shows one example of backup alarm display; and -
FIG. 21 is a graph which shows an ideal frequency of use. - Hereinafter, a memory system according to embodiments of the present invention will be described based on the drawings.
- The
FeRAM 2 has a counter (not shown), and for wear leveling, counts the number of erase operations in each block of the NANDtype flash memory 1 as well as retaining a total of the number of erase operations. In addition, it retains a maximum number of erase operations and a threshold of exhaustion level of the NANDtype flash memory 1. The exhaustion level will be described later. The maximum number of erase operations is obtained here from (limiting number of store/erase operations in each block of the NAND type flash memory 1)×(total number of blocks of the NAND type flash memory 1). In addition,FeRAM 2 also has a function as a cache for high-speed reading/writing of the NANDtype flash memory 1. - The
controller 3 has theconnection interface 31, a processing unit (MPU) 32, aFeRAM controller 33, and amemory controller 34. TheFeRAM controller 33 controls transferring data retained by theFeRAM 2, and thememory controller 34 controls transferring data to the NANDtype flash memory 1. In addition, thememory controller 34 includes an error correction circuit (ECC) 35. When an incorrect value is stored in the NANDtype flash memory 1, thememory controller 34 can detect this error and correct it to a correct value. In the NANDtype flash memory 1, wear leveling is performed such that the number of store/erase operations in each block is averaged. - As shown in
FIG. 2 , a self-diagnosis command is regularly issued from thecomputer 4 to this memory system. Theprocessing unit 32 receives the self-diagnosis command through theconnection interface 31, and performs control to output a total of the number of erase operations, a maximum number of erase operations, and a threshold of exhaustion level which are retained by theFeRAM 2 to thecomputer 4 through theconnection interface 31. Thecomputer 4 calculates an exhaustion level of the NANDtype flash memory 1 based on the total of the number of erase operations and the maximum number of erase operations. The exhaustion level is a ratio of the total of the number of erase operations to the maximum number of erase operations. If this exhaustion level is greater than or equal to the threshold, the exhaustion level and a backup alarm are displayed on thedisplay unit 5 as shown inFIG. 3( a) so that a user is notified of them. The exhaustion level is calculated and displayed in percentage here. In addition, an alarm sound is emitted from thespeaker 6 to give notification to the user. In addition, the user can optionally display the exhaustion level on thedisplay unit 5. If the exhaustion level is less than or equal to the threshold, the exhaustion level is displayed as shown inFIG. 3( b). Of course, various representations may be used as a notification to a user. For example, it goes without saying that a circle graph, a line graph, various words and colors, and other indications can be used. -
FIG. 4 shows a process flow of calculation of an exhaustion level of the NANDtype flash memory 1 and notification of the exhaustion level to a user. - (Step S1) The
processing unit 32 accepts a self-diagnosis command issued by thecomputer 4. - (Step S2) A total of the number of erase operations, the maximum number of erase operations, and a threshold of exhaustion level are retrieved from the
FeRAM 2 and outputted to thecomputer 4. - (Step S3) The exhaustion level is calculated by the
computer 4. - (Step S4) Whether or not the calculated exhaustion level is greater than the threshold is determined. If it is less than or equal to the threshold, the process is terminated. If it is greater than the threshold, the process proceeds to step S5.
- (Step S5) A backup alarm sound is emitted from the
speaker 6. - (Step S6) The exhaustion level and a backup alarm are displayed on the
display unit 5. The step S5 of emitting an alarm sound and the step S6 of displaying an alarm may be replaced with each other. - In the above description, the exhaustion level is calculated from the total of the number of erase operations. However, since the number of erase operations in each block is averaged by wear leveling, an exhaustion level may be calculated from the number of erase operations in each block and a maximum number of erase operations.
- In the NAND
type flash memory 1, the numbers of rewrite operations are evenly distributed among blocks by wear leveling so that the number of rewrite operations with respect to a whole memory area is increased. A notification of an exhaustion level of the NANDtype flash memory 1 can be provided to a user at any time. Backup is recommended when the exhaustion level exceeds a predetermined threshold and comes close to the end of a system lifetime, so that data loss can be prevented before it happens. - As described above, according to the memory system of the first embodiment, a memory state such as an exhaustion level can be determined, and a memory can be efficiently used.
-
FIG. 5 shows a schematic configuration of a memory system according to the second embodiment of the present invention. This memory system is configured to further include atimer 7 in addition to the memory system of the first embodiment shown inFIG. 1 . Thetimer 7 measures an energization time of this memory system. The measured energization time is retained in theFeRAM 2. - As shown in
FIG. 6 , a self-diagnosis command is regularly issued from thecomputer 4 to this memory system. Theprocessing unit 32 receives the self-diagnosis command through theconnection interface 31, and performs control to output a total of the number of erase operations, a maximum number of erase operations, and an energization time, and a remaining lifetime which are retained by theFeRAM 2 to thecomputer 4 through theconnection interface 31. The remaining lifetime will be described later. - The
computer 4 calculates an exhaustion level of the NANDtype flash memory 1 based on the total of the number of erase operations and the maximum number of erase operations. Further, it calculates the remaining lifetime from the exhaustion level and the energization time. The exhaustion level is a ratio of the total of the number of erase operations to the maximum number of erase operations. A remaining lifetime is represented as (100−exhaustion level)/exhaustion level×energization time. For example, when maximum number of erase operations=1,000,000, total of the number of erase operations=990,000, and energization time=9,900 hours, remaining lifetime equals 100 hours. - If the remaining lifetime is less than a predetermined threshold, the exhaustion level, the remaining lifetime, and a backup alarm are displayed on the
display unit 5 as shown inFIG. 7 so that a user is notified of them. The exhaustion level is calculated and displayed in percentage, and the remaining lifetime is calculated and displayed in units of days. In addition, an alarm sound may be emitted from thespeaker 6 to give notification to the user. In addition, the user can optionally display the exhaustion level and the remaining lifetime on thedisplay unit 5. -
FIG. 8 shows a process flow of calculation of an exhaustion level and a lifetime of the NANDtype flash memory 1 and notification of them to a user. - (Step S11) The
processing unit 32 accepts a self-diagnosis command issued by thecomputer 4. - (Step S12) A total of the number of erase operations, the maximum number of erase operations, an energization time, and a threshold of a remaining lifetime are retrieved from the
FeRAM 2 and outputted to thecomputer 4. - (Step S13) The exhaustion level and the remaining lifetime are calculated by the
computer 4. - (Step S14) Whether or not the calculated remaining lifetime is less than the threshold is determined. If it is greater than or equal to the threshold, the process is terminated. If it is less than the threshold, the process proceeds to step S15.
- (Step S15) A backup alarm sound is emitted from the
speaker 6. - (Step S16) The exhaustion level, the remaining lifetime, and a backup alarm are displayed on the
display unit 5. - In the above description, the exhaustion level is calculated from the total of the number of erase operations. However, since the number of erase operations in each block is averaged by wear leveling, an exhaustion level may be calculated from the number of erase operations in each block and a maximum number of erase operations.
- In the NAND
type flash memory 1, the numbers of rewrite operations are evenly distributed among blocks by wear leveling so that the number of rewrite operations with respect to a whole memory area is increased. A notification of an exhaustion level of the NANDtype flash memory 1 can be provided to a user at any time. Backup is recommended when the exhaustion level exceeds a predetermined threshold and comes close to the end of a system lifetime, so that data loss can be prevented before it happens. Further, a remaining lifetime is displayed, so that the user can replace a memory system in an efficient way. - As described above, according to the memory system of the second embodiment, a memory state such as a remaining lifetime can be determined, and a memory can be efficiently used.
-
FIG. 9 shows a schematic configuration of a memory system according to the third embodiment of the present invention. The memory system has a configuration similar to the first embodiment shown inFIG. 1 . In the memory system according to the first embodiment, an exhaustion level is calculated from a maximum number of erase operations and a total of the number of erase operations. However, in the present embodiment, an exhaustion level is calculated from an amount of writing into the NANDtype flash memory 1 and an amount of reading therefrom. - The
FeRAM 2 has a management table of a capacity of access to the NANDtype flash memory 1, which retains an amount of writing, an amount of reading, and a threshold of an exhaustion level. In addition, it retains a limiting amount of writing of the NANDtype flash memory 1. As used herein, a limiting amount of writing is defined as (a limiting number of store/erase operations in each block of the NAND type flash memory 1)×(a total capacity of the NAND type flash memory 1), multiplied by an efficiency of saving data as a weight, wherein the efficiency of saving data is an amount of erasing of the NAND type flash memory with respect to an amount of writing from thecomputer 4, and is predicted by simulation. The limiting amount of writing may have a margin to allow a minimum backup, startup, shutdown, and the like. - As shown in
FIG. 10 , a self-diagnosis command is regularly issued from thecomputer 4 to this memory system. Theprocessing unit 32 receives the self-diagnosis command through theconnection interface 31, and performs control to output an amount of writing, an amount of reading, a limiting amount of writing, and a threshold of exhaustion level which are retained by theFeRAM 2 to thecomputer 4 through theconnection interface 31. Thecomputer 4 calculates an exhaustion level of the NANDtype flash memory 1 based on the amount of writing, the amount of reading, and the limiting amount of writing. - The exhaustion level (%) can be calculated as (amount of writing+amount of readingדx”)/limiting amount of writing×100, wherein “x” is derived from the number of read operations by which read disturb occurs. For example, in a case where read disturb is caused by 104 read operations, it is assumed that refresh occurs once with respect to an amount of reading which is a block capacity x 104, and thus “x” can be set to 10−4.
- If this exhaustion level is greater than or equal to the threshold, the exhaustion level and a backup alarm are displayed on the
display unit 5 as shown inFIG. 11 so that a user is notified of them. In addition, an alarm sound may be emitted from thespeaker 6 to give notification to the user. In addition, the user can optionally display the exhaustion level on thedisplay unit 5. -
FIG. 12 shows a process flow of calculation of an exhaustion level of the NANDtype flash memory 1 and notification of the exhaustion level to a user. - (Step S21) The
processing unit 32 accepts a self-diagnosis command issued by thecomputer 4. - (Step S22) A limiting amount of writing, an amount of reading, an amount of writing, and a threshold of exhaustion level are retrieved from the
FeRAM 2 and outputted to thecomputer 4. - (Step S23) The exhaustion level is calculated by the
computer 4. - (Step S24) Whether or not the calculated exhaustion level is greater than the threshold is determined. If it is less than or equal to the threshold, the process is terminated. If it is greater than the threshold, the process proceeds to step S25.
- (Step S25) The exhaustion level and a backup alarm are displayed on the
display unit 5. - In the NAND
type flash memory 1, the numbers of rewrite operations are evenly distributed among blocks by wear leveling so that the number of rewrite operations with respect to a whole memory area is increased. A notification of an exhaustion level of the NANDtype flash memory 1 can be provided to a user at any time. Backup is recommended when the exhaustion level exceeds a predetermined threshold and comes close to the end of a system lifetime, so that data loss can be prevented before it happens. Further, since refresh is also taken into account, the exhaustion level can be obtained more precisely. - As described above, according to the memory system of the third embodiment, a memory state such as an exhaustion level can be determined, and a memory can be efficiently used.
- Although an exhaustion level is calculated using an amount of writing and an amount of reading in the present embodiment, an exhaustion level may be obtained from an amount of writing without use of an amount of reading.
-
FIG. 13 shows a schematic configuration of a memory system according to the fourth embodiment of the present invention. The memory system has a configuration similar to the first embodiment shown inFIG. 1 . Although the memory system according to the first embodiment calculates an exhaustion level from the maximum number of erase operations and a total of the number of erase operations, and determines whether or not to display an alarm based on the exhaustion level, the number of error bits is considered in addition to an exhaustion level in the present embodiment. - The
FeRAM 2 has a counter (not shown), and counts the number of erase operations of the NANDtype flash memory 1 and retains a total of the number of erase operations. In addition, it retains a maximum number of erase operations and a threshold of exhaustion level of the NANDtype flash memory 1. The maximum number of erase operations is obtained here from (limiting number of store/erase operations in each block of the NAND type flash memory 1)×(total number of blocks of the NAND type flash memory 1). In addition, the number of error bits in each block is managed, and the number of error bits in a block having a maximum number of error bits and a threshold of the number of error bits are retained. Since in the NANDtype flash memory 1, wear leveling is performed such that the number of write operations in each block is averaged, the number of error bits to be retained may be the number of error bits in any block. - A self-diagnosis command is regularly issued from the
computer 4 to this memory system. Theprocessing unit 32 receives the self-diagnosis command through theconnection interface 31, and performs control to output a total of the number of erase operations, a maximum number of erase operations, the number of error bits, and each threshold which are retained by theFeRAM 2 to thecomputer 4 through theconnection interface 31. Thecomputer 4 calculates an exhaustion level of the NANDtype flash memory 1 based on the total of the number of erase operations and the maximum number of erase operations. - If this exhaustion level is greater than or equal to a predetermined threshold and the number of error bits is greater than or equal to a predetermined threshold, the exhaustion level, a backup alarm, and a message to the effect that many errors have occurred are displayed on the
display unit 5 as shown inFIG. 14( a) so that a user is notified of them. As shown inFIG. 14( b), only the exhaustion level and the backup alarm may be displayed. Further, a degree of forcing of a backup alarm to be displayed may be increased in a stepwise manner depending on the case of “exhaustion level>threshold” or the case of “exhaustion level>threshold && the number of bits>threshold”. Further, an alarm sound may be emitted from thespeaker 6 to give notification to the user. -
FIG. 15 shows a process flow of calculation of an exhaustion level of the NANDtype flash memory 1 and notification of the exhaustion level to a user. - (Step S31) The
processing unit 32 accepts a self-diagnosis command issued by thecomputer 4. - (Step S32) A total of the number of erase operations, the maximum number of erase operations, the number of error bits, and thresholds are retrieved from the
FeRAM 2 and outputted to thecomputer 4. - (Step S33) The exhaustion level is calculated by the
computer 4. - (Step S34) Whether or not the calculated exhaustion level is greater than a predetermined threshold and whether or not the number of error bits is greater than a predetermined threshold are determined. If both the exhaustion level and the number of error bits are greater than their thresholds, the process proceeds to step S35. If at least one of them is less than or equal to its threshold, the process is terminated.
- (Step S35) The exhaustion level and a backup alarm are displayed on the
display unit 5. - In the above description, the exhaustion level is calculated from the total of the number of erase operations. However, since the number of erase operations in each block is averaged by wear leveling, an exhaustion level may be calculated from the number of erase operations in each block and a maximum number of erase operations.
- The number of error bits in each block of the NAND
type flash memory 1 may be monitored and retained in theFeRAM 2, the number of blocks in which the number of error bits exceeds a predetermined threshold may be obtained by thecomputer 4, and a degree of forcing of a backup alarm to be displayed may be increased in a stepwise manner according to the obtained number of blocks. - In the NAND
type flash memory 1, the numbers of rewrite operations are evenly distributed among blocks by wear leveling so that the number of rewrite operations with respect to a whole memory area is increased. A notification of an exhaustion level of the NANDtype flash memory 1 can be provided to a user at any time. Backup is recommended when the exhaustion level exceeds a predetermined threshold and comes close to the end of a system lifetime, so that data loss can be prevented before it happens. Further, since the number of error bits is also taken into account, timing for backup can be obtained more precisely. - As described above, according to the memory system of the fourth embodiment, a memory state such as an exhaustion level can be determined, and a memory can be efficiently used.
-
FIG. 16 shows a schematic configuration of a memory system according to the fifth embodiment of the present invention. This memory system is configured to further include atime counter 36 provided in thememory controller 34 of the memory system of the first embodiment shown inFIG. 1 . The time counter 36 measures times required for storing/erasing in the NAND type flash memory 1 (which are referred to as “tPROG” and “tERASE” respectively). The measured “tPROG” hu “tERASE” are retained in theFeRAM 2. - During a store (erase) operation of the NAND type flash memory, a verify operation for verifying whether data has been written or not is performed after data is stored (erased). If data has been incorrectly written, store (erase)/verify operations are repeated so that correct data is written. As a fatigue level of the NAND type flash memory increases (an exhaustion level increase), the number of store (erase)/verify operations increases, and with it, “tPROG” (“tERASE”) increases. In the present embodiment, these “tPROG” and “tERASE” are taken into account in addition to an exhaustion level.
- A self-diagnosis command is regularly issued from the
computer 4 to this memory system. Theprocessing unit 32 receives the self-diagnosis command through theconnection interface 31, and performs control to output a total of the number of erase operations, a maximum number of erase operations, a storing time (“tPROG”), an erasing time (“tERASE”), and each threshold which are retained by theFeRAM 2 to thecomputer 4 through theconnection interface 31. Thecomputer 4 calculates an exhaustion level of the NANDtype flash memory 1 based on the total of the number of erase operations and the maximum number of erase operations. - If this exhaustion level is greater than or equal to a predetermined threshold, and the storing time (“tPROG”) and the erasing time (“tERASE”) are greater than or equal to respective predetermined thresholds, the exhaustion level, a backup alarm, and an error are displayed on the
display unit 5 as shown inFIG. 17( a) so that a user is notified of them. As shown inFIG. 17( b), only the exhaustion level and the backup alarm may be displayed. Further, a degree of forcing of a backup alarm to be displayed may be increased in a stepwise manner depending on the case of “exhaustion level>threshold” or the case of “exhaustion level>threshold && “tPROG”/“tERASE”>threshold”. Further, an alarm sound may be emitted from thespeaker 6 to give notification to the user. -
FIG. 18 shows a process flow of calculation of an exhaustion level of the NANDtype flash memory 1 and notification of the exhaustion level to a user. - (Step S41) The
processing unit 32 accepts a self-diagnosis command issued by thecomputer 4. - (Step S42) A total of the number of erase operations, the maximum number of erase operations, a storing/erasing time (“tPROG”/“tERASE”), and thresholds are retrieved from the
FeRAM 2 and outputted to thecomputer 4. - (Step S43) The exhaustion level is calculated by the
computer 4. - (Step S44) Whether or not the calculated exhaustion level is greater than a predetermined threshold and whether or not the storing/erasing time (“tPROG”/“tERASE”) is greater than a predetermined threshold are determined. If both the exhaustion level and the storing/erasing time (“tPROG”/“tERASE”) are greater than their thresholds, the process proceeds to step S45. If at least one of them is less than or equal to its threshold, the process is terminated.
- (Step S45) The exhaustion level and a backup alarm are displayed on the
display unit 5. - It has been described that the exhaustion level is calculated from the total of the number of erase operations. However, since the number of erase operations in each block is averaged by wear leveling, an exhaustion level may be calculated from the number of erase operations in each block and a maximum number of erase operations.
- In the NAND
type flash memory 1, the numbers of rewrite operations are evenly distributed among blocks by wear leveling so that the number of rewrite operations with respect to a whole memory area is increased. A notification of an exhaustion level of the NANDtype flash memory 1 can be provided to a user at any time. Backup is recommended when the exhaustion level exceeds a predetermined threshold and comes close to the end of a system lifetime, so that data loss can be prevented before it happens. Further, since a time required for the verify operation is also taken into account, timing for backup can be obtained more precisely. - As described above, according to the memory system of the fifth embodiment, a memory state such as an exhaustion level can be determined, and a memory can be efficiently used.
- Any of the above described embodiments is just one example, and should not be considered to be restrictive. For example, when the number of erase operations of the NAND
type flash memory 1 exceeds a limiting number of erase operations, a notification of a data retention period (a data guarantee period) may be provided to a user. As shown inFIG. 19 , a data retention period based on the number of erase operations is determined from characteristics of the NAND type flash memory, and is retained in theFeRAM 2. When the number of erase operations in each block of the NANDtype flash memory 1 which is being monitored by theFeRAM 2 becomes 400, the data guarantee period passes over a line of five years, and therefore thecomputer 4 displays the data guarantee period and a backup alarm on thedisplay unit 5 as shown inFIG. 20( a) so that a user is notified of them. When the number of erase operations becomes 450 after further writing, the data guarantee period passes over a line of four years, and therefore the data guarantee period is made shorter and displayed as four years as shown inFIG. 20( b) so that the user is notified of it. Thereby, a notification that possibility of data loss has been increased is provided to the user, and reliability of the memory system can be improved. Although it has been described that a data guarantee period according to the number of erase operations in each block is displayed, a data guarantee period may be displayed based on a total of the number of erase operations. - Further, in the second embodiment, an ideal frequency of use which is determined from a maximum energization time and a limiting number of store/erase operations as shown in
FIG. 21 may be compared with a user's frequency of use, and a notification that the memory has been used to an excessive degree may be provided to the user when the user's frequency of use exceeds the ideal frequency of use. The number of erase operations in each block, a maximum number of erase operations, a present energization time, and a maximum energization time are retained in theFeRAM 2, and are outputted to thecomputer 4 when a self-diagnosis command is accepted. The number of write operations are varied depending on blocks, because an amount of writing is increased due to initialization and the like in an early use stage, or the numbers of write operations are not yet completely distributed in an even manner among blocks by wear leveling. For this reason, an alarm is not displayed even if an ideal frequency of use is exceeded when a total of the number of erase operations is small, and an alarm is displayed, for example, when the total of the number of erase operations becomes half or more of the limiting number of store/erase operations. - In the fourth and fifth embodiments, an exhaustion level based on a total of the number of erase operations is calculated, but an exhaustion level based on an amount of writing and an amount of reading may be calculated as described in the third embodiment.
- The
nonvolatile memory 2 in the memory system of the above described embodiments may be an MRAM, a PRAM, or an RRAM instead of the FeRAM. Or, it may be composed of a DRAM or SRAM, which is a volatile memory. However, if it is composed of a volatile memory, management information needs to be saved in the NANDtype flash memory 1, which is a nonvolatile memory, each time the memory system is powered off. - A self-diagnosis command may be issued every time the
computer 4 is started up.
Claims (17)
1. A memory system comprising:
a first memory in which data can be electrically written/erased;
a second memory which retains a number of erase operations and a maximum number of erase operations of the first memory; and
a controller configured to receive a self-diagnosis command through a connection interface, and retrieve the number of erase operations and the maximum number of erase operations from the second memory in response to receiving self-diagnosis command and output the number of erase operations and the maximum number of erase operations and threshold of an exhaustion level through the connection interface.
2. The memory system according to claim 1 , wherein the threshold of an exhaustion level is calculated by division of the number of erase operations by the maximum number of erase operations.
3. The memory system according to claim 1 , wherein the second memory retains data guarantee period information of the first memory associated with the number of erase operations, and the controller outputs the data guarantee period information in response to receiving the self-diagnosis command.
4. The memory system according to claim 1 , wherein the second memory is non-volatile random access memory.
5. The memory system according to claim 1 , wherein the number of erase operations of the first memory is retained for each block of the first memory.
6. A memory system comprising:
a first memory in which data can be electrically written/erased;
a second memory which counts the number of erase operations of the first memory and retains the number of erase operations and a maximum number of erase operations of the first memory;
a timer configured to measure an operation time; and
a controller configured to receive a self-diagnosis command through a connection interface, and retrieve from the second memory in response to receiving self-diagnosis command and output the number of erase operations, the maximum number of erase operations, operation time and threshold of remaining lifetime through the connection interface.
7. The memory system according to claim 6 , wherein the second memory further retinas a maximum operating time of the first memory, and the controller further outputs the maximum operating time in response to the self-diagnosis command.
8. The memory system according to claim 6 , wherein the second memory is non-volatile random access memory.
9. The memory system according to claim 6 , wherein a number of erase operations of the first memory is retained for each block of the first memory.
10. A memory system comprising:
a memory in which data can be electrically written/erased;
a controller configured to receive a self-diagnosis command through a connection interface, and output a number of erase operations, a maximum number of erase operations, and threshold of an exhaustion level of the memory through the connection interface in response to receiving self-diagnosis command.
11. The memory system according to claim 10 , wherein further comprising a second memory which retain the number of erase operations and the maximum number of erase operations of the first memory.
12. The memory system according to claim 11 , wherein the second memory is non-volatile random access memory.
13. The memory system according to claim 10 , wherein the threshold of an exhaustion level is calculated by division of the number of erase operations by the maximum number of erase operations.
14. A system comprising:
a host device;
a memory system electronically connected to the host device;
the memory system comprising;
a command interface configured to receive self-diagnosis command from the host device
a memory in which data can be electrically written/erased;
a controller configured to receive a self-diagnosis command through a connection interface, and output a number of erase operations, a maximum number of erase operations, and threshold of an exhaustion level of the memory through the connection interface in response to receiving self-diagnosis command.
15. The system according to claim 14 , wherein the host device calculate an exhaustion level based on the number of erase operations and the maximum number of erase operation of the memory, and determine if the calculated exhaustion level is greater than threshold of an exhaustion level.
16. The system according to claim 15 , wherein the host device output alarm signal if the calculation exhaustion level is greater than the threshold of an exhaustion level.
17. The system according to claim 15 , wherein the host device further comprising the display, and the host device displays the exhaustion level of the first memory on the display.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/426,696 US20120179942A1 (en) | 2006-11-30 | 2012-03-22 | Memory system |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006322868A JP4575346B2 (en) | 2006-11-30 | 2006-11-30 | Memory system |
JP2006-322868 | 2006-11-30 | ||
PCT/JP2007/072898 WO2008066058A1 (en) | 2006-11-30 | 2007-11-28 | Memory system |
US51386009A | 2009-05-07 | 2009-05-07 | |
US13/426,696 US20120179942A1 (en) | 2006-11-30 | 2012-03-22 | Memory system |
Related Parent Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2007/072898 Continuation WO2008066058A1 (en) | 2006-11-30 | 2007-11-28 | Memory system |
US51386009A Continuation | 2006-11-30 | 2009-05-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
US20120179942A1 true US20120179942A1 (en) | 2012-07-12 |
Family
ID=39467848
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/249,070 Active 2028-04-28 USRE47946E1 (en) | 2006-11-30 | 2007-11-28 | Method for determining the exhaustion level of semiconductor memory |
US12/513,860 Ceased US8156393B2 (en) | 2006-11-30 | 2007-11-28 | Memory system |
US13/426,696 Abandoned US20120179942A1 (en) | 2006-11-30 | 2012-03-22 | Memory system |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/249,070 Active 2028-04-28 USRE47946E1 (en) | 2006-11-30 | 2007-11-28 | Method for determining the exhaustion level of semiconductor memory |
US12/513,860 Ceased US8156393B2 (en) | 2006-11-30 | 2007-11-28 | Memory system |
Country Status (8)
Country | Link |
---|---|
US (3) | USRE47946E1 (en) |
EP (1) | EP2088512B1 (en) |
JP (1) | JP4575346B2 (en) |
KR (1) | KR101079502B1 (en) |
CN (2) | CN104699546A (en) |
AT (1) | ATE546782T1 (en) |
TW (1) | TW200834581A (en) |
WO (1) | WO2008066058A1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130262942A1 (en) * | 2012-03-27 | 2013-10-03 | Yung-Chiang Chu | Flash memory lifetime evaluation method |
CN103559115A (en) * | 2013-09-29 | 2014-02-05 | 记忆科技(深圳)有限公司 | SSD intelligent monitoring system based on SMART |
US10254982B2 (en) * | 2016-11-10 | 2019-04-09 | Western Digital Technologies, Inc. | System and methodology for low latency error management within a shared non-volatile memory architecture |
US10514867B2 (en) | 2016-11-10 | 2019-12-24 | Western Digital Technologies, Inc. | System and methodology that facilitates error management within a shared non-volatile memory architecture |
Families Citing this family (75)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7653778B2 (en) * | 2006-05-08 | 2010-01-26 | Siliconsystems, Inc. | Systems and methods for measuring the useful life of solid-state storage devices |
US8549236B2 (en) * | 2006-12-15 | 2013-10-01 | Siliconsystems, Inc. | Storage subsystem with multiple non-volatile memory arrays to protect against data losses |
KR20090000192A (en) * | 2007-01-29 | 2009-01-07 | 삼성전자주식회사 | Electronic system informing the term of validity and/ or endurance data and method thereof |
US7596643B2 (en) * | 2007-02-07 | 2009-09-29 | Siliconsystems, Inc. | Storage subsystem with configurable buffer |
JP5073402B2 (en) * | 2007-07-31 | 2012-11-14 | パナソニック株式会社 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE USING THE SAME, AND NONVOLATILE MEMORY SYSTEM |
JP4533968B2 (en) | 2007-12-28 | 2010-09-01 | 株式会社東芝 | Semiconductor memory device, control method therefor, controller, information processing device |
JP4461170B2 (en) | 2007-12-28 | 2010-05-12 | 株式会社東芝 | Memory system |
US8078918B2 (en) * | 2008-02-07 | 2011-12-13 | Siliconsystems, Inc. | Solid state storage subsystem that maintains and provides access to data reflective of a failure risk |
US7962792B2 (en) * | 2008-02-11 | 2011-06-14 | Siliconsystems, Inc. | Interface for enabling a host computer to retrieve device monitor data from a solid state storage subsystem |
JP4439569B2 (en) * | 2008-04-24 | 2010-03-24 | 株式会社東芝 | Memory system |
JP4683438B2 (en) * | 2008-06-13 | 2011-05-18 | 讀賣テレビ放送株式会社 | Data broadcasting system, data broadcasting method and program |
CN101625901A (en) * | 2008-07-10 | 2010-01-13 | 深圳市朗科科技股份有限公司 | Method for prewarning service life of semiconductor storage medium and system and device using same |
US8140739B2 (en) * | 2008-08-08 | 2012-03-20 | Imation Corp. | Flash memory based storage devices utilizing magnetoresistive random access memory (MRAM) to store files having logical block addresses stored in a write frequency file buffer table |
JP5319985B2 (en) * | 2008-08-22 | 2013-10-16 | 株式会社バッファローメモリ | Storage device use limit prediction method, use limit prediction device or use limit prediction time analysis program |
JP2010061578A (en) * | 2008-09-05 | 2010-03-18 | Jds:Kk | Program or system for use limit estimation analysis of semiconductor storage device |
KR101038167B1 (en) | 2008-09-09 | 2011-05-31 | 가부시끼가이샤 도시바 | Information processing device including memory management device managing access from processor to memory and memory management method |
JP4575484B2 (en) | 2008-09-26 | 2010-11-04 | 株式会社東芝 | Storage device and storage device control method |
US20100125696A1 (en) * | 2008-11-17 | 2010-05-20 | Prasanth Kumar | Memory Controller For Controlling The Wear In A Non-volatile Memory Device And A Method Of Operation Therefor |
US20100199020A1 (en) * | 2009-02-04 | 2010-08-05 | Silicon Storage Technology, Inc. | Non-volatile memory subsystem and a memory controller therefor |
JP5268710B2 (en) * | 2009-02-27 | 2013-08-21 | 株式会社東芝 | Semiconductor memory device |
JP4843693B2 (en) * | 2009-03-30 | 2011-12-21 | 株式会社東芝 | Storage device |
US8219776B2 (en) * | 2009-09-23 | 2012-07-10 | Lsi Corporation | Logical-to-physical address translation for solid state disks |
US8166258B2 (en) * | 2009-07-24 | 2012-04-24 | Lsi Corporation | Skip operations for solid state disks |
US8245112B2 (en) * | 2009-06-04 | 2012-08-14 | Lsi Corporation | Flash memory organization |
US8321639B2 (en) * | 2009-12-30 | 2012-11-27 | Lsi Corporation | Command tracking for direct access block storage devices |
US8296480B2 (en) * | 2009-11-30 | 2012-10-23 | Lsi Corporation | Context execution in a media controller architecture |
US20100306451A1 (en) * | 2009-06-01 | 2010-12-02 | Joshua Johnson | Architecture for nand flash constraint enforcement |
US8516264B2 (en) * | 2009-10-09 | 2013-08-20 | Lsi Corporation | Interlocking plain text passwords to data encryption keys |
US8555141B2 (en) * | 2009-06-04 | 2013-10-08 | Lsi Corporation | Flash memory organization |
US7975193B2 (en) * | 2009-06-01 | 2011-07-05 | Lsi Corporation | Solid state storage end of life prediction with correction history |
JP2011186553A (en) * | 2010-03-04 | 2011-09-22 | Toshiba Corp | Memory management device |
JP2011070346A (en) * | 2009-09-25 | 2011-04-07 | Toshiba Corp | Memory system |
CN102597906B (en) * | 2009-11-06 | 2016-02-03 | 飞思卡尔半导体公司 | To the response of the loss in electron device |
JP4762342B2 (en) * | 2009-12-25 | 2011-08-31 | 株式会社東芝 | Recording control apparatus and recording control method |
JP2011164994A (en) | 2010-02-10 | 2011-08-25 | Toshiba Corp | Memory system |
US9170933B2 (en) * | 2010-06-28 | 2015-10-27 | International Business Machines Corporation | Wear-level of cells/pages/sub-pages/blocks of a memory |
JP2012079100A (en) * | 2010-10-01 | 2012-04-19 | Canon Inc | Disk control apparatus and method and program |
KR101190742B1 (en) * | 2010-12-06 | 2012-10-12 | 에스케이하이닉스 주식회사 | Controller for memory and storage system includint the same, method for measuring life span of memory |
US9129699B2 (en) | 2011-04-28 | 2015-09-08 | Hitachi, Ltd. | Semiconductor storage apparatus and method including executing refresh in a flash memory based on a reliability period using degree of deterioration and read frequency |
CN102163165B (en) * | 2011-05-26 | 2012-11-14 | 忆正存储技术(武汉)有限公司 | Error estimation module and estimation method thereof for flash memory |
US8719531B2 (en) | 2011-06-14 | 2014-05-06 | Western Digital Technologies, Inc. | System and method for performing data retention that incorporates environmental conditions |
EP2745203B1 (en) | 2011-08-19 | 2016-09-21 | Kabushiki Kaisha Toshiba | Information processing apparatus |
CN102956266B (en) * | 2011-08-30 | 2015-08-05 | 株式会社理光 | A kind of information storage means used in the engine part of image processing system |
CN102999448B (en) * | 2011-09-14 | 2018-07-06 | 奇智软件(北京)有限公司 | A kind of processing method and processing device of external equipment detection |
JP5222388B2 (en) * | 2011-11-22 | 2013-06-26 | 株式会社日立製作所 | Storage system management system and management method using flash memory |
TWI455140B (en) * | 2012-02-21 | 2014-10-01 | Fluiditech Ip Ltd | Flash memory usage period assessment method |
US20140013028A1 (en) * | 2012-07-09 | 2014-01-09 | Hamilton Sundstrand Corporation | Hardware flash memory wear monitoring |
US20140095778A1 (en) * | 2012-09-28 | 2014-04-03 | Jaewoong Chung | Methods, systems and apparatus to cache code in non-volatile memory |
GB2514354A (en) * | 2013-05-20 | 2014-11-26 | Ibm | Managing storage devices having a lifetime of a finite number of operations |
US9875810B2 (en) * | 2013-07-24 | 2018-01-23 | Microsoft Technology Licensing, Llc | Self-identifying memory errors |
US9612773B2 (en) * | 2013-11-21 | 2017-04-04 | Samsung Electronics Co., Ltd. | User device having a host flash translation layer (FTL), a method for transferring an erase count thereof, a method for transferring reprogram information thereof, and a method for transferring a page offset of an open block thereof |
CN106909318B (en) * | 2013-12-23 | 2020-05-08 | 华为技术有限公司 | Solid state disk using method and device |
CN105005450B (en) * | 2014-04-25 | 2018-11-02 | 群联电子股份有限公司 | Method for writing data, memory storage apparatus and memorizer control circuit unit |
KR101628925B1 (en) * | 2014-06-17 | 2016-06-10 | 고려대학교 산학협력단 | Memory system and operation method of the same |
CN105512056A (en) * | 2014-09-24 | 2016-04-20 | 中兴通讯股份有限公司 | Method and device for data storage, and terminal |
JP6421042B2 (en) * | 2015-01-16 | 2018-11-07 | ルネサスエレクトロニクス株式会社 | Information processing device |
JP6365341B2 (en) * | 2015-02-23 | 2018-08-01 | 京セラドキュメントソリューションズ株式会社 | Image forming apparatus |
JP6541369B2 (en) * | 2015-02-24 | 2019-07-10 | キヤノン株式会社 | Data processing apparatus for processing data in memory, data processing method, and program |
CN106779008A (en) * | 2015-11-23 | 2017-05-31 | 杭州海康威视数字技术股份有限公司 | SD card, video camera and SD card reliability early warning system |
CN105373350A (en) * | 2015-11-23 | 2016-03-02 | 联想(北京)有限公司 | Data management method and device |
JP6515799B2 (en) * | 2015-12-18 | 2019-05-22 | 京セラドキュメントソリューションズ株式会社 | Electronic equipment and memory life warning program |
JP6432499B2 (en) * | 2015-12-18 | 2018-12-05 | 京セラドキュメントソリューションズ株式会社 | Electronic device and memory life warning program |
US10558369B2 (en) * | 2016-02-01 | 2020-02-11 | Qualcomm Incorporated | Flash device lifetime monitor systems and methods |
JP6190488B2 (en) * | 2016-04-15 | 2017-08-30 | 東芝メモリ株式会社 | Information recording system |
JP2018156582A (en) * | 2017-03-21 | 2018-10-04 | キヤノン株式会社 | Method for controlling storage of information processing apparatus and image forming apparatus |
CN106980566B (en) * | 2017-03-27 | 2020-05-26 | 联想(北京)有限公司 | Display control method and storage device |
JP7010667B2 (en) | 2017-11-06 | 2022-01-26 | キオクシア株式会社 | Memory system and control method |
TWI692691B (en) | 2018-01-11 | 2020-05-01 | 大陸商合肥沛睿微電子股份有限公司 | Memory control device and memory control method |
US10714187B2 (en) | 2018-01-11 | 2020-07-14 | Raymx Microelectronics Corp. | Memory control device for estimating time interval and method thereof |
JP6913797B2 (en) * | 2018-08-31 | 2021-08-04 | キオクシア株式会社 | Information processing device |
KR102599176B1 (en) * | 2018-11-14 | 2023-11-08 | 삼성전자주식회사 | Storage device using host memory buffer and memory management method thereof |
JP7424321B2 (en) * | 2019-02-06 | 2024-01-30 | ソニーグループ株式会社 | Memory diagnostic device and memory diagnostic method |
JP7143487B2 (en) * | 2020-05-18 | 2022-09-28 | キオクシア株式会社 | Information processing equipment |
JP7097631B2 (en) * | 2020-11-04 | 2022-07-08 | 株式会社ユピテル | Systems and programs |
KR20220124318A (en) | 2021-03-02 | 2022-09-14 | 삼성전자주식회사 | Storage controller redirecting a write operation and operating method thereof |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6078520A (en) * | 1993-04-08 | 2000-06-20 | Hitachi, Ltd. | Flash memory control method and information processing system therewith |
US6249838B1 (en) * | 1998-12-28 | 2001-06-19 | Cisco Technology Inc. | Physical medium information in file system header |
US20020091965A1 (en) * | 2000-12-22 | 2002-07-11 | Mark Moshayedi | System and method for early detection of impending failure of a data storage system |
US6993690B1 (en) * | 1998-12-16 | 2006-01-31 | Hagiwara Sys-Com Co., Ltd. | Memory unit having memory status indicator |
US20060265545A1 (en) * | 2005-05-20 | 2006-11-23 | Nec Infrontia Corporation | Information processing apparatus, lifetime monitoring method and program for monitoring lifetime of storage device including flash memory |
US20070266200A1 (en) * | 2006-05-15 | 2007-11-15 | Gorobets Sergey A | Methods of End of Life Calculation for Non-Volatile Memories |
US20080126679A1 (en) * | 2004-07-13 | 2008-05-29 | Michael Philipps | Electronic Device with a Nonvolatile, Writable Data-Memory |
US20080162079A1 (en) * | 2006-10-05 | 2008-07-03 | International Business Machines Corp. | End of life prediction of flash memory |
US7512847B2 (en) * | 2006-02-10 | 2009-03-31 | Sandisk Il Ltd. | Method for estimating and reporting the life expectancy of flash-disk memory |
US7653778B2 (en) * | 2006-05-08 | 2010-01-26 | Siliconsystems, Inc. | Systems and methods for measuring the useful life of solid-state storage devices |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US265545A (en) * | 1882-10-03 | Emanuel m | ||
US4224506A (en) * | 1978-03-24 | 1980-09-23 | Pitney Bowes Inc. | Electronic counter with non-volatile memory |
JP2001195316A (en) * | 2000-01-14 | 2001-07-19 | Canon Inc | Backup storage device, image formation device, backup storage device control method and storage medium |
US6426898B1 (en) * | 2001-03-05 | 2002-07-30 | Micron Technology, Inc. | Method of reducing trapped holes induced by erase operations in the tunnel oxide of flash memory cells |
US6775624B2 (en) * | 2001-10-19 | 2004-08-10 | International Business Machines Corporation | Method and apparatus for estimating remaining life of a product |
JP2003216506A (en) * | 2002-01-23 | 2003-07-31 | Hitachi Ltd | Storage device with flash memory and computer |
US6751766B2 (en) * | 2002-05-20 | 2004-06-15 | Sandisk Corporation | Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data |
JP4381740B2 (en) * | 2002-08-15 | 2009-12-09 | 独立行政法人産業技術総合研究所 | Optical recording / reproducing apparatus, optical recording / reproducing method, and optical recording medium |
JP4110000B2 (en) * | 2003-01-28 | 2008-07-02 | 株式会社ルネサステクノロジ | Storage device |
JP4073799B2 (en) * | 2003-02-07 | 2008-04-09 | 株式会社ルネサステクノロジ | Memory system |
CN1858855A (en) | 2006-02-17 | 2006-11-08 | 华为技术有限公司 | Counting method and device for extending non-volatile storage life |
-
2006
- 2006-11-30 JP JP2006322868A patent/JP4575346B2/en active Active
-
2007
- 2007-11-28 US US14/249,070 patent/USRE47946E1/en active Active
- 2007-11-28 AT AT07832620T patent/ATE546782T1/en active
- 2007-11-28 US US12/513,860 patent/US8156393B2/en not_active Ceased
- 2007-11-28 KR KR1020097011144A patent/KR101079502B1/en active IP Right Grant
- 2007-11-28 WO PCT/JP2007/072898 patent/WO2008066058A1/en active Application Filing
- 2007-11-28 CN CN201510111605.2A patent/CN104699546A/en active Pending
- 2007-11-28 EP EP07832620A patent/EP2088512B1/en active Active
- 2007-11-28 CN CNA2007800425527A patent/CN101535967A/en active Pending
- 2007-11-30 TW TW096145749A patent/TW200834581A/en unknown
-
2012
- 2012-03-22 US US13/426,696 patent/US20120179942A1/en not_active Abandoned
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6078520A (en) * | 1993-04-08 | 2000-06-20 | Hitachi, Ltd. | Flash memory control method and information processing system therewith |
US6993690B1 (en) * | 1998-12-16 | 2006-01-31 | Hagiwara Sys-Com Co., Ltd. | Memory unit having memory status indicator |
US6249838B1 (en) * | 1998-12-28 | 2001-06-19 | Cisco Technology Inc. | Physical medium information in file system header |
US20020091965A1 (en) * | 2000-12-22 | 2002-07-11 | Mark Moshayedi | System and method for early detection of impending failure of a data storage system |
US20080126679A1 (en) * | 2004-07-13 | 2008-05-29 | Michael Philipps | Electronic Device with a Nonvolatile, Writable Data-Memory |
US20060265545A1 (en) * | 2005-05-20 | 2006-11-23 | Nec Infrontia Corporation | Information processing apparatus, lifetime monitoring method and program for monitoring lifetime of storage device including flash memory |
US7512847B2 (en) * | 2006-02-10 | 2009-03-31 | Sandisk Il Ltd. | Method for estimating and reporting the life expectancy of flash-disk memory |
US7653778B2 (en) * | 2006-05-08 | 2010-01-26 | Siliconsystems, Inc. | Systems and methods for measuring the useful life of solid-state storage devices |
US20070266200A1 (en) * | 2006-05-15 | 2007-11-15 | Gorobets Sergey A | Methods of End of Life Calculation for Non-Volatile Memories |
US20080162079A1 (en) * | 2006-10-05 | 2008-07-03 | International Business Machines Corp. | End of life prediction of flash memory |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130262942A1 (en) * | 2012-03-27 | 2013-10-03 | Yung-Chiang Chu | Flash memory lifetime evaluation method |
CN103559115A (en) * | 2013-09-29 | 2014-02-05 | 记忆科技(深圳)有限公司 | SSD intelligent monitoring system based on SMART |
US10254982B2 (en) * | 2016-11-10 | 2019-04-09 | Western Digital Technologies, Inc. | System and methodology for low latency error management within a shared non-volatile memory architecture |
US10514867B2 (en) | 2016-11-10 | 2019-12-24 | Western Digital Technologies, Inc. | System and methodology that facilitates error management within a shared non-volatile memory architecture |
Also Published As
Publication number | Publication date |
---|---|
EP2088512B1 (en) | 2012-02-22 |
WO2008066058A1 (en) | 2008-06-05 |
CN104699546A (en) | 2015-06-10 |
KR101079502B1 (en) | 2011-11-03 |
TW200834581A (en) | 2008-08-16 |
US8156393B2 (en) | 2012-04-10 |
EP2088512A4 (en) | 2009-11-25 |
TWI380302B (en) | 2012-12-21 |
USRE47946E1 (en) | 2020-04-14 |
US20100011260A1 (en) | 2010-01-14 |
JP4575346B2 (en) | 2010-11-04 |
JP2008139927A (en) | 2008-06-19 |
EP2088512A1 (en) | 2009-08-12 |
KR20090079969A (en) | 2009-07-22 |
ATE546782T1 (en) | 2012-03-15 |
CN101535967A (en) | 2009-09-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8156393B2 (en) | Memory system | |
US10020072B2 (en) | Detect developed bad blocks in non-volatile memory devices | |
US8078923B2 (en) | Semiconductor memory device with error correction | |
KR101498669B1 (en) | Semiconductor memory system and access method thereof | |
JP5112566B1 (en) | Semiconductor memory device, nonvolatile semiconductor memory inspection method, and program | |
US8977803B2 (en) | Disk drive data caching using a multi-tiered memory | |
JP5759630B2 (en) | Wear leveling for memory devices | |
US10657014B2 (en) | Methods for monitoring and managing memory devices | |
US10592134B1 (en) | Open block stability scanning | |
US20160041760A1 (en) | Multi-Level Cell Flash Memory Control Mechanisms | |
TWI566252B (en) | Method of performing wear management in non-volatile memory devices | |
US20140006688A1 (en) | Endurance and Retention Flash Controller with Programmable Binary-Levels-Per-Cell Bits Identifying Pages or Blocks as having Triple, Multi, or Single-Level Flash-Memory Cells | |
CN104919434A (en) | System and method for lower page data recovery in a solid state drive | |
US7962810B2 (en) | Recording medium structure capable of displaying defect rate | |
US10475522B2 (en) | Memory system including a delegate page and method of identifying a status of a memory system | |
JP2010086404A (en) | Method for managing memory, and flash memory device | |
JP2012123641A (en) | Semiconductor disk device | |
TW202236291A (en) | Methods and systems for improving ecc operation of memories | |
Janukowicz et al. | IN THIS WHITE PAPER | |
CN114121110A (en) | NAND flash management with pre-learned endurance | |
JP2010192047A (en) | Disk drive apparatus and method for controlling nonvolatile memory |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |