US4374411A - Relocatable read only memory - Google Patents
Relocatable read only memory Download PDFInfo
- Publication number
- US4374411A US4374411A US06/121,450 US12145080A US4374411A US 4374411 A US4374411 A US 4374411A US 12145080 A US12145080 A US 12145080A US 4374411 A US4374411 A US 4374411A
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- memory
- bits
- processor
- address
- byte
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/261—Microinstruction address formation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
- G06F12/0669—Configuration or reconfiguration with decentralised address assignment
Definitions
- the present invention relates to computer memory apparatus and more specifically to read only memory devices for use with microprocessors and microcomputers.
- microprocessors and one chip microcomputers have fostered a virtual revolution in consumer electronic products.
- microprocessors control a host of devices for which computer control would have been prohibitively expensive ten years ago.
- ROM read only memories
- instructions containing memory addresses generally require several sequential fetches from memory.
- Most instructions containing memory references can be fetched from memory in one or two accesses (fetches), but in some microprocessors, memory reference instructions require three fetches from memory. The first fetch accesses the instruction byte which signifies the type of memory reference instruction. The second two bytes contain the two-byte address referenced in the memory reference instruction.
- a common format for such memory reference instructions places the most significant byte of the referenced memory address in the last byte fetched from memory.
- standardized software may be most economically distributed for use in microprocessors via read only memories.
- the least expensive vehicle for propagating software directly usable by a microprocessor is the mass produced mask programmed read only memory.
- the economics of production of such read only memories come from the ability to produce large numbers of identical devices because there is a relatively large setup cost for producing a mask programmed ROM but the cost per unit manufactured decreases as the setup cost is distributed over a large number of units.
- a read only memory could provide a microprocessor with an instruction to jump to what the ROM program considered another address within the ROM, but due to the addressing scheme used in the microprocessor system, would cause the processor to fetch an instruction from an entirely unrelated memory location.
- the prior art has included a scheme for writing program segments out of a read only memory into a random access memory and identifying portions of memory reference instructions, and using a combination of software and hardware to modify the address bytes in memory reference instructions.
- the main processor is then designed to execute instructions contained in the random access memory.
- Another device has included a relatively complicated base address register and an adder for modifying the address supplied to the microprocessor program counter from memory reference instructions contained in a ROM.
- the prior art has heretofore not provided a simple and inexpensive scheme of locating a ROM within the memory addressing scheme of a microprocessor based system so that memory reference instructions contained within the ROM will not cause the program counter to jump to an improper memory location and which also allows the ROM to be placed in different address locations within different microprocessor based systems without extensive modification to either hardware or ROM software.
- the present invention overcomes the problems presented by the prior art of providing general purpose software in mask programmed read only memories which may be located at different addresses of a microprocessor based system.
- the invention disclosed herein allows the user to modify the address contained in a memory reference instruction (such as a JUMP instruction) using a set of switches which is also used to define the address of the particular read only memory by comparison to highest order bits from the system address bus.
- the present invention is usable in any microprocessor based system wherein: (1) the microprocessor is characterized by an instruction set requiring M fetches from memory for a memory reference instruction; (2) the first memory fetch for any instruction is readily identifiable; (3) and the most significant byte of the address referenced in the memory reference instruction is contained in the final or Mth byte fetched.
- the present invention generally locates the ROM in any desired portion of the address space by defining N replacement bits for memory reference instructions and providing these N bits in lieu of N bits contained in the Mth byte of the memory reference instruction whenever the invention detects the most significant byte of a memory reference instruction being provided from the ROM to the data bus. More specifically the disclosed embodiment uses a simple counter which resets upon each occurrence of the first fetch of any instruction from memory and which will substitute N predetermined replacement bits on the N most significant bits of the data bus whenever the counter counts that M memory fetches have occurred without the counter being reset.
- a further advantage of the present invention is that many microprocessor systems already require the apparatus necessary to provide the N replacement bits.
- This apparatus is often embodied as N input bits to an address decoder which is used to define the block of memory in which the particular ROM circuit is located. With signals defining the block available, the present invention takes advantage of such systems by using the same signals which are inputs to the address decoder as the outputs to the data bus for N bits of the most significant byte of a memory reference instruction.
- the present invention provides an extremely simple and inexpensive way of locating generalized mass produced read only memory programs which may be located virtually anywhere within a microprocessor memory space.
- the programmer may develop all purpose programs for a particular microprocessor, mass produce read only memories containing the programs using zero base addressing, and distribute the read only memories with the assurance that they may be used successfully in any system employing the microprocessor for which the program was written.
- FIG. 1 is a block diagram of a microprocessor system embodying the present invention.
- FIG. 2 is a schematic diagram of the preferred embodiment of the present invention as used with a particular commercially available microprocessor.
- FIG. 3 is a timing diagram showing several relevant waveforms within the preferred embodiment of FIG. 2.
- the present invention is useful in any microprocessor system having an instruction set using memory reference instructions which are M bytes in length, and in which such instructions use the Mth byte as the most significant address byte of the memory reference.
- the present invention is most easily accomplished in systems in which the first memory fetch for any instruction is readily identifiable.
- the present invention will substitute N bits (N being an integer greater than 0 and less or equal to L) of the most significant byte on the data bus when a memory reference instruction is being executed.
- the type 8080, type 6502, and the Z80 fill all of these qualifications.
- the preferred embodiment disclosed herein shows, by way of example, a system using the Intel 8080 microprocessor. It will be appreciated by those skilled in the art that the 8080 microprocessor is a byte oriented processor having eight bit bytes and which are characterized by an instruction set requiring three memory fetches for memory reference instructions. It will therefore be appreciated that the preferred embodiment disclosed herein fits the generalized description set forth above wherein L equals eight and M equals three. As will be appreciated from the description to follow the four most significant address bits are used to define memory blocks in the example of the preferred embodiment and therefore N equals four.
- FIG. 1 a block diagram of the preferred embodiment is shown so that the simplicity of the present invention may be readily appreciated.
- a microprocessor 10 including an address bus 11 and a data bus 12 is the environment of the present invention. It is to be understood that a plurality of read only memory devices such as the type disclosed herein may be used in any microprocessor system and that other read only memories together with random access memories and other I/O devices will be attached to the address and data buses of processor 10.
- An address block decoder 15 is connected to address bus 11 and provides an output on line 16 when the N most significant bits of address bus 11 compare on a one to one basis with N replacement bits from block 17.
- An output on line 16 enables read only memory 18.
- the least significant bits of the address bus 11 appear on a small address bus 19 to directly address a location in the enabled ROM.
- the output of ROM 18 is divided into its significant bits 20, and its least significant bits 21.
- the least significant bits 21 of the output of ROM 18 are provided directly to data bus 12 while the most significant bits 20 of the output of ROM 18 are provided to a data selector 25.
- the output of data selector 25 appears as a small bus 22 which contains the most significant bits of data bus 12. It will be be appreciated that data selector 25 will have three state outputs connected to bus 22 in order that the entirety of data bus 12 may be connected to other devices without being adversely affected by data selector 25.
- the other input port to data selector 25 carries the N replacement bits from block 17 which appear on bus 26. Therefore, depending on the state of line 27 which is provided to the select input of data selector 25, either the most significant bits 20 from ROM 18 will be provided on output bus 22 or the replacement bits from bus 26 will be provided onto output bus 22.
- Line 27 is controlled by a generalized latch 30 shown as setting when an output is received from first fetch detector 28 and clearing when the most significant byte of a memory reference instruction is detected by block 29.
- generalized status bus 31 shown in FIG. 1 may comprise outputs directly from processor 10 and also comprise outputs from a status latch and a control bus associated with a microprocessor system.
- Microprocessor 10 is an Intel type 8080 but, as has been mentioned hereinabove, other processors may be used with the present invention.
- Address bus 11 is identified by a dashed line. The lowest address bits are shown as 19a and 19b in FIG. 2.
- Address block decoder 15 is embodied at a TTL 7485 four bit magnitude comparator with line 16 being connected to the equal output of said comparator.
- 1 corresponds to 1K ROMs 18a-18d together with two line to one-of-four decoder 38 which decodes the next two most significant bits (A11 and A10) of the address bus in order to select one of the 1K ROMs 18a-18d when enabled by a logical one on line 16.
- bit bus 20 of FIG. 2 is a four bit bus which directly corresponds to bus 20 of FIG. 1 as do four bit buses 21 and 22 of FIG. 2.
- Data selector 25 is embodied by a type 74257 quad two input multiplexer having tristate outputs which are controlled by the signal present on line 36.
- a logical zero on line 36 enables multiplexer 25 and a logical one on line 36 forces bus 22 to a high impedance state. It will therefore be appreciated that when a favorable comparison is detected by address block decoder 15, as evidenced by a logical one on line 16, a logical zero will appear on line 36 and multiplexer 25 will be enabled.
- replacement bit source 17 is embodied simply as four single pole switches which establish the logical conditions on four bits bus 26 as well as at the B inputs to comparator 15. It will be appreciated that switches 17 define both the block of memory which microprocessor 10 must address in order to access ROMs 18a-18d as well as providing the replacement bits on bus 26.
- switches 17 may be embodied by a plurality of different conventional devices incuding DIP switches, the output of a thumb wheel switch, or hard wired connections.
- switches 17 are set with their two most significant bits equal to zero and their two least significant bits equal to one. Therefore line 16 will be in its logical one state whenever a number 0011XXXXXXXXXXXXX is provided on address bus 11. Therefore the block defined by address block decoder 15 is a four K memory block which could also have been determined from inspection of ROMs 18a-18d.
- a conventional status latch 37 having an output labeled as M1 which appears on line 40 is shown. It will be appreciated by those skilled in the art that status latch 37 is conventionally embodied as a type 8212 latch presently manufactured by Intel Corporation. It will further be appreciated that in a system built using a type 8080 microprocessor line M1 goes high during the machine cycle for which the first fetch to memory for an instruction is made.
- DBIN DATA BUS IN
- line 41 DATA BUS IN
- the DBIN output may be generically referred to as a read strobe and, in the particular processor shown, line 41 will go to a logical one state when processor 10 is reading data from data bus 12.
- FIG. 3 a timing diagram is provided showing the fetching of a generalized memory reference instruction by microprocessor 10.
- the environment of the present invention usually requires that the first fetch from memory for an instruction be easily identified.
- output M1 which appears on line 40 fills this qualification since the output goes high during the first memory fetch for every instruction fetched from memory by the processor. This may be seen from inspection of FIG. 3 wherein M1 is seen to go high at the beginning of the T2 period of the phase one system clock.
- the representation of the data bus being in a logical one state during the transition from T1 to T2 is indicative that a status word is present on the bus during this time. It will be appreciated that this status word corresponds to the M1 output about to be latched onto line 40 at the beginning of the T2 period.
- a negative edge triggered D-type flip-flop 30' embodies the generalized latch 30 shown in FIG. 1. It is the combination of the input characteristics of D-type flip-flop 30', the M1 signal on line 40, and the read strobe signal on line 41 for the 8080 microprocessor that fulfill the conditions set forth above for the environment of the present invention.
- the M1 pulse lasts through the first read strobe pulse which appears during clock periods T2 and T3.
- the first byte of a memory reference instruction is provided onto the data bus.
- a new status word is latched onto status latch 37 and therefore the M1 output on line 40 goes low.
- the read strobe on line 41 goes high and, as may be seen from FIG. 3, the second byte of the memory reference instruction is read from the data bus by processor 10.
- byte two of the memory reference instruction contains the least signficant bits (corresponding to A0-A7) of the memory location reference in the memory reference instruction.
- flip-flop 30' On the falling edge of the read strobe on line 41, flip-flop 30' will be clocked. Since the D input is grounded, flip-flop 30' will clear and a logical one will appear on line 27 to the select input of data selector 25. From FIG. 3, it may be appreciated that, since M1 set the flip-flop prior to byte one of the memory reference instruction being read from the data bus, data selector 25 has had a logical zero on line 27 during the reading of the previous two bytes. It will also be appreciated that upon the falling edge of the read strobe, which occurs in the middle of period T8, the select input to selector 25 becomes logical one. The third and most significant byte of the memory reference instruction appears on the data bus during the portions of periods T10 and T11 shown in FIG. 3.
- any memory reference instruction such as a JUMP instruction, may be written into ROM 18 in the form JUMP 0000ABCDEFGHIJKL but will be provided to data bus 12 of processor 10 in the form of JUMP 0011ABCDEFGHIJKL by the preferred embodiment.
- the program contained within 1K ROMs 18a-18d may be mass produced with all memory reference instructions zero based, that is, having their four most significant bits equal to zero, and yet may be placed in a block of memory, and be treated by processor 10, as containing memory reference instructions having their four most significant bits equal to a number defined by switches 17.
- the first memory fetch for the beginning of any instruction causes output M1 to go high thus setting flip-flop 30' and providing the most significant bits from the outputs of ROMs 18a-18d appearing on bus 20 to bus 22. Therefore, if processor 10 is executing a sequence of two byte instructions flip-flop 30' will remain set. Other three byte instructions will not reference memory and will not affect operation of the processor.
- the flip-flop clears at the end of the second fetch (the falling edge of DBIN) in period T8 and will remain cleared if a third fetch occurs (thus providing the replacement bits to bus 22), or will be set once again by the next occurrence of an M1 output indicating the first memory fetch of another instruction.
- any device which will detect the first occurrence of a memory fetch for an instruction, and which will thereafter count memory fetches during that same instruction and change the state of a particular output when the Mth fetch for that instruction takes place, will be the equivalent of flip-flop 30' shown in FIG. 2.
- FIG. 2 the apparatus enclosed within block 31 corresponds to the apparatus enclosed within block 31 in FIG. 1 and, as explained previously, the remaining apparatus shown in FIG. 2 would be required of a conventional system. Therefore the very slight increase in cost in order to construct an embodiment of the present invention for use in a microprocessor based system will be appreciated since data selector 25 is available conventionally as a single MSI integrated circuit package and flip-flops for flip-flop 30' are available several to the package. It will be appreciated that the elements enclosed by dashed line 50 are the components which will be used on a 4K memory "card" embodying the present invention.
- the present invention may be embodied very conveniently on a card containing 4K of read only memory but can greatly increase the versatility and variety of mass produced ROMs which may be placed in the locations of ROMs 18a-18d.
Abstract
Description
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/121,450 US4374411A (en) | 1980-02-14 | 1980-02-14 | Relocatable read only memory |
Applications Claiming Priority (1)
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US06/121,450 US4374411A (en) | 1980-02-14 | 1980-02-14 | Relocatable read only memory |
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US4374411A true US4374411A (en) | 1983-02-15 |
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US06/121,450 Expired - Lifetime US4374411A (en) | 1980-02-14 | 1980-02-14 | Relocatable read only memory |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4473878A (en) * | 1981-11-23 | 1984-09-25 | Motorola, Inc. | Memory management unit |
US4736290A (en) * | 1985-06-18 | 1988-04-05 | International Business Machines Corporation | Microprocessors |
US4979148A (en) * | 1988-12-09 | 1990-12-18 | International Business Machines Corporation | Increasing options in mapping ROM in computer memory space |
US5592652A (en) * | 1994-05-06 | 1997-01-07 | Mitsubishi Denki Kabushiki Kaisha | Single-chip microcomputer system having address space allocation hardware for different modes |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US3681757A (en) * | 1970-06-10 | 1972-08-01 | Cogar Corp | System for utilizing data storage chips which contain operating and non-operating storage cells |
US3781826A (en) * | 1971-11-15 | 1973-12-25 | Ibm | Monolithic memory utilizing defective storage cells |
US3959783A (en) * | 1973-12-27 | 1976-05-25 | Compagnie Internationale Pour L'informatique | Control store unit addressing device |
US3980991A (en) * | 1973-12-28 | 1976-09-14 | Ing. C. Olivetti & C., S.P.A. | Apparatus for controlling microprogram jumps in a microprogrammable electronic computer |
US4038645A (en) * | 1976-04-30 | 1977-07-26 | International Business Machines Corporation | Non-translatable storage protection control system |
US4051460A (en) * | 1975-02-01 | 1977-09-27 | Nippon Telegraph And Telephone Public Corporation | Apparatus for accessing an information storage device having defective memory cells |
US4121286A (en) * | 1975-10-08 | 1978-10-17 | Plessey Handel Und Investments Ag | Data processing memory space allocation and deallocation arrangements |
-
1980
- 1980-02-14 US US06/121,450 patent/US4374411A/en not_active Expired - Lifetime
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3681757A (en) * | 1970-06-10 | 1972-08-01 | Cogar Corp | System for utilizing data storage chips which contain operating and non-operating storage cells |
US3781826A (en) * | 1971-11-15 | 1973-12-25 | Ibm | Monolithic memory utilizing defective storage cells |
US3959783A (en) * | 1973-12-27 | 1976-05-25 | Compagnie Internationale Pour L'informatique | Control store unit addressing device |
US3980991A (en) * | 1973-12-28 | 1976-09-14 | Ing. C. Olivetti & C., S.P.A. | Apparatus for controlling microprogram jumps in a microprogrammable electronic computer |
US4051460A (en) * | 1975-02-01 | 1977-09-27 | Nippon Telegraph And Telephone Public Corporation | Apparatus for accessing an information storage device having defective memory cells |
US4121286A (en) * | 1975-10-08 | 1978-10-17 | Plessey Handel Und Investments Ag | Data processing memory space allocation and deallocation arrangements |
US4038645A (en) * | 1976-04-30 | 1977-07-26 | International Business Machines Corporation | Non-translatable storage protection control system |
Non-Patent Citations (2)
Title |
---|
"Kilobaud: Hardware Program Relocation-The Way Biggies Do It", Dr. Michael Wingfield, The Small Computer Magazine, Jan. 1978, Issue No. 13, pp. 60-62. * |
Computer Dictionary & Handbook, Sippl & Sippl, Howard W. Sams & Co., Inc., Third Edition, 1980, Preface and pp. 136, 340, 278, 279, 336 & 337. * |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4473878A (en) * | 1981-11-23 | 1984-09-25 | Motorola, Inc. | Memory management unit |
US4736290A (en) * | 1985-06-18 | 1988-04-05 | International Business Machines Corporation | Microprocessors |
US4979148A (en) * | 1988-12-09 | 1990-12-18 | International Business Machines Corporation | Increasing options in mapping ROM in computer memory space |
US5592652A (en) * | 1994-05-06 | 1997-01-07 | Mitsubishi Denki Kabushiki Kaisha | Single-chip microcomputer system having address space allocation hardware for different modes |
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