WO1997002602A1

WO1997002602A1 - Semiconductor integrated circuit device and method of production thereof

Info

Publication number: WO1997002602A1
Application number: PCT/JP1996/001653
Authority: WO
Inventors: Sohei Omori; Shinichiro Wada; Nobuo Tamba; Akihisa Uchida
Original assignee: Hitachi, Ltd.
Priority date: 1995-07-04
Filing date: 1996-06-17
Publication date: 1997-01-23
Also published as: JP3942192B2

Abstract

A semiconductor integrated circuit device comprising an SOI substrate (5) that includes a semiconductor layer (5c) deposited on an insulating layer (5b) formed over a semiconductor substrate (5a). The insulating layer (5b) is selectively removed immediately below the p-n junctions of input protective diodes D1, D2 to remove heat and static charges from the diodes by conducting them directly to the semiconductor substrate (5a).

Description

Description: Semiconductor integrated circuit device and method of manufacturing the same

The present invention relates to a semiconductor integrated circuit device and a manufacturing technology thereof, and more particularly to a technology effective when applied to a protection element technology of a semiconductor integrated circuit device using an SOI (Silicon On Insulator) substrate. Background art

The SOI technology is a technology for forming a predetermined semiconductor integrated circuit device on a thin semiconductor layer formed on an insulating layer, and has, for example, the following excellent effects.

That is, a complete element isolation structure can be realized by forming the element isolation portion to reach the insulating layer for forming SOI. Also, since there is no active parasitic effect such as a parasitic M0S transistor or a parasitic bipolar transistor appearing in the pn junction isolation structure, a latch-up phenomenon can be prevented. Furthermore, since the area occupied by the element isolation portion is small, the degree of element integration can be improved.

Meanwhile, the SOI substrate studied by the present inventors has a structure in which a thin semiconductor layer is provided on a semiconductor substrate for securing strength via an insulating layer, and a predetermined semiconductor integrated circuit device is provided on the semiconductor layer. Are formed.

These elements include the elements that make up the internal circuits of the semiconductor integrated circuit device, the input / output circuits (including input circuits, output circuits, and input / output bidirectional circuits) of the semiconductor integrated circuit device, and the like. elements such as power ^¾ Mel protective circuit for protecting the.

On such a semiconductor layer for element formation, wiring for connecting elements and the like via an insulating layer is formed. That is, the SOI substrate The structure is such that a semiconductor layer for element formation is sandwiched between insulating layers above and below it.

The SOI substrate is described, for example, in Keigaku Shuppan Co., Ltd., published on February 15, 1990, in “Illustrated Super LSI Engineering” on pages 322 to 325. The structure and various manufacturing methods are described.

However, the present inventor has found that the above-mentioned inventor's ssociated SOI technology has the following problems.

First, in the S0I substrate, the heat generated when the element breaks down is transferred to the thin semiconductor layer because the semiconductor layer on which the element for the protection circuit is formed is sandwiched between the upper and lower insulating layers. There is a problem that only heat can escape in the horizontal direction, and the heat may cause the protection circuit element to deteriorate or be damaged.

Second, in the SOI substrate, when a large current due to static electricity or the like flows through the semiconductor layer on which the element for the protection circuit is formed, the large current is reduced because the upper and lower portions of the semiconductor layer are sandwiched by insulating layers. There is a problem that only a lateral current can escape along the thin semiconductor layer, and the large current concentrates on the element for the protection circuit, so that the element for the protection circuit is deteriorated or damaged. An object of the present invention is to provide a technique capable of improving the heat dissipation of heat generated in a protection circuit element in a semiconductor integrated circuit device using an SOI substrate.

Another object of the present invention is to provide a technique capable of improving the electrostatic breakdown resistance of a protection circuit element in a semiconductor integrated circuit device using an SOI substrate.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

A semiconductor integrated circuit device according to the present invention includes a supporting semiconductor substrate, A semiconductor integrated circuit device comprising: an SOI substrate having an element forming semiconductor layer provided via an insulating layer; and an external terminal for leading out an electrode of the element on an upper layer of the semiconductor layer. In the above, an element for a protection circuit electrically connected to the external terminal is provided on the insulating layer removed region where the insulating layer is partially removed.

According to the above-described semiconductor integrated circuit device of the present invention, the heat generated when the protection circuit element breaks down can be released to the supporting semiconductor substrate side through the insulating layer removal region. It is possible to improve the heat dissipation of the heat generated in the element for use.

In addition, the charge generated by static electricity or the like can be released to the supporting semiconductor substrate side through the insulating layer removal area, and the charge can be prevented from being concentrated on the protection circuit element. It becomes possible to improve the electrostatic breakdown resistance of the device.

In addition, since the insulating layer of the SOI substrate is only partially removed and the insulating layer is left in other regions, the above-described effects can be obtained without increasing the diffusion capacitance and the wiring-substrate capacitance. It becomes possible.

Furthermore, since the insulating layer of the SOI substrate is only partially removed and the insulating layer is left in other regions, no significant step is formed in the upper semiconductor layer. Therefore, it is possible to prevent the occurrence of a defect such as a disconnection of a wiring due to a step.

Further, in the semiconductor integrated circuit device according to the present invention, the predetermined semiconductor region of the element for the protection circuit is provided so as to be in contact with the insulating layer, and the predetermined semiconductor region of the element forming the semiconductor integrated circuit is insulated. It is provided so as to be in contact with the layer.

According to the semiconductor integrated circuit device described above, the overall diffusion capacitance in the semiconductor integrated circuit device can be reduced, so that the operation speed of the semiconductor integrated circuit device can be improved. BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 1, a main part plan view of the semiconductor integrated circuit device of FIG. 1, FIG. 4 is a plan view of a semiconductor chip constituting the semiconductor integrated circuit device, FIG. 5 is a plan view of a semiconductor chip constituting the semiconductor integrated circuit device, FIG. 6 is a circuit diagram of an input protection circuit of a semiconductor integrated circuit device, FIG. 7 is a circuit diagram of an output protection circuit of a semiconductor integrated circuit device, and FIG. 8 is a cross-sectional view of a main part during a manufacturing process of the semiconductor integrated circuit device. FIG. 9 is a cross-sectional view of a main part of the semiconductor integrated circuit device during the manufacturing process following FIG. 8, and FIG. 10 is a cross-sectional view of a main part of the semiconductor integrated circuit device during the manufacturing process following FIG. 1 is a cross-sectional view of the main parts during the manufacturing process of the semiconductor integrated circuit device following Fig. 10. FIG. 12 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during the manufacturing process following FIG. 11; FIG. 13 is a fragmentary sectional view of the semiconductor integrated circuit device during the manufacturing process following FIG. FIG. 14 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during the manufacturing process following FIG. 13, and FIG. 15 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during the manufacturing process following FIG. 6 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during the manufacturing process following FIG. 15, and FIG. 17 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to another embodiment of the present invention during the manufacturing process. FIG. 18 is a cross-sectional view of a main part of the semiconductor integrated circuit device during the manufacturing process following FIG. 17, and FIG. 19 is a cross-sectional view of a main part of the semiconductor integrated circuit device during the manufacturing process following FIG. FIG. 20 is a cross-sectional view of a main part of the semiconductor integrated circuit device during the manufacturing process following FIG. 1 is a cross-sectional view of a main part of the semiconductor integrated circuit device during the manufacturing process following FIG. 20; FIG. 22 is a cross-sectional view of a main portion of the semiconductor integrated circuit device during the manufacturing process following FIG. 21; Is a circuit diagram of an input protection circuit of a semiconductor integrated circuit device according to another embodiment of the present invention. FIG. 24 is a circuit diagram of an output protection circuit of the semiconductor integrated circuit device according to another embodiment of the present invention. FIG. 25 is a cross-sectional view of a main part of the semiconductor integrated circuit device of FIG. 23, FIG. 26 is a plan view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. XXVII in Figure 26 — Cross-sectional view along line XXVII, Figure 2 FIG. 8 is a cross-sectional view of a main part of an internal circuit region of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 29 is a protection circuit of a semiconductor integrated circuit device according to another embodiment of the present invention. FIG. 30 is a cross-sectional view of a main part of a semiconductor integrated circuit device including the protection circuit of FIG. 29. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

FIG. 4 is a plan view of a semiconductor chip included in the semiconductor integrated circuit device according to the first embodiment. The semiconductor chip 1 is composed of, for example, a semiconductor chip having a rectangular shape in a plane, an internal circuit area A is arranged at the center, and a peripheral circuit area B is arranged at the outer periphery.

In the internal circuit area A, a predetermined logic circuit (semiconductor integrated circuit) such as a microprocessor is formed. In the peripheral circuit area B, for example, an input / output circuit such as an input buffer circuit, an output buffer circuit, or an input / output bidirectional circuit, a protection circuit and a power supply circuit are formed.

A plurality of CCB (Controlled Collapse Bonding) bump electrodes (external terminals) 2 are regularly arranged on the main surface of the semiconductor chip 1. The CCB bump electrode 2 is made of, for example, a lead (Pb) -tin (Sn) alloy, and is electrically connected to elements formed on the semiconductor chip 1 through wiring. Note that, in the internal circuit region A, the CCB bump electrodes 2 for mainly supplying power supply voltage are arranged, and in the peripheral circuit region B, the CCB bump electrodes 2 for signals are arranged.

However, the arrangement states of the internal circuit area A and the peripheral circuit area B are not limited to those shown in FIG. 4 and can be variously changed, and for example, may be as shown in FIG. That is, the rectangular internal circuit area A and the peripheral circuit area B extending vertically in FIG. 5 are alternately arranged along the horizontal direction in FIG. May be placed. In this case, for example, the CCB bump electrode 2 for supplying the power supply voltage on the low potential side is arranged in the internal circuit area A, and the CCB bump electrode 2 for supplying the power supply voltage on the high potential side is disposed in the peripheral circuit area B. CCB bump electrodes 2 for signals and CCB bump electrodes 2 for signals are alternately arranged.

Next, circuit diagrams of the input protection circuit and the output protection circuit formed in the peripheral circuit region B are shown in FIGS. 6 and 7, respectively. In FIGS. 6 and 7, the current I indicates the direction in which the electrostatic current flows.

The input protection circuit 3 shown in FIG. 6 is a circuit for protecting peripheral circuits and internal circuits from static electricity or the like, and has, for example, two diodes D 1 and D 2 and a resistor R.

The diode (first pn junction diode) D 1 is electrically connected between the power supply wiring V C C and the input C C B bump electrode 2 in the opposite direction. The power supply wiring V CC is a high-potential power supply wiring, and is set to, for example, about 0 V.

The diode (second pn junction diode) D 2 is electrically connected in the opposite direction between the input CCB bump electrode 2 and the power supply wiring V EE. The power supply wiring V EE is a low-potential power supply wiring, and is set to, for example, about 12 V.

The resistor R is electrically connected between the input CCB bump electrode 2 and the internal circuit, and is set to, for example, about 100 Ω.

The output protection circuit 4 shown in FIG. 7 is a circuit for protecting peripheral circuits and internal circuits from static electricity and the like, and has, for example, two diodes D 3 and D 4.

The diode (first pn junction diode) D 3 is electrically connected between the power supply wiring V C C and the output C C B bump electrode 2 in the opposite direction. The diode (second pn junction diode) D 4 is electrically connected between the output CCB bump electrode 2 and the power supply wiring V EE in the opposite direction.

Next, a plan view of the input protection circuit 3 is shown in FIG. Figure 3 FIG. 1 shows a cross-sectional view taken along the line II of FIG. Fig. 2 shows a cross-sectional view of the main part of the internal circuit area A. In FIG. 3, some hatchings are added to make the drawing easier to see.

In the first embodiment, as shown in FIG. 1 and FIG. 2, an S 0 I substrate 5 is used as an element formation substrate constituting the semiconductor chip 1. The SOI substrate 5 includes a semiconductor substrate 5a, an insulating layer 5b formed thereon, and a semiconductor layer 5c formed thereon.

The semiconductor substrate 5a is a supporting substrate component mainly for securing the strength of the SOI substrate 5, and is made of, for example, n-type silicon (Si) single crystal. Insulating layer 5 b is made of, for example, silicon dioxide (S i 0 _2), has a thickness of, for example 5 0 0 OA about.

In the first embodiment, only the region directly below the pn junction surface of the input protection circuit diodes D 1 and D 2 in the insulating layer 5 b is partially removed. That is, in a region immediately below the pn junction surface, the semiconductor layer 5c and the semiconductor substrate 5a are in physical contact with each other. As a result, in the semiconductor integrated circuit device according to the first embodiment, the following can be performed.

First, the heat generated when the diodes D1 and D2 break down can be released to the supporting semiconductor substrate 5a through the removed area of the insulating layer 5b. It is possible to improve the heat dissipation.

Secondly, the current flowing through the diodes D 1 and D 2 due to static electricity or the like can be released to the supporting semiconductor substrate 5 a through the removed area of the insulating layer 5 b, and the current flows to the diodes D 1 and D 2. Since the concentration of the electric field can be prevented, it is possible to improve the electrostatic breakdown resistance of the diodes D 1 and D 2. Arrow C in FIG. 1 schematically shows an escape route for heat or electrostatic current.

Third, the removal of the insulating layer 5b of the SOI substrate 5 only partially Since the insulating layer 5b is left in this region, the above-mentioned effects can be obtained without causing a large increase in the diffusion capacitance or the wiring-substrate capacitance.

Fourth, since the insulating layer 5b of the SOI substrate 5 is only partially removed and the insulating layer 5b is left in other regions, a large step occurs in the upper semiconductor layer 5c. Not even. Therefore, it is possible to prevent the occurrence of a defect such as a disconnection of the wiring due to the step of the base.

The semiconductor layer 5c is a substrate component for element formation, and is made of, for example, an n-type Si single crystal, and has a thickness of, for example, about 1 to 2 / m. At a predetermined position above the semiconductor layer 5c, a field insulating film 6a for isolation and a trench isolation portion 6b are formed.

Field insulating film 6 a is composed of, for example, S i 0 _2. Also, train Chi separating unit 6 b is in the dug to the extent that the upper surface of the field insulating film 6 b reaching a portion of the insulating layer 5 b groove, an insulating film is padded made of, for example, S i 0 ₂ It is formed.

The diode D 1 includes an n ^{+ -type} buried region 7 a 1, an n + -type lead-out region 7 b 1, an IT-type semiconductor region 7 c 1, and a p + -type semiconductor region (first p-type semiconductor region) 7 d 1.

The n + -type buried region 7a1 is made of, for example, an n + -type Si single crystal, and is formed in the lowermost layer of the semiconductor layer 5c. The n + -type lead region 7 b 1 is formed so as to extend from the upper surface of the semiconductor layer 5 c to the n + -type buried region 7 a 1, and has a connection hole 9 formed in the insulating film 8 on the SOI substrate 5. It is electrically connected to wiring 10a through a.

The wiring 10a is made of, for example, an aluminum (A 1) —Si—copper (Cu) alloy, and is electrically connected to, for example, a power supply wiring V CC. As shown in FIG. 3, the wiring 10a and the connection hole 9a are arranged so as to surround the periphery of the p + type semiconductor region 7d1.

The II-type semiconductor region 7 c 1 is made of, for example, an η-type Si single crystal formed by an epitaxial method, and is formed on the n + -type buried region 7 a 1. Have been. For example, the n-type buried region 7a1, the n + -type lead region 7b1, and the IT-type semiconductor region 7c1 are doped with an n-type impurity such as phosphorus or arsenic (As).

Above the n-type semiconductor region 7 c 1, a p + type semiconductor region (first p-type semiconductor region) 7 d 1 is formed, and the p + type semiconductor region 7 d 1 and the n− type semiconductor region are formed. The main action part of diode D1 is formed at the pn junction with 7c1.

The P + type semiconductor region 7 d 1 is electrically connected to wirings 10 b and 10 c formed independently of each other through connection holes 9 b and 9 c formed in the insulating film 8. The wiring 10b is electrically connected to, for example, an internal circuit. The wiring 10c is electrically connected to the wiring 10d through the connection hole 9d, and further electrically connected to the input CCB bump electrode 2 (see FIG. 4) through the wiring 10a. . The wirings 10b and 10c are made of, for example, an A1-Si-Cu alloy, and are electrically connected to each other through a resistor R made of a p + type semiconductor region 7d1. The size of the diode D 1 including the n + -type lead region 7 b 1 is, for example, about 35 ^ mX 28 ^ m.

The diode D 2 includes an n ^{+ -type} buried region 7 a 2, an n + -type lead-out region 7 b 2, an IT-type semiconductor region 7 c 2, and a p + -type semiconductor region (second p-type semiconductor region) 7 d 2 And

The n + type buried region 7a2 is made of, for example, an n + type Si single crystal, and is formed in the lowermost layer of the semiconductor layer 5c. The n + -type lead-out region 7 b 2 is formed to extend from the upper surface of the semiconductor layer 5 c to the n + -type buried region 7 a 2, and has a connection hole 9 e formed in the insulating film 8 on the SOI substrate 5. Is electrically connected to the wiring 10e through the wire. As shown in FIG. 3, the wiring 10 e and the connection hole 9 e are arranged so as to surround the periphery of the p + -type semiconductor region 7 d 2. The wiring 10 e is made of, for example, A 1—Si—Cu alloy, is electrically connected to the wiring 10 d through the connection hole 9 f, and is further connected to the input CCB bump electrode through the wiring 10 d. 2 (see Fig. 4 etc.).

The n − type semiconductor region 7 c 2 is made of, for example, an IT type Si single crystal formed by an epitaxial method, and is formed on the n + type buried region 7 a 2. For example, phosphorus or As of an n-type impurity is introduced into the n ⁺ buried region 7a2, the n + -type lead region 7b2, and the IT-type semiconductor region 7c2.

A p + type semiconductor region 7 d 2 is formed above the IT type semiconductor region 7 c 2, and a diode is formed at a pn junction between the p + type semiconductor region 7 d 2 and the IT type semiconductor region 7 c 2. The main working part of D2 is formed.

The p + type semiconductor region 7 d 2 is electrically connected to the wiring 10 f through a connection hole 9 g formed in the insulating film 8. The wiring 10 f is made of, for example, an A 1 -Si—Cu alloy, and is electrically connected to, for example, a power supply wiring V EE. Note that the size of the diode D 2 including the n + -type extraction region 7 b 2 is, for example, about 28 / .rnX 22 m. The insulating film 8 is made of, for example, a PSG (Phospho Silicate Glass) film.

On the other hand, in the internal circuit formation region, as shown in FIG. 2, for example, a vertical npn bipolar transistor (hereinafter, referred to as npn transistor) 11, a p-channel MOS transistor (hereinafter, referred to as pMOS) 12, An n-channel type MOS transistor (hereinafter referred to as nMOS) 13 is formed.

The pMOS 12 and the nMOS 13 form a CMOS circuit, and the CMOS circuit and the npn transistor 11 form a BiC-MOS (Bipolor C-MOS) circuit.

The npn transistor 11 includes a collector buried region 11a, a base region 11c formed above the n ゥ well 11b thereon, and an emitter region 11d formed in the upper center of the base region 11c. have. The n ^{+ -type} collector buried region 11a has, for example, phosphorus or As of an n-type impurity introduced therein. The collector electrode 14c is formed through the collector bow I-exposed region 1If formed in the n-type well 11b. Electrically connected to I have. The collector electrode 14 c has, for example, a _c base region 11 c made of an A 1 -Si—Cu alloy, and surrounds a central intrinsic base region 11 c 1 and an emitter region 11 d above it. And the base drawer area 1 1 c 2 arranged as follows.

For example, P-type impurity boron is introduced into the intrinsic base region 11c1 and the base extraction region 11c2. However, the impurity concentration of the base extraction region 11c2 is set higher than that of the intrinsic base region 11c1.

The base extraction region 11c2 is electrically connected to the base electrode 14b2 via the base extraction electrode 14b1. The base extraction electrode 14 b 1 is made of, for example, low-resistance polysilicon, and the base electrode 14 b 2 is made of, for example, an A 1 -S i -Cu alloy.

The emitter region 11 d has, for example, n-type impurity phosphorus or As introduced therein, and is electrically connected to the emitter electrode 14 e 2 via the emitter extraction electrode 14 el. The emitter extraction electrode 14 e 1 is made of, for example, low-resistance polysilicon, and the emitter electrode 14 e 2 is made of, for example, an A 1 -Si—Cu alloy.

The pMOS 12 includes a pair of source region 12a and drain region 12b formed above the semiconductor layer 5c, a gate oxide film 12c formed on the semiconductor layer 5c, and It has a gate electrode 12d formed thereon.

The source region 12 a and the drain region 12 b have a structure having a low concentration region 12 a 1, 12 b 1 and a high concentration region 12 a 2, 12 b 2 outside thereof, respectively. I have. The low-concentration regions 12a1 and 12b1 and the high-concentration regions 12a2 and 12b2 contain, for example, boron as a p-type impurity. The source region 12a and the drain region 12b are electrically connected to the source electrode 14s1 and the drain electrode 14d, respectively. The source electrode 14 s 1 and the drain electrode 14 d 1 are made of, for example, an A 1 —S i —Cu alloy. Gate oxide film 1 2 c is made of, for example, S i 0 _2. The gate electrode 1 2 d is formed by Shirisai de layer mosquitoes ^s deposition consisting WS i ₂ like for example the low-resistance poly-silicon layer. Incidentally, the upper and side surfaces of the gate electrode 1 2 d is, for example S i 0 ₂ consists of a cap insulating film 1 5 a and cyclic Dowo - le 1 5 b are formed.

The nMOS 13 includes a pair of a source region 13 a and a drain region 13 b formed on the semiconductor layer 5 c, a gate oxide film 13 c formed on the semiconductor layer 5 c, And a gate electrode 13d formed thereon. It should be noted that boron as a p-type impurity is introduced into the semiconductor layer 5c in the region where the nMOS 13 is formed.

The source region 13a and the drain region 13b consist of low concentration regions 13a1, 13b1 and high concentration regions 13a2, 13b2 outside thereof, respectively. It has the same structure as 12. The low-concentration regions 13a1, 13b1 and the high-concentration regions 13a2, 13b2 contain, for example, n-type impurity phosphorus or As. The source region 13a and the drain region 13b are electrically connected to the source electrode 14s2 and the drain electrode 14d2, respectively. The source electrode 14 s 2 and the drain electrode 14 d 2 are made of, for example, an A 1 —S i —Cu alloy.

A gate oxide film 1 3 c is made of, for example, S i 0 _2. Gate - gate electrode 1 3 d is formed by Shirisai de layer mosquito deposition made of WS i ₂ like for example the low-resistance poly-silicon layer. The upper and side surfaces of the gate one gate electrode 1 3 d, if example embodiment S i 0 ₂ cap insulating film 1 made of 5 a and cyclic Douoru 1 5 b are formed.

On such an SOI substrate 5, FIG. 1 and FIG. 2, example if are S i 0 ₂ made of an insulating film 1 6 force s deposits, which in due connexion Wiring 1 0 a, 1 0 b, 10 e, 10 f, base electrode 14 b 2, emitter electrode 14 e 2, collector electrode 14 c, source electrode 14 s 1, 14 s 2, and drain electrode 14 d 1 , 14 d 2 are coated. Furthermore, the On the insulating film 16, for example, a surface protection film 17 composed of a SiO ₂ film or a laminated film formed by depositing a silicon nitride film on the SiO ₂ film is deposited. The wiring 10d (see Fig. 3) is covered. Next, an example of a method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.

First, as shown in FIG. 8, for example, a photo-resist that covers the removal region of the insulating layer 5b (see FIG. 1) on the main surface of a semiconductor substrate 5a made of, for example, an n-type Si single crystal. Regis Tono ,. Turn 18a is formed by photolithographic techniques.

Subsequently, using the photoresist pattern 18a as a mask, for example, oxygen ions are introduced into the semiconductor substrate 5a by an ion implantation method or the like. The dose at this time is, for example, about 10 ¹⁸ Z cm ² . The acceleration energy is, for example, about 180 keV to 200 keV.

After that, the semiconductor substrate 5a is subjected to a nitrogen annealing treatment at about 130 ° C. to 135 ° C. for about 2 hours to 6 hours, and the region into which oxygen ions are implanted is selectively subjected to S annealing. By changing to i 0 ₂ , as shown in FIG. 9, an insulating layer 5 b having a thickness of, for example, about 500 OA is formed at a predetermined depth position of the semiconductor substrate 5 a, and, for example, A thin semiconductor layer 5 c 1 having a thickness of about 0.1 μm is formed.

Here, in the first embodiment, there is a removed region where the insulating layer 5b is not formed in a part, and the thin semiconductor layer 5c1 and the lower semiconductor substrate 5a are physically and physically in the removed region. It is in contact. The area where the insulating layer 5b is removed is an area where heat, electrostatic current, and the like generated by the input / output protection circuit are released to the semiconductor substrate 5a.

Next, as shown in FIG. 10, after a buried region is formed in the thin semiconductor layer 5c1, a semiconductor layer 5c2 made of, for example, an n-type Si single crystal is formed on the thin semiconductor layer 5c1. Is formed by an epitaxy method. Thereby, the semiconductor layer 5c is formed on the insulating layer 5b, and the SOI substrate 5 is manufactured. Subsequently, as shown in FIG. 11, the upper portion of the semiconductor layer 5 c, for example, S i 0 ₂ consists of the field insulating film 6 a conventional LOCOS (Local Oxidi zation of Silicon Roh, / removed by the cowpea "! Form 9

Thereafter, a groove is formed at a predetermined position of the field insulating film 6a so as to reach the upper portion of the insulating layer 5b, and then an insulating film made of, for example, SiO ₂ is buried in the groove. The separation part 6b is formed.

Next, as shown in FIG. 12, a collector extraction region 11 f is formed in the transistor formation region of the internal circuit region A. The collector extraction region 11f is formed by forming a photoresist pattern so as to cover the region other than that region, and then implanting, for example, phosphorus or As of an n-type impurity into the SOI substrate 5 by ion implantation or the like. And an annealing treatment is performed.

Subsequently, n + -type lead-out regions 7 b 1 and 7 b 2 are formed in the rr semiconductor regions 7 c 1 and 7 c 2 of the input / output protection circuit region in the peripheral circuit region B. After forming a photoresist pattern so as to cover the n + -type extraction regions 7 b 1 and 7 b 2, the SOI substrate 5 is ionized with, for example, n-type impurity phosphorus or As. It is formed by injecting by an injection method or the like and further performing an annealing process.

Thereafter, ρ + type semiconductor regions 7 d 1 and 7 d 2 are formed above the η · semiconductor regions 7 c 1 and 7 c 2 of the input / output protection circuit region in the peripheral circuit region B. In the P + type semiconductor regions 7 d 1 and 7 d 2, after forming a photoresist pattern covering the other regions, ion implantation of, for example, BF _{2 of a} P type impurity into the SOI substrate 5 is performed. It is formed by injecting by a method or the like and further performing an annealing process.

Then, the internal circuit region A, the pMOS 12 and nMOS 13, after forming respectively according the method of forming the conventional M 0 S transistors, as shown in FIG. 13, on SO I substrate 5, for example, from S i 0 ₂ An insulating film 8a is deposited by a CVD method or the like.

Next, the isolation in the base region of the bipolar transistor formation region The edge film 8a is removed by photolithography and dry etching.

Thereafter, a conductive film made of, for example, p-type low-resistance polysilicon is deposited on the S01 substrate 5 by a CVD method or the like, and the conductive film is patterned by photolithography and dry etching to obtain a conductive film. A film 18 is formed.

Next, after an insulating film 8b made of, for example, SiO ₂ is deposited on the SOI substrate 5 by a CVD method or the like, the insulating film 8b and the conductive film 18 in the base region of the bipolar transistor formation region are formed by photolithography. Then, by removing by a dry etching technique, as shown in FIG. 14, a base extraction electrode 14 b 1 is formed and a part of the upper surface of the semiconductor layer 5 c is exposed.

Subsequently, using the insulating film 8b as a mask, for example, BF ₂ ions are introduced into the exposed portions of the semiconductor layer 5c of the SOI substrate 5 by ion implantation or the like. The dose at this time is, for example, about 10 ¹³ Z cm ² , and the acceleration energy is, for example, about 60 keV.

Thereafter, annealing is performed on the SOI substrate 5 to form an intrinsic base region 11 c 1, and then p-type impurities in the conductor film 18 are diffused into the upper portion of the semiconductor layer 5 c. As shown in FIG. 15, a base lead-out region 11 c 2 is formed.

Next, an insulating film made of, for example, SiO ₂ is deposited on the SOI substrate 5 by a CVD method or the like, and the insulating film is etched back to form openings in the insulating film 8 and the conductor film 18. Form insulation film 8c on the side o

Subsequently, a conductive film made of, for example, n-type low-resistance polysilicon is deposited on the S0I substrate 5 by a CVD method or the like, and then the conductive film is patterned by photolithography and dry etching. Thus, an emitter extraction electrode 14 e 1 is formed.

After that, the n-type impurity in the emitter electrode 14 e 1 is removed from the semiconductor layer 5. By diffusing the region above c, an emitter region 11 d is formed above the intrinsic base region 11 c 1.

Next, as shown in FIG. 16, after an insulating film 8 d made of, for example, SiO 2 is deposited on the SOI substrate 5 by a CVD method or the like, a connection hole 19 is formed in the insulating film 8 by photolithography. And drilling by dry etching technology.

Subsequently, after depositing a metal film made of, for example, an A1-Si-Cu alloy on the SOI substrate 5 by a sputtering method or the like, the metal film is patterned by photolithography and dry etching. Thus, wiring 10a, 10b, 10e, 10f, collector electrode 14c, base electrode 14b2, emitter electrode 14e2, source electrodes 14s1, 14s2, and drain electrode 14c then to form a d 1, 14 d 2, as shown in FIGS. 1 and 2, on sO I substrate 5, after the insulating film 1 6 consisting of S i 0 ₂ deposited by CVD method or the like for example, After a wiring forming step, a surface protective film 17 is deposited on the insulating film 16 by a CVD method or the like. Thereafter, the semiconductor integrated circuit device is manufactured according to the normal semiconductor integrated circuit device manufacturing process.

As described above, according to the first embodiment, the following effects can be obtained.

(1) By removing the insulating layer 5 b under the diodes D 1 and D 2, the heat generated when the diodes D 1 and D 2 break down is passed through the region where the insulating layer 5 b is removed. Since the heat can be released to the supporting semiconductor substrate 5a side, the heat radiation of the heat can be improved.

(2) By removing the insulating layer 5b under the diodes D1 and D2, the current flowing through the diodes D1 and D2 due to static electricity or the like can be supported through the removed area of the insulating layer 5b. It can escape to the side of the semiconductor substrate 5a and can prevent the electric field from being concentrated on the diodes D1 and D2. Therefore, the electrostatic damage resistance of the diodes D1 and D2 can be reduced. It can be improved. (3) .Since the insulating layer 5 b of the S 0 I substrate 5 is only partially removed and the insulating layer 5 1) remains in other areas, the diffusion capacitance and the capacitance between the wiring and the substrate are greatly increased. The above-described effect can be obtained without causing a significant increase. Therefore, it is possible to improve the reliability of the semiconductor integrated circuit device without causing a delay in the operation speed of the semiconductor integrated circuit device.

(4) Since the insulating layer 5b of the SOI substrate 5 is only partially removed and the insulating layer 5b is left in other regions, a large step occurs in the upper semiconductor layer 5c. Not even. Therefore, it is possible to prevent the occurrence of a defect such as a disconnection of the wiring caused by the step of the base.

Next, another embodiment 2 of the present invention will be described with reference to FIGS. In the second embodiment, another example of the manufacturing method of the SOI substrate 5 will be described.

First, as shown in FIG. 1 7, for example, the first semiconductor substrate 2 0 on the main surface consisting of n-type S i monocrystal by conventional LOCOS method, a field insulating consisting S i 0 ₂ For example A film 21 is formed. At this time, a removal region without the field insulating film 21 is formed at a predetermined position of the first semiconductor substrate 20.

Subsequently, the main surface of the first semiconductor substrate 20 is polished by a CMP (Chemical Mechanical Polishing) method or the like, as shown in FIG. Flatten. However, in the polishing process at this time, the field insulating film 21 (see FIG. 17) is left above the main surface of the semiconductor substrate 20. Thereby, the insulating layer 5b is formed.

Thereafter, as shown in FIG. 19, the main surface of the first semiconductor substrate 20 and the main surface of the other prepared second semiconductor substrate (supporting semiconductor substrate) 22 were opposed to each other and brought into contact with each other. In this state, the first semiconductor substrate 20 and the second semiconductor substrate are subjected to annealing treatment in an oxygen atmosphere or the like at about 800 ° C. to 110 ° C. for about 2 hours. 2 Laminate with 2. The second semiconductor substrate 22 is made of, for example, an n-type Si single crystal. Next, the back surface of the first semiconductor substrate 20 is etched away by, for example, a dry etching process to form a thin semiconductor layer 5c1, as shown in FIG. 20, and then the same as in the first embodiment. On the thin semiconductor layer 5c1, as shown in FIG. 21, a semiconductor layer 5c2 made of, for example, an n-type Si single crystal is grown by an epitaxy method or the like to form the semiconductor layer 5c. Form.

Subsequently, as in the first embodiment, as shown in FIG. 22, a field insulating film 6 a made of, for example, SiO ₂ is formed on the semiconductor layer 5 c by a LOCOS method or the like. A trench isolation 6b is formed at a predetermined position. Subsequent steps are the same as in the first embodiment, and a description thereof will be omitted.

In the second embodiment, the same effect as in the first embodiment can be obtained.

Next, another embodiment 3 of the present invention will be described with reference to FIGS. FIGS. 23 and 24 show circuit diagrams of the input protection circuit and the output protection circuit formed in the peripheral circuit region of the third embodiment, and FIG. 25 shows a semiconductor integrated circuit including this input protection circuit element. 1 shows a cross-sectional view of a main part of a circuit device.

In the third embodiment, the electrostatic protection element constituting the protection circuit is constituted by MOS transistors Q1 to Q4 functioning as diodes.

The MOS transistor (first MIS transistor) Q1 of the input protection circuit 3 is connected to the power supply wiring V CC and the input CCB bump electrode 2 with its gate electrode connected to the power supply wiring V CC. And a diode connection. The M 0 S transistor (second MIS transistor) Q 2 is connected between the power supply wiring V EE and the input CCB bump electrode 2 with its gate electrode connected to the power supply wiring V EE. Diode connected.

MOS transistor of output protection circuit 4 (first MIS transistor E) Q3 is electrically connected between the power supply wiring V CC and the output CCB bump electrode 2 with its gate electrode connected to the power supply wiring V CC. The MOS transistor (second MIS transistor) Q4 is electrically connected between the output CCB bump electrode 2 and the power supply wiring VEE with its gate electrode connected to the power supply wiring VEE. Connected.

Next, a cross-sectional view of the input protection circuit 3 is shown in FIG. FIG. 25 shows only the MOS transistor Q1 described above, but the MOS transistors Q2 to Q4 have basically the same structure.

The above-mentioned MOS transistor Q1 is composed of a pair of source region (first n-type semiconductor region) 24a and a drain region provided separately from each other above a semiconductor layer 5c made of, for example, a p-type Si single crystal. (First n-type semiconductor region) 24 b, a gate insulating film 24 c composed of an insulating film 8 on the semiconductor layer 5 c, and a gate electrode 24 d disposed on the insulating film 8 And

The source region 24a and the drain region 24b are doped with, for example, an n-type impurity such as phosphorus or As to form the source region 13a and the drain region 13b of the nMOS 13 of the internal circuit. Sometimes formed at the same time. A channel region is formed between the source region 24a and the drain region 24b.

The gate electrode 24 d is made of, for example, A 1 -Si—Cu alloy, and has a collector electrode 14 c base electrode 14 b 2, an emitter electrode 14 e 2, a source electrode 14 s 1, It is formed simultaneously when 14 s 2 and the drain electrodes 14 d 1 and 14 d 2 are formed.

In the third embodiment as well, the insulating layer 5b immediately below the channel region of the MOS transistor Q1 for the electrostatic protection element is removed. As a result, also in the third embodiment, the same effect as that obtained in the first embodiment can be obtained.

Next, another embodiment 4 of the present invention will be described with reference to FIGS. You. In the fourth embodiment, since the configuration of the semiconductor chip, the circuit configuration of the protection circuit, and the method of manufacturing the SOI substrate are the same as those in the first and second embodiments, the description will be omitted.

FIG. 27 shows a plan view of the input protection circuit 3 of the fourth embodiment and a cross-sectional view taken along line XXVII-XXVII of the input protection circuit 3. Fig. 28 shows a cross-sectional view of the main part of the internal circuit area A (see Fig. 4 etc.). Note that FIG. 26 is partially hatched to make the drawing easier to see.

In the fourth embodiment, as shown in FIG. 2 6 and 2 7 is similar SOI substrate 5 ^force? Using the first embodiment as the element forming substrate constituting the semi-conductor chip 1. The SOI substrate 5 includes a semiconductor substrate 5a, an insulating layer 5b formed thereon, and a semiconductor layer 5c formed thereon.

The semiconductor substrate 5a is a supporting substrate component that mainly secures the strength of the SOI substrate 5, and is made of, for example, n-type silicon (Si) single crystal. Insulating layer 5 b is made of, for example, silicon dioxide (S i 0 _2), has a thickness of, for example 5 0 0 OA about.

In the fourth embodiment, only the region directly below the pn junction surface of the diodes D 1 and D 2 for the input protection circuit in the insulating layer 5 b is partially removed. That is, in a region immediately below the pn junction surface, the semiconductor layer 5c and the semiconductor substrate 5a are in a state of being in physical contact with each other. As a result, the semiconductor integrated circuit device according to the fourth embodiment enables the following first to fourth operations.

Second, the current flowing through the diode D 1, D 2 by the static electricity or the like, can also Nigasuko and force ^s on the semiconductor substrate 5 a side of the supporting through removal region of the insulating layer 5 b, Daio one de D 1, It can prevent the electric field from concentrating on D2 Therefore, it is possible to improve the electrostatic breakdown resistance of the diodes D 1 and D 2. Arrow C in FIG. 1 schematically shows an escape route for heat or electrostatic current.

Third, since the insulating layer 5b of the SOI substrate 5 is only partially removed and the insulating layer 5b is left in other regions, the diffusion capacitance and the wiring / substrate capacitance are greatly increased. The above-mentioned effects can be obtained without inviting.

The semiconductor layer 5 Ho, a substrate structure of the element formation, for example, an n-type S i monocrystalline, its thickness is thinner than the first to third embodiments, preferably, for example, 0.1 _lambda m It is about.

At a predetermined position above the semiconductor layer 5c, a field insulating film 6a for isolation is formed. The field insulating film 6 a is made of, for example, S i 0 _2, its bottom is in contact insulating layer 5 as shown in FIG. 2 7 and 2 8.

Incidentally, in the protection circuit region, the field insulating film 6 c which is arranged inside the field insulating film 6 a, for example, an insulating film S i 0 ₂ consists of elements in the separation. The field insulating film 6c does not have a bottom portion in contact with the insulating layer 5b, and a semiconductor layer is interposed therebetween.

The diode D 1 for the input protection circuit shown in FIGS. 26 and 27 is composed of an n + -type lead region 7 b 1, an rr -type semiconductor region 7 c 1 surrounded by this region, and a p + Semiconductor region (first p-type semiconductor region) 7 d 1.

In the diode D1 of the fourth embodiment, the diffusion capacitance of the diode D〗 can be reduced by the absence of the η + buried region 7a1 described in the first embodiment. I have. The n + -type extraction region 7 b 1 contains, for example, an n-type impurity such as phosphorus or As, and extends so that the bottom reaches the insulating layer 5 b. The n ⁺ -shaped lead region 7 b 1 is electrically connected to the wiring 10 a through a connection hole 9 a formed in the insulating film 8 on the SOI substrate 5.

The wiring 10a is made of, for example, an aluminum (A 1) —Si—copper (Cu) alloy, and is electrically connected to, for example, a power supply wiring V CC. As shown in FIG. 26, the wiring 10a and the connection hole 9a are arranged so as to surround the periphery of the p + -type semiconductor region 7d1.

The IT-type semiconductor region 7 c 1 is formed by introducing n-type impurity phosphorus or As into an IT-type Si single crystal formed by, for example, an epitaxy method, and the center of the bottom is a supporting semiconductor substrate. Physical contact with 5a.

The p + -type semiconductor region (first p-type semiconductor region) 7 d1 contains, for example, p-type impurity boron, and the p + -type semiconductor region 7 d 1 and the rr -type semiconductor region 7 c 1 The main working part of the diode D1 is formed at the pn junction of FIG.

The P + type semiconductor region 7 d 1 is electrically connected to wirings 10 b and 10 c formed independently of each other through connection holes 9 b and 9 c formed in the insulating film 8. .

The wiring 10b is electrically connected to, for example, an internal circuit. The wiring 10c is electrically connected to the wiring 10d through the connection hole 9d, and is further electrically connected to the input CCB bump electrode through the wiring 10a. The wirings 10b and 10c are made of, for example, A1-Si-Cu alloy, and are electrically connected to each other through a resistor R composed of ap + type semiconductor region 7d1. . The size of Daiodo D 1 including the n + type extraction region 7 bl is, for example, ₃ 5 m X 2 8 Λ m extent.

The diode D 2 for the input protection circuit is composed of an n + -type lead region 7 b 2, an n − -type semiconductor region 7 c 2 surrounded by the n + -type lead region 7 b 2, and a p + -type semiconductor Body region (second p-type semiconductor region) 7 d 2.

In the diode D2 of the fourth embodiment, the diffusion capacity of the diode D2 can be reduced by the absence of the n + buried region 7a2 described in the first embodiment. .

The n + -type extraction region 7b2 contains, for example, phosphorus or As of an n-type impurity, and extends so that the bottom reaches the insulating layer 5b. The n + -type lead region 7b2 is electrically connected to the wiring 10e through a connection hole 9e formed in the insulating film 8 on the SOI substrate 5.

As shown in FIG. 26, the wiring 10e and the connection hole 9e are arranged so as to surround the p + type semiconductor region 7d2. The wiring 10 e is made of, for example, an A 1 -Si i-Cu alloy, is electrically connected to the wiring 10 d through the connection hole 9 f, and furthermore, is connected to the input CCB bump through the wiring 10 d. It is electrically connected to the electrodes.

The n-type semiconductor region 7c2 is formed, for example, by introducing n-type impurity phosphorus or As into a Si single crystal formed by an epitaxy method.

The p + type semiconductor region 7 d 2 contains, for example, boron as a p-type impurity, and the main function of the diode D 2 is formed at the pn junction between the p + type semiconductor region 7 d 2 and the η type semiconductor region 7 c 2. A part is formed.

The p + type semiconductor region 7 d 2 is electrically connected to the wiring 10 f through a connection hole 9 g formed in the insulating film 8. The wiring 10 f is made of, for example, an A 1 Si—Cu alloy, and is electrically connected to, for example, a power supply wiring V EE. Note that the size of the diode D2 including the n + -shaped extraction region 7b2 is, for example, about 28 m × 22 m. The insulating film 8 is made of, for example, a PSG (Phospho Silicate Glass) film.

On the other hand, in the internal circuit formation region, for example, pM〇S 12 and nMOS 13 are formed as shown in FIG. The pMOS 12 and the nMOS 13 form a CM〇S circuit. The pMOS 12 is formed on a pair of the source region 12 a and the drain region 12 b formed on the semiconductor layer 5 c and on the semiconductor layer 5 c. It has a gate oxide film 12c and a gate electrode 12d formed thereon.

The source region 12a and the drain region 12b have a structure having low concentration regions 12a1 and 12b1 and high concentration regions 12a2 and 12b2 outside thereof. The low-concentration regions 12a1, 12b1 and the high-concentration regions 12a2, 12b2 contain, for example, p-type impurity boron.

The bottoms of the high-concentration regions 12a2 and 12b2 of the source region 12a and the drain region 12b are formed to reach the insulating layer 5b. Thus, the structure (diffusion capacitance) between the source region 12a and the drain region 12b of the pMOS 12 and the semiconductor substrate 5a can be significantly reduced. This is for the following reasons.

Generally, the diffusion capacity of a MOS FET formed on a normal semiconductor substrate is given by the series connection of the gate insulating film capacity and the depletion layer capacity.

On the other hand, in a MOS FET formed on an S〇I substrate, when the source region and the drain region are formed so as to reach the insulating layer 5b, the depletion layer capacitance is caused by complete depletion of the semiconductor layer 5c. Instead, the effect of the capacitance due to the insulating layer 5b becomes significant. That is, in the MOS FET on the SOI substrate, the diffusion capacitance is determined by the capacitance of the insulating layer 5b.

By the way, the dielectric constant of Si is 12, whereas the dielectric constant of Si 0 ₂ is 4, which is 1/3 of the dielectric constant of Si. Can reduce the diffusion capacitance (determined by the capacitance of the insulating layer 5b) to about 1/10 of the diffusion capacitance (determined by the pn junction capacitance) of the M0S • FET formed on a normal semiconductor substrate. It becomes possible.

This can be said to be compared with the pMOS 12 (see FIG. 2) described in the first embodiment and the like. That is, in the structure of the pMOS 12 of the fourth embodiment, a semiconductor layer as shown in the structure of the first embodiment and the like is interposed under the source region 12a and the drain region 12b. Since it does not exist, the diffusion capacity can be lower than that of pMOS 12 described in the first embodiment and the like.

The source region 12a and the drain region 12b of the pMOS 12 are electrically connected to the source electrode 14s1 and the drain electrode 14d1, respectively. The source electrode 14 s 1 and the drain electrode 14 d 1 are made of, for example, an A 1 —S i —Cu alloy.

Gate - gate oxide film 12 c is made of, for example, S i 0 _2. Gate electrode 12 d is Shirisai de layer made of WS i ₂ etc., which are deposited for example on a low resistance polysilicon layer. Incidentally, the upper and side surfaces of the gate electrode 12 d, for example S i 0 ₂ consists of a cap insulating film 1 5 a and cyclic Dowo Lumpur 15 b are formed.

The nMOS 13 is formed on a pair of the source region 13a and the drain region 13b formed on the semiconductor layer 5c, the gate oxide film 13c formed on the semiconductor layer 5c, and formed thereon. Gate electrode 13d. It should be noted that boron as a P-type impurity is introduced into the semiconductor layer 5c in the region where the nMOS 13 is formed.

The source region 13a and the drain region 13b are composed of low-concentration regions 13a1 and 13b1 and high-concentration regions 13a2 and 13b2 outside thereof, respectively, and have a structure similar to that of the pMOS 12. I have. The low-concentration regions 13a1, 13b1 and the high-concentration regions 13a2, 13b2 contain, for example, n-type impurity phosphorus or As.

The bottoms of the high-concentration regions 13a2 and 13b2 of the source region 13a and the drain region 13b are also formed to reach the insulating layer 5b. Thus, the structure (diffusion capacitance) between the source region 13a and the drain region 13b of the nMOS 13 and the semiconductor substrate 5a can be significantly reduced. In the structure of the nMOS 13 of the fourth embodiment, the semiconductor layer shown in the structure of the first embodiment and the like is not interposed under the source region 13a and the drain region 13b. The diffusion capacitance is larger than that of the nMOS 13 described in the first embodiment. It is possible to lower. The reasons for these are the same as in the above pMOSl2, and will not be described.

Such a source region 13a and a drain region of the nMOS 13

13b is electrically connected to the source electrode 14s2 and the drain electrode 14d2, respectively. Source electrode 14 s 2 and drain electrode

14 d2 is made of, for example, an A1-Si-Cu alloy.

A gate oxide film 13 c is made of, for example, S i 0 _2. Gate - gate electrode 13 d is formed by Shirisai de layer power deposition made of WS i ₂ like for example the low-resistance poly-silicon layer. On the upper layer and the side surface of the gate electrode 13d, for example, a cap insulating film 15a made of SiO ₂ and a sidewall 15b are formed.

Or SO I on the substrate 5, such as, as shown in FIGS. 27 and 28, for example, S i 0 ₂ made of an insulating film 16 ^force? Are deposited, that this shall wiring 10 a, 10 b, 10 e, 10 f, source electrodes 14 sl, 14 s 2 and drain electrodes 14 d 1, 14 d 2 are coated. Further, on the insulating film 16, for example, a SiO ₂ film or a surface protective film 17 formed by depositing a silicon nitride film on the SiO ₂ film is deposited, thereby forming the wiring 10d ( See Fig. 26).

As described above, in the fourth embodiment, in addition to the effects obtained in the first embodiment, the following effects can be obtained.

(1) Since the diffusion capacities of the pMOS 12 and the nMOS 13 in the internal circuit area can be reduced as compared with the first embodiment, the gate input capacity of the pMOS 12 and the nMOS 13 can be reduced, and the pMOS 1 It is possible to improve the switching characteristics of the CMOS circuit composed of the NMOS 2 and the nMOS 13.

(2) Since the diffusion capacitance of the diodes D 1 and D 2 for the protection circuit can be reduced as compared with the first embodiment, the overall diffusion capacitance of the semiconductor integrated circuit device can be reduced. .

(3) According to the above (1) and (2), the operation speed of the semiconductor integrated circuit device can be improved. It becomes possible.

Next, another embodiment 5 of the present invention will be described with reference to FIGS. In the fifth embodiment, since the configuration of the semiconductor chip, the circuit configuration of the protection circuit, and the method of manufacturing the SOI substrate are the same as those in the first and second embodiments, description thereof will be omitted.

FIG. 29 shows a circuit diagram of the input protection circuit according to the fifth embodiment. In the fifth embodiment, the input protection circuit has three elements, two diode-connected MOS transistors (first MIS transistors) Q5 and MOS transistors (second MIS transistors) Q6.

The MOS transistor Q5 of the input protection circuit 3 is electrically connected between the power supply wiring V CC and the output CCB bump electrode 2 with its gate electrode connected to the power supply wiring V CC. ing.

The MOS transistor Q6 is electrically connected between the output CCB bump electrode 2 and the power supply wiring VEE with its gate electrode connected to the power supply wiring VEE.

Next, FIG. 30 shows a cross-sectional view of a main part of a semiconductor integrated circuit device including such an input protection circuit 3. FIG. 30 shows an input protection circuit on the left side and an internal circuit on the right side. The internal circuit is the same as that of the fourth embodiment, and the description is omitted.

In the fifth embodiment, the insulating layer 5b immediately below the channel region of the MOS transistors Q5 and Q6 forming the input protection circuit 3 is removed. Therefore, the same effect as in the first embodiment can be obtained.

Each of the MOS transistors Q5 and Q6 is, for example, an n-channel type MOS transistor, and has semiconductor regions 25A and 26A and source regions (first n-type semiconductor region and second n-type semiconductor region) 25a. , 26a and drain regions (first n-type semiconductor region, second n-type semiconductor region) 25b, 26b, gate oxide films 25c, 26c, and gate electrodes 25d, 26d And The source regions 25a, 26a and the drain regions 25b, 2b The region between 6 b is the channel region.

The source region 25a, 26a and the drain region 25b, 26b are respectively a low concentration region 25a1, 25b1, 26a1, 26b1 and a high concentration region 25a2. , 25b2,26a2,26b2. The low-concentration region 25 a 1,25 b 1,26 a 1,26 b 1 and the high-concentration region 25 a 2,25 b 2,26 a 2,26 b 2 include, for example, n-type impurity phosphorus or A s is contained.

The bottoms of the high-concentration regions 25a2, 25b2, 26a2, 26b2 in the source regions 25a, 26a and the drain regions 25b, 26b are such that they reach the insulating layer 5b. Is formed. Therefore, according to the fifth embodiment, the diffusion capacitance of the MOS transistors Q5 and Q6 for the input protection circuit can be reduced for the same reason as in the pMOS 12 of the fourth embodiment (see FIG. 28). Is possible.

The source region 25a, 26a and the drain region 25b, 26b of such M〇S transistors Q5, Q6 are respectively connected to the source electrode 14s3, 14s4 and the drain electrode 14d3, 14d. It is electrically connected to d4. The source electrodes 14 s 3, 14 s 4 and the drain electrodes 14 d 3, 14 d 4 are made of, for example, an A 1 —Si—Cu alloy.

Then, the source electrode 14 s 3 of the MOS transistors Q 5 and Q 6 and the drain electrode 14 d 4 are electrically connected by a wiring 10 g. The wiring 10 g is made of, for example, an A 1 -Si-Cu alloy.

Gate one gate oxide film 2 5 c, 26 c are made of, for example, S i 0 _2. The gate electrodes 25 d and 26 d are formed by depositing a silicide layer made of WSi ₂ or the like on a low-resistance polysilicon layer, for example. The upper and side surfaces of the gate one gate electrode 2 5 d, 26 d, for example, S I_〇 ₂ consisting cap insulating film 1 5 a and cyclic Douoru 1 5 b are formed.

As described above, according to the fifth embodiment, the following effects can be obtained.

(1) .The lower insulating layer 5b of the MOS transistors Q5 and Q6 for the protection circuit By the removal, the heat generated when the MOS transistors Q5 and Q6 break down can be released to the supporting semiconductor substrate 5a through the removed area of the insulating layer 5b. This makes it possible to improve the heat dissipation.

(2). By removing the insulating layer 5b under the MOS transistors Q5 and Q6 for the protection circuit, the current flowing through the MOS transistors Q5 and Q6 due to static electricity and the like is removed. It is possible to escape to the supporting semiconductor substrate 5a side through the region, and it is possible to prevent the electric field from being concentrated on the MOS transistors Q5 and Q6. It is possible to improve the electrostatic breakdown resistance.

(3) Since the insulating layer 5b of the SOI substrate 5 is only partially removed and the insulating layer 5b is left in other regions, the diffusion capacitance and the wiring-substrate capacitance are greatly increased. The above-mentioned effect can be obtained without inviting.

(4) Since the diffusion capacity of the pMOS 12 and the nMOS 13 in the internal circuit area can be reduced as compared with the first embodiment, the gate input capacity of the pMOS 12 and the nMOS 13 can be reduced. It is possible to improve the switching characteristics of the CMOS circuit composed of 12 and nMOS 13.

(5) Since the diffusion capacitance of the MOS transistors Q5 and Q6 for the protection circuit can be reduced as compared with the first embodiment, the overall diffusion capacitance of the semiconductor integrated circuit device can be reduced.

(6) According to the above (3) to (5), the operation speed of the semiconductor integrated circuit device can be improved.

(7). Since the insulating layer 5b of the SOI substrate 5 is only partially removed and the insulating layer 5b is left in other regions, a large step is formed in the upper semiconductor layer 5c. It does not occur. Therefore, it is possible to prevent the occurrence of a defect such as a disconnection of the wiring caused by the step of the base.

(8) According to the above (1) to (7), it is possible to improve the operation speed of the semiconductor integrated circuit device while securing the reliability of the semiconductor integrated circuit device. As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the first to fifth embodiments and can be variously modified without departing from the gist thereof. Needless to say,

For example, in the first embodiment, the case where a diode is used as an electrostatic protection element has been described. However, the present invention is not limited to this. For example, the electrostatic protection element may be configured by a lateral bipolar transistor. .

Further, in the second embodiment, the force described in the case of using the L 0 C 0 S method and the polishing method as a method of forming the insulating layer on the first semiconductor substrate is not limited to this. Instead, various changes can be made. For example, the following may be performed.

That is, first, oxygen ions are introduced into a predetermined plane position of the first semiconductor substrate by an ion implantation method, and then an annealing process is performed on the semiconductor substrate to insulate only the oxygen ion introduction region in the semiconductor substrate. The layers are selectively formed. Subsequently, the upper surface of the semiconductor substrate is etched and removed by a dry etching method or the like until the upper portion of the insulating layer 5b is exposed, thereby forming a first semiconductor substrate provided with an insulating layer on the upper portion.

In the above description, the power described mainly when the invention made by the present inventor is applied to a semiconductor integrated circuit device having a microprocessor, which is the application field behind it, is not limited to this. For example, the present invention is applied to other semiconductor integrated circuit devices having a memory circuit such as DRAM (Dynamic Random Access Memory), SRAM (Static RAM) or other semiconductor integrated circuit devices such as SRAM with logic. It is also possible. Industrial applicability

As described above, the semiconductor integrated circuit device and the method of manufacturing the same according to the present invention For example, the present invention is suitable for use in a semiconductor integrated circuit device incorporated in a small electronic device such as a mobile communication device, an electronic computer or a video camera, and a method of manufacturing the same.

Claims

Range of request

1. An S0I substrate having a supporting semiconductor substrate and an element forming semiconductor layer provided thereon with an insulating layer interposed therebetween, and an external terminal for leading an electrode of the element to the upper layer of the semiconductor layer. A semiconductor integrated circuit device provided, comprising: an element for a protection circuit electrically connected to the external terminal on an insulating layer removal region in which the insulating layer is partially removed from the semiconductor layer for element formation. And a semiconductor integrated circuit device.

2. The semiconductor integrated circuit device according to claim 1, wherein the protection circuit comprises:

(a) a first p η junction diode electrically connected in a reverse direction between the external terminal and a high power supply potential;

(b) a second pn junction diode electrically connected between the external terminal and a reference potential in a reverse direction.

3. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor substrate is made of silicon single crystal, the insulating layer is made of silicon dioxide, and the semiconductor layer for forming the element is made of n-type silicon single crystal, The first pn junction diode is formed in a junction region between the semiconductor layer for element formation and a first p-type semiconductor region formed on the semiconductor layer immediately above the insulating layer removed region, and The second pn junction diode is formed in a junction region between the semiconductor layer for element formation and a second p-type semiconductor region formed on the semiconductor layer immediately above the insulating layer removal region. Semiconductor integrated circuit device.

4. The semiconductor integrated circuit device according to claim 3, wherein an n-type lead region connected to the n-type semiconductor layer of the first pn junction diode and the second pn junction diode has a bottom portion. A semiconductor integrated circuit device provided so as to be in contact with the insulating layer.

5. The semiconductor integrated circuit device according to claim 4, wherein a pair of semiconductor regions for a source / drain region of an MIS transistor constituting an internal circuit of the semiconductor integrated circuit are provided such that bottom portions thereof are in contact with the insulating layer. And a semiconductor integrated circuit device.

6. The semiconductor integrated circuit device according to claim 1, wherein the protection circuit comprises:

(a) a first MIS transistor diode-connected in a reverse direction between the external terminal and a high power supply potential;

(b) A semiconductor integrated circuit device having a second MIS transistor which is diode-connected between the external terminal and a reference potential in a reverse direction.

7. The semiconductor integrated circuit device according to claim 6, wherein the semiconductor substrate is made of silicon single crystal, the insulating layer is made of silicon dioxide, and the semiconductor layer for forming the element is made of n-type silicon single crystal, The first MIS transistor is formed between a pair of first n-type semiconductor regions formed apart from each other on the element-forming semiconductor layer, and between the pair of first n-type semiconductor regions. A channel region formed above the semiconductor layer for element formation immediately above the insulating layer removed region, a gate insulating film formed on the channel region, and a gate insulating film formed on the gate insulating film. A gate electrode, wherein the second MIS transistor includes a pair of second n-type semiconductor regions formed above and separated from each other on the element-forming semiconductor layer; and a pair of second n-type semiconductor regions. Semiconductor territory A channel region formed between and above the element forming semiconductor layer immediately above the insulating layer removed region; a gate insulating film formed on the channel region; And a gate electrode formed on the gate insulating film.

8. The semiconductor integrated circuit device according to claim 7, wherein the first n-type semiconductor region of the first MIS transistor and the second n-type semiconductor region of the second MIS transistor have their bottom portions in contact with the insulating layer. A semiconductor integrated circuit device characterized by being provided as described above.

9. The semiconductor integrated circuit device according to claim 8, wherein a pair of semiconductor regions for a source / drain region of an MIS transistor constituting an internal circuit of the semiconductor integrated circuit are provided so that bottom portions thereof are in contact with the insulating layer. And a semiconductor integrated circuit device.

10. The semiconductor integrated circuit device according to claim 1, wherein one end of the protection circuit is electrically connected to a bump electrode forming the external terminal formed on a semiconductor layer for element formation via an insulating film. And the other end is electrically connected to an internal circuit constituting the semiconductor integrated circuit.

11. The semiconductor integrated circuit device according to claim 1, wherein a pair of semiconductor regions for a source and a drain region of an MIS transistor constituting an internal circuit of the semiconductor integrated circuit are provided such that bottom portions thereof are in contact with the insulating layer. A semiconductor integrated circuit device characterized by the above-mentioned.

12. The semiconductor integrated circuit according to claim 1, wherein a bipolar transistor and an MIS transistor are provided as elements constituting an internal circuit of the semiconductor integrated circuit in the semiconductor layer for element formation. apparatus.

13. An S0I substrate having a supporting semiconductor substrate and an element-forming semiconductor layer provided thereon with an insulating layer interposed therebetween, wherein an element is formed on the element-forming semiconductor layer. A semiconductor integrated circuit device provided with an external terminal from which an electrode is drawn out, the insulating layer partially removing the insulating layer below a protection circuit element electrically connected to the external terminal. A semiconductor integrated circuit device having a removal area.

14. The method for manufacturing a semiconductor integrated circuit device according to claim 1,

(a) selectively introducing oxygen ions at a predetermined depth and a planar position of the supporting semiconductor substrate,

(b) performing heat treatment on the supporting semiconductor substrate to form the insulating layer in the oxygen ion introduction region and to form the semiconductor layer on the main surface side of the semiconductor substrate. Process and

(C) forming a protection circuit element on the element formation semiconductor layer on the insulating layer removed region where the insulating layer is not formed. Method.

15. The method of manufacturing a semiconductor integrated circuit device according to claim 1,

(a) forming an insulating layer having a partially removed region on at least one surface of the first semiconductor substrate;

(b) After the surface of the first semiconductor substrate on which the insulating layer is formed and the predetermined surface of the second semiconductor substrate prepared separately are brought into contact with each other and brought into contact with each other, the two semiconductor substrates are bonded together. The process of

(c) forming a semiconductor layer for element formation by removing a back surface of the first semiconductor substrate or the second semiconductor substrate;

(d) forming a protection circuit element on the element formation semiconductor layer on the insulation layer removed area where the insulation layer is not formed. Method.