WO2000067463A1

WO2000067463A1 - Method of transferring power across an isolation barrier

Info

Publication number: WO2000067463A1
Application number: PCT/US2000/011468
Authority: WO
Inventors: Frank Sacca; Guang-Ming Yin; Faouzi Chaahoub
Original assignee: Conexant Systems, Inc.
Priority date: 1999-04-30
Filing date: 2000-04-29
Publication date: 2000-11-09

Abstract

An efficient method and circuitry for transferring various levels of power across a high voltage isolation transformer. In one embodiment of the invention, differential transformer driver pulses are provided to the primary side of the isolation transformer, with one of the pulses being delayed with respect to the other in order to improve transformer efficiency. The pulses may be repeated at a predetermined frequency, with the duty cycle of the pulse signals applied to the negative node of the primary side of the isolation transformer being equal to or greater than the duty cycle of the pulse signal applied to the positive node of the transformer. Further, the amount of power transferred to the secondary side of the transformer may be varied in accordance with the invention by varying the frequency and/or duty cycle of the differential transformer driver signals. In an alternate embodiment of the invention, a single-ended, variable duty cycle pulse is applied to the primary side of the transformer.

Description

METHOD OF TRANSFERRING POWER ACROSS AN ISOLATION BARRIER

Inventor

Frank Sacca Guang-Ming Yin Faouzi Chaahoub

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is based on and claims priority to U.S. Provisional

Application Serial No. 60/131,897 (Attorney Docket No. 99RSS112), filed April 30, 1999, and U.S. Provisional Application Serial No. 60/147,293 (Attorney Docket No. 99RSS273), filed August 4, 1999.

INCORPORATIONS BY REFERENCE The following commonly-assigned patent applications are hereby incorporated by reference in their entirety, including drawings and appendices, and are hereby made part of this application for all purposes:

1) U.S. Provisional Application Serial No. 60/131,897 (Attorney Docket No. 99RSS112), filed April 30, 1999;

2) U.S. Provisional Application Serial No. 60/147,293 (Attorney Docket No. 99RSS273), filed August 4, 1999; 3) U.S. Patent Application Serial No. 09/212,718 (Attorney Docket No. 98RSS128), filed December 16, 1998, entitled "On-Hook Telephone Line Event/Ring Monitor"; and 4) U.S. Patent Application Serial No. 09/193,113 (Attorney Docket No. 98RSS408), filed November 16, 1998, entitled "Modem Having A Programmable Universal Data Access Arrangement".

COPYRIGHT NOTICE A portion of the disclosure of this patent document and/or the provisional application on which it is based contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates generally to communication devices for coupling to a telephone line; and, more particularly, it relates to an efficient method for transferring various levels of power across a high voltage isolation barrier.

2. Related Art

Communication devices coupled to a telephone line generally include circuitry for providing ring signal detection capabilities. Incoming ring signals are normally detected and validated by examining the frequency range and voltage threshold level of the incoming signal. Individual countries throughout the world have specific threshold (amplitude) and frequency requirements for ring signals, complicating the design of such circuitry. The voltage threshold, in general, is set by using appropriate zener diodes. The voltage threshold is therefore generally fixed, and selection of the zener diodes is dependent on the country in which the circuit operates. This limitation is highly disadvantageous, as is the relatively high cost of the zener diodes and associated circuitry.

Further, electrical isolation requirements may complicate provision of power to ring detect circuitry. Subscriber equipment or data communications equipment (DCE), such as data modems, generally provide for some form of electrical isolation to prevent voltage surges or transients originating from the subscriber equipment or lightning from having a deleterious effect on the telephone network and vice versa. Electrical isolation also addresses potential problems sometimes associated with differences in operating voltages between a telephone line and the subscriber equipment. More particularly, telephone line voltages may vary widely across a given network, and often exceed the operating voltage of subscriber equipment. In the United States, 1,500 volt isolation is currently required. In other countries, the prescribed isolation may reach 3,000-4,000 volts.

Isolation transformers are often employed to magnetically couple signals between a two-wire telephone line and the analog front end of a modem or other circuit while maintaining an appropriate level of electrical isolation. The isolation transformer functions to block potentially harmful DC components, thereby protecting both sides of the data connection. The isolation transformer is typically part of what is referred to in the modem arts as a data access arrangement (DAA). The term DAA generally indicates circuitry which provides an interface between a public telephone network originating in a central office (CO) and a digital data bus of a host system or data terminal equipment (DTE). In addition to electrical isolation, the DAN may develop a number of signals (e.g., a ring signal) for provision to subscriber equipment. The DAA generally receives signals from the phone line through a telephone jack, such as a RJ11C connection as used for standard telephones. Traditional ring detection and validation circuitry is part of the DAA, and often derives power from the subscriber equipment in which it is incorporated. The amount of power required by prior ring detection and validation circuitry, in particular, may present problems in low power applications such as mobile computing, wherein a premium is placed on battery life. Likewise, in desktop computing, various power saving features may conflict with a desire to incorporate "wake-on-ring" or similar capabilities due to the power consumed by the ring detection and validation circuitry. For example, a precise integrated voltage threshold reference for use in amplitude validation implies the use of a band gap reference, which generally consumes a relatively large amount of power. Further, some modem configurations utilize a DAN having line side circuitry including telephone network interface and system side circuitry including a host system interface, the line side circuitry and system side circuitry being separated by the high voltage isolation barrier. Power for line side circuitry incorporating the ring detect circuitry may be communicated from the host system across an isolation transformer. Difficulties arise, however, in minimizing power dissipation due to losses typically incurred in transferring power across the high voltage isolation barrier of a DAA. The inherent inefficiencies in prior transformer circuitry requires that the system side supply more power than actually required by the line side circuitry to detect and validate ring signals or to perform other communications functions. Such inefficiencies may be particularly problematic in a wake- on-ring mode of operation in which power consumption specifications are very stringent.

Therefore, an efficient method for reducing power consumption by ring detection circuitry operating in a wake-on-ring or other low power state is desirable. Likewise, an improved method of transferring power across a high voltage isolation barrier is needed. SUMMARY OF THE INVENTION

Briefly, the present invention provides an efficient method and circuitry for transferring various levels of power across a high voltage isolation transformer. In one embodiment of the invention, differential transformer driver pulses are provided to the primary side of the isolation transformer, with one of the pulses being delayed with respect to the other in order to improve transformer efficiency.

The end of a first pulse and the beginning of the second pulse, for example, may overlap or be slightly delayed with respect to one another. The pulses may be repeated at a predetermined frequency, with the duty cycle of the pulse signals applied to the negative node of the primary side of the isolation transformer being equal to the duty cycle of the pulse signal applied to the positive node of the transformer. Further, the amount of power transferred to the secondary side of the transformer may be varied in accordance with the invention by varying the frequency and/or duty cycle of the differential transformer driver signals. In an alternate embodiment of the invention, a single ended pulse is applied to the primary side of the transformer.

Use of the disclosed transformer driver signals results in improved transformer efficiency, particularly when relatively small amounts of power are transferred across the isolation transformer.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of the present invention can be obtained when the following detailed description of an exemplary embodiment is considered in conjunction with the following drawings, in which: Figure 1 is a drawing of an exemplary data access arrangement implemented in accordance with the present invention;

Figure 2 is a schematic diagram providing exemplary details of the line side circuitry of the data access arrangement of Figure 1 ;

Figure 3 is a schematic diagram providing exemplary details of a high voltage isolation barrier comprising a transformer driven by differential signals in accordance with the present invention;

Figures 4A - 4C illustrate exemplary transformer driver waveforms according to the present invention;

Figure 5 is a block diagram providing exemplary details of the transformer driver circuitry of Figure 3 ;

Figure 6 is a schematic diagram providing exemplary details of alternate transformer driver circuitry implemented in accordance with the present invention;

Figures 7A, 7B and 7C are flowcharts depicting exemplary ring signal validation steps performed by the data access arrangement of Figure 1 in accordance with the present invention; and

Figure 8 is a schematic diagram of exemplary circuitry for implementing the programmable duty cycle circuitry of Figure 5 in accordance with the present invention. DETAILED DESCRIPTION OF THE INVENTION

Figure 1 is a drawing of an exemplary data access arrangement (DAA) implemented in accordance with the present invention The DAA provides ring detection and validation capabilities in a reduced power consumption mode As descπbed in greatei detail below in conjunction with Figures 3-6, a method and apparatus for improving power transfer across a high voltage isolation barrier is also provided

The disclosed embodiment of the DAA includes line side circuitry 100 and system side circuitry 104 separated by a high voltage isolation barrier 102 The line side circuitry 100 incorporates a telephone line interface 114 for developing signals from and providing signals to a telephone network 116 The line side circuitry 100 also includes πng detection capabilities utilizing a first threshold detection circuit 108 for identifying probable valid πng signals, and a second threshold detection circuit 110 for use in further validating the probable valid πng signals identified by the first threshold detection circuit 108 The first threshold detection circuit 108 is configured to consume less power than the second threshold detection circuit 110 In general, the second threshold detection circuit 110 is disabled until a probable valid πng signal has been identified, thus allowing the DAA to remain in an ultra-low power mode until higher accuracy, higher power validation circuitry is likely to be required

The disclosed embodiment of the line side circuitry 100 further includes comparator circuitry 112 having at least one input adapted to receive signals from the telephone A switch 106 is coupled to a second input of the comparator circuitry 112 to selectively provide a reference voltage from either the first threshold detection circuit 108 or the second threshold detection circuit 110 In this configuration, the switch 106 provides the output of the first threshold detection circuit 108 to the comparator circuitry 112 duπng a wake-on-rmg operating mode The output of the second threshold detection circuit is switched to the comparator circuitry following detection of a probable valid ring signal. The switch 106 can be controlled by the enhanced comparator circuitry 112 itself or, alternatively, by system side circuitry 104.

A programmable power supply 118 is provided in the system side circuitry 104 to generate at least two different of amounts of power for use by the line side circuitry 100. In one disclosed embodiment of the invention, the combined power consumption of the system side circuitry 104 and line side circuitry 100 does not exceed a specified power requirement, which is dependent on the operational mode of the system. At least three operational modes are contemplated (with exemplary power limitations): a) Ultra low-power mode - total power consumption not to exceed 3mW; b) Low-power mode - total power consumption not to exceed 15mW; and c) Normal operating mode - total power consumption not to exceed lOOmW.

In a wake-on-ring state, the system normally operates in ultra low-power mode until a probable valid ring signal is detected. Once such a signal is recognized, the programmable power supply 118 is switched to accommodate a low-power mode for performing further validation of the probable valid ring signal involving the second threshold detection circuit 110. Following validation of the probable valid ring signal, the system is placed in normal operating mode to conduct communication operations with the telephone network 116.

System side controller circuitry 120 is provided to determine the amount of power to transfer to the line side circuitry via the high voltage isolation barrier, as well as ring validation method being utilized at any given time. It is contemplated that the system side controller circuitry 120 could be included in an embedded device. Alternatively, the system side controller 120 functions could be performed by a host system processor, or by digital circuitry located in the line side circuitry 100. The line side circuitry 100 may also include detection circuitry that is programmable to measure electrical characteristics (e.g., ring detection circuitry) of a telephone line interface 114. The DAA may be software programmable via control signals sent across the high voltage isolation barrier 102 to establish ring detection criteria corresponding to a specific country where the equipment may be used. Exemplary details of a programmable ring detection circuit operable as a second threshold detection circuit 110 are described generally below, and in greater detail in previously incorporated U.S. Patent Application Serial No. 09/212/718. In typical wake-on-ring enabled systems, a valid ring signal must pass both voltage amplitude and frequency requirements before a "wake" signal is communicated to the host system. Frequency validation of an incoming ring signal can be accomplished in many ways. For example, a counter could be utilized to convert a reference clock signal of a predetermined frequency to a count range. The output of the comparator circuitry 112, which may be related to the frequency of the incoming ring signal, could then be "measured" using the counter to determine if the ring signal is within a specified frequency range corresponding to the requirements of a particular country. If necessary, the output of the comparator circuitry 1 12 can be "squared" to have approximately a 50% duty cycle prior to comparison to the count range. If a probable valid ring signal passes both amplitude and frequency tests, the ring signal is treated as a valid ring signal. Frequency validation circuitry can be included in either the line side circuitry 100 (as part of the comparator circuitry 112, for example) or the system side circuitry 104.

A CODEC such as that described in previously incorporated U.S. Patent Application Serial No. 09/193,113 may also be provided in the line side circuitry 100, such that encoded information generated by the CODEC, as well as information for decoding by the CODEC, is communicated across the high voltage isolation barrier 102. By placing the CODEC on the line side of the DAA, these communications may be accomplished in a digital manner, thereby permitting a reduction in the size and expense of the high voltage isolation barrier 102. It is also possible at this stage to capture caller ID information that typically follows the first ring signal.

A DAA in accordance with the present invention can be utilized with any product that interfaces a telephone network 116 to any digital signal processor technology, or any process of a host system that performs analog modem modulations. Examples include, but are not limited to, data modems, computers, web browsers, set top boxes, fax machines, cordless telephones and telephone answering machines. In addition, many different interfaces with the telephone network 1 16 and/or other transmission media are contemplated, such that the DAA may be configured to be compatible with whichever means is utilized.

Figure 2 is a schematic diagram providing exemplary details of the line side circuitry 100 of Figure 1. In this embodiment of the invention, a digital to analog converter (DAC) 132 is utilized as a programmable precision threshold reference for use in validating probable valid ring signals. The output voltage of the DAC 132 is selectively coupled to the " — " input of a comparator 130 by the switch 106. The output voltage level of the DAC 132 may be programmed to a previously determined country-specific value by a register 134 (located in either the line side circuitry 100 or the system side circuitry 104), or by software executing on a host system. The DAC 132 may be programmed before or after the system enters a wake-on-ring/ultra-low power mode.

The first threshold detection circuit 108 of this embodiment of the invention is comprised of a relatively large value resistor 136 and a forward biased diode 138 coupled in series between power and ground nodes of the line side circuitry 100. The fixed voltage at the common node of the resistor 136 and diode 138 is selectively coupled to the " — " input of the comparator 130 by the switch 106, and provides the voltage threshold used to identify probable valid ring signals while the DAA is in an ultra-low power mode. The value of the resistor 136 is relatively large in order to limit the amount of current through the diode 138. In this embodiment, the voltage threshold is equal to the voltage drop across the diode 138. Because the low power fixed voltage reference 108 is only used to identify probable valid ring signals, relatively low accuracy components may be utilized. The low power fixed voltage reference 108 is preferably designed such that the highest voltage provided to the comparator 130 is less than or equal to a minimum value (e.g., 15Vrms) for detecting line disturbances corresponding to worldwide ring signals.

The "+" input of the comparator 132 is driven by the output of an amplifier stage 140. The amplifier stage 140 functions to convert TIP and RING signals from a telephone line into a single-ended signal for provision to the comparator 130. The TIP signal is AC-coupled to the amplifier stage 140 via a capacitor 142a and a resistor 144a, while the RING signal is AC-coupled to the amplifier stage 140 via a capacitor 142b and a resistor 144b. Alternatively, the TIP and RING signals may be conditioned in a vary of ways, such as illustrated in the previously-incorporated patent applications, and the precise implementation is not considered critical to the invention.

The output of the DAC 132 can be programmed to a country-specific value for ring validation following receipt of a probable valid ring signal. As noted above, however, most high precision voltage reference circuitry such as DAC 132 consume more power than desirable for ultra-low power operation. When a ring signal is present and its represented value is higher than the threshold voltage established by the low power fixed voltage reference 108, then the ring is considered a probable valid ring signal and may be passed through the high voltage isolation barrier to the system to initiate a relatively higher power mode utilizing the DAC 132 for further validation of the probable valid ring signal. Frequency validation may be performed on the line side or system side prior to enabling the DAC 132. As will be appreciated by those skilled in the art, many operable modifications to the disclosed circuitry are possible. For example, separate comparators could be provided at the output nodes of the low power fixed voltage reference 108 and the DAC 132, with the outputs of the comparators being multiplexed to provide ring signal validation appropriate to a particular operating mode. Alternatively, a separate switch could be coupled in series with the resistor 136 and diode 138 to disable power to the low power fixed voltage reference 108 during periods in which the circuitry is not in use.

Figure 3 is a schematic diagram providing exemplary details of a high-voltage isolation barrier 102 comprising a transformer 200 having a primary side driven by differential signals DIB_P and DIB_N. The differential transformer driver signals DIB_P and DIB_N are used to transfer power from the system side circuitry 104 to the line side circuitry 100 via the transformer 200. In the disclosed embodiment of the invention, the efficiency of the transformer driver circuitry at low power levels is improved by driving the primary of the transformer 200 with offset differential signals having relatively small duty cycles (Figure 3) or a single ended signal having a relatively small duty cycle (Figure 6). It is also contemplated that offset differential signals DIB P and DIB_N having relatively high frequencies (e.g., 4 MHz) and/or duty cycles could be utilized to increase the efficiency of power transfer across the transformer 200.

The offset differential transformer driver signals DIB_P and DIB_N are provided to the transformer 200 by a programmable differential driver circuit 202 located in the system side circuitry 104. As will be appreciated by those skilled in art, the programmable differential driver circuit 202 may take many forms. Exemplary details of a programmable differential driver circuit 202 for use with the present invention are discussed below in conjunction with Figure 5. The secondary side of the transformer 200 is coupled to the power supply node VDD of the line side circuitry 100 via a rectifier diode 204. Energy for use by the line side circuitry 100 (provided in the form of a rectified signal) is stored by a capacitor 206 coupled between the power supply node VDD and ground node GND of the line side circuitry 100. In other contemplated embodiments, the rectifier diode 204 could be replaced by a full bridge rectifier. In addition, a regulator could be used in series between the rectifier diode and the capacitor 206 to limit the voltage provided to the line side circuitry 100 without limiting or clamping the voltage across the terminals of the transfom er 200.

A clock signal CLK may also be transferred across the high voltage barrier 102 in conjunction with the transformer driver signals. It should be noted that the transformer should have relatively good operating characteristics at the clock frequency of interest. Any such clock signals are preferably AC-coupled from the secondary of the transformer 200 to the line side circuitry 100 via a series-connected capacitor 210 and a current limiting resistor 212. In addition, the high voltage isolation barrier 102 may also include one or more capacitors 208 for communicating alternate clock signals and/or bi-directional data between the system side circuitry 104 and the line side circuitry 100.

As noted above, the efficiency of the transformer 200 will impact the total power consumption of the DAA. If the maximum total power consumption of the DAA in ultra low-power mode is specified at 3mW, for example, the power consumption of the line circuitry 100, the system side circuitry 104, as well as losses to the transformer 200 must all be considered in the power budget calculation. The ratio of the power used by the line side circuitry 100 and the power supplied by the system side circuitry 104, multiplied by 100, provides a numerical approximate of the efficiency of the transformer:

PLme_s-de / Psys_s.de X 100 = (eta), where lLine Sιde------_----,Lιne Side X ' Line Side Svs Side ^— iSvs Side X Svs Side

In the embodiment of the invention disclosed in Figure 3, the efficiency of power transfer across the transformer 200 is improved by providing offset differential transformer driver signals DIB_P and DIB_N to the primary side of the transformer 200. Further, the duty cycles of the respective differential signals may be adjusted to accommodate power consumption constraints placed on the DAA. Generally, a decrease in the duty cycle of the signals applied to the primary of the transformer 200 is reflected by a decrease in current and a corresponding decreasing power supplied to the secondary side of the transformer 200. More specifically, in the first cycle, a square wave input signal at output DIB_P is

applied to the primary side of the transformer 200 with a duty cycle Δ. In this cycle current

through the transformer 200 increases linearly with time (L x I = V x t) according to the general equation for an inductor, Ldi/dt = V where V is the amplitude of the square wave signal (constant) and t is the time the square wave is at a logic HIGH voltage level. If the

duty cycle Δ is expressed as a percentage of the clock period T, the time value t can be

expressed as t = Δ x T = Δ/f, where f is the frequency of the input (driving) signal. For

example, a 50% duty cycle yields a time value of t = 0.5T. Power transfer in the transformer during time T can be represented by the following equation:

[1] P = Vi Lp Ipeak f, where Lp is the primary inductance of the transformer, and I_peak is the peak current reached in the inductor during one period of the input signal or after time t=ΔT. The duty cycle Δ of the input signal is related to I_peak according to the following equation:

[2]

_ V - Δ - T V - Δ ^~ Lp ^~ Lp -f

Therefore, an increase in the duty cycle of the input clock signal is reflected to an increase in peak current, which results in a corresponding increase in power to the transformer

according to equation [1]. Substituting equation [2] into equation [1] yields P= W ² x Δ² /

Lp x f, which illustrates that the duty cycle Δ has a greater effect than frequency in power

transfer to the transformer 200.

In the second cycle, when the voltage at the primary side of the transformer 200 is "reversed" in accordance with the invention by applying a time-delayed, positive signal at DIB_N, current flows in the secondary through diode 204 and causes magnetic fluxes in the transformer core which tend to cancel the flux generated by the primary current. Hence, the equivalent inductance of the transformer 200 seen at the primary side is lowered (preferably to zero), and the peak current I_peak becomes related to the current Is in the secondary side by the formula I_peak ⁼N x Is, where N is the turn ratio of the secondary winding of the transformer 200 to its primary winding. Also, the voltage Vs at the secondary side of the transformer 200 is related to the voltage Vp at the primary side by the formula Vs = N x Vp. Assuming that Vs = Vdd (the forward voltage drop of diode 204 can be neglected with respect to Vdd) and that Vp = Vcc - Rdib x lp, where Vcc is the power supply voltage on the system side circuitry 104 (or Vp max) and Rdib is the total combined output resistance of transformer driver circuitry that provides the transformer driver signals DIB_P and DIB_N, it is possible to relate the duty cycle of the clock signal to the voltage Vdd expected on the line side and load RL present on the line side using the following equation: [3]

Duty Cycle = [(N² x Rdib)/(N x Vcc - Vdd)] x (Vdd/RL).

Equation [3] demonstrates that the duty cycle is a function of the output resistance of the transformer driver circuitry, and of the load on the secondary side. Therefore, an alternative method to control the power delivered to the line side involves varying the quantity Rdib using an array of switches controlled by a separate control register on the system side or other impedance control circuitry to adjust the impedance of the transformer driver circuitry. For example, the impedance control circuitry could be used to effectively vary the size (W/L) of the output transistors in the transformer driver circuitry to vary the transistors' on-resistance (Rdib).

Since the peak current I_peak in the second cycle is related to the current consumption in the line side circuitry 100, the power delivered to the transformer 200 is limited by power losses in the primary side equal to Rdib x I_peak . However, if the primary of the transformer 200 is "precharged" as described in the first cycle discussed above, the energy stored in the primary side (! ^•> Lp I_peak ) is used in conjunction with the current I_peak of the second cycle to transfer energy to the line side circuitry 100. This combination of factors can improve power efficiency considerably, depending on the load and duty cycles selected for the transformer driver signals DIB_P and DIB_N.

To achieve relatively good efficiency, therefore, it is important to apply the appropriate clock polarity sequence to the primary of the transformer 200 so that the first cycle corresponds to a charging phase with current flowing only in the primary. Also, it may be important that the transformer driver signals DIB P and DIB_N are of equal pulse width, respectively, so that the DC average voltage applied to the primary side of the transformer is approximately zero. This approach increases efficiency because the equivalent DC current flowing through the primary of the transformer is approximately zero.

Although it is contemplated that a clock signal may be supplied to the line side circuitry 100 via the transformer 200, this configuration requires that the transformer 200 be optimized for the specified clock frequency. Also, in order to comply with FCC and other government regulations throughout the world, this configuration may require additional circuitry to suppress the clock signal and its related harmonics injected into the telephone network.

Alternatively, a relatively large value capacitor 634 (Figure 6) coupled between the ground nodes of the system side circuitry 104 and the line side circuitry 100 may be used to provide a return path or ground reference for signals transferred between the system side circuitry 104 and line side circuitry 100. Such a configuration reduces the need to use differential drivers to transfer data between the two sides, permitting a single, relatively small value capacitor to be used for each data path and for a clock signal. This configuration also enables relatively easy compliance with regulatory requirements addressing radio frequency emissions, because the frequency of the power clock to the transformer 200 can be chosen to be outside the range measured by the FCC, for example, independently of the signal clock delivered to the line side circuitry 100.

Another advantage provided by such a configuration is that the frequency and duty cycle of the differential transformer driver signals DIB P and DIB_N can be chosen to match and optimize the characteristics of the transformer 200. Therefore, by choosing an optimal frequency for the transformer outside the bands where the FCC is most restrictive, and by varying the duty cycle, it is possible to maintain efficient control over the power delivered to the line side circuitry 100 via the transformer 200 without affecting regulatory compliance. Command or programming signals may also be multiplexed and serialized for transmission across the isolation barrier 102, thereby reducing the complexity and expense of the isolation barrier 102. Data signals may also be combined with command or programming signals, further simplifying the isolation barrier 102. Figures 4A - 4C illustrate exemplary waveforms for differential transformer driver signals DIB_P and DIB_N in accordance with the present invention. In general, the amount of power transferred across the transformer 200 is related to both the duty cycle and frequency of the driver signals, assuming a typical voltage (e.g., 3.3 volts) on the system side. In an ultra-low power mode, for example, the duty cycles of the transformer driver signals DIB_P and DIB_N may be approximately l%-2% with a frequency of 330KHz.

Referring more specifically to Figure 4A, a leading pulse 400 is provided by the transformer driver signal DIB_P to the negative terminal of the primary side of the transformer 200. Immediately following the initial pulse 400, a lagging pulse 402 is provided by the transformer driver signal DIB_N to the positive terminal of the primary side of the transformer 200. The initial pulse 400 functions to precharge the transformer 200 before energy is transferred to the secondary load by the pulse 402. This configuration improves the efficiency of the energy transfer across the transformer 200. More specifically, if the charging pulse is applied in a direction such that current does not flow in the secondary circuit (diode 204 reverse- biased), the inductance seen by the driver circuits is equivalent to the inductance of the primary side of the transfomier 200, and energy can be efficiently stored in the transformer 200. In the next phase, the stored energy in the transformer 200 is discharged to the secondary load and partially "returned" to the power supply of the primary driver. The respective periods 404 and 408 of the differential transformer driver signal DIB_P and DIB_N, respectively, are preferably equal such that differential pulses are consistently spaced with respect to one another. It should also be noted that the respective duty cycles of the transformer driver signals DIB_P and DIB_N may affect the efficiency of power transfer across the transformer 200. In the waveforms illustrated in Figure 4A, the leading pulse 400 of the transformer driver signal DIB_P has a width 410 (i.e., duty cycle) that is equal to the width 406 of a pulse 402 of the transformer driver signal DIB_N. However, it may be beneficial to change the duty cycles of the transformer driver signals DIB P and DIB_N with respect to each other to balance the charge and discharge phases with respect to the load on the secondary and improve the overall efficiency of the power transfer from the system side circuitry 104 to the line side circuitry 100.

Figure 4B illustrates an alternate embodiment of the invention in which pulses 420 of the transformer driver signal DIB_N precede pulses 422 of the transformer driver signal DIB_P. Again, the offset relationship between the pulses 420 and 422 provides improved power transfer characteristics as compared to prior solutions.

Figure 4C illustrates a relatively higher power mode of operation in which the period

430 of both the transformer driver signals DIB P and DIB N corresponds to a relatively high frequency (e.g., 4 MHz). Increases in the duty cycles of the transformer driver signals DIB_P and DIB_N may also be effected in order to increase power delivered to the line side circuitry 100.

Figure 5 is a block diagram providing details of the programmable differential driver circuit 202 in Figure 3. In the illustrated embodiment, a ring oscillator 500 and a pair of dividers/programmable duty cycle circuits 502 and 504 are provided in the system side circuitry 104. In operation, the output of the ring oscillator 500 is provided as a reference clock to each of the divider/programmable duty cycle circuits 502 and 504. The divider/programmable duty cycle circuit 502 is programmed to divide the frequency of the signal provided by the ring oscillator 500 to a desired value, and is also capable of adjusting the duty cycle of the transformer driver signal DIB_P. Likewise, the dividers/programmable duty cycle circuit 504 is programmable to divide the frequency of the signal received from the ring oscillator 500 to a desired value. The divider/programmable duty cycle circuit 504 is also programmable to vary the duty cycle of the transformer driver signal DIB_N in general accordance with the exemplary wave form depicted in Figures 4 A and 4B. Figure 8 provides exemplary details of the divider/programmable duty cycle circuitry 502 and 504. Figure 6 is a schematic diagram providing exemplary details of alternate transformer driver circuitry implemented in accordance with the present invention. In this embodiment of the invention, the transformer 200 is driven by a single-ended transformer driver signal provided at the output of a comparator 612. The single-ended transformer driver signal controls the gate of an external transistor 600 having a drain node connected to one side of the primary side of the transformer 200, and a source node connected to a system side ground reference. The opposing side of the primary side of the transformer 200 is connected to a power supply VCC of the system side, such that current flows through the primary side of the transformer 200 during periods in which the transistor is turned on. The charging phase of the transformer 200 occurs when the transistor 600 is on, while the discharging phase of the transformer 200 occurs when the transistor 600 is off. Current does not flow on the secondary during the charge phase (the transformer polarity is reversed in Figure 6), and therefore this configuration is efficient. Furthermore, during the discharge phase power is only delivered to the load on the secondary and is not returned to the primary drivers as in the differential configuration. Nevertheless, the single-ended configuration provides improved efficiency over prior solutions.

In this embodiment of the invention, an analog duty-cycle control circuit is used to generate the control signal to the transistor 600. More specifically, a resistor 606 and capacitor 608 are coupled in series between the power supply VCC and ground node GND of the system side. The voltage established at the common node 611 is provided to one input of a comparator 604 with hysterisis. The voltage at node 611 is compared to an internal reference voltage VREF provided to the other input of the comparator 604. When the reference voltage VREF is exceeded by the voltage at node 611, the comparator 604 output transitions to a logic high state. This output is provided to the gate of a transistor 610 coupled between the node 611 and the ground of the system side, such that the transistor 610 turns on in response to a logic high signal. While on, the transistor 610 functions to discharge the capacitor 608, eventually causing voltage at the node 611 to be less than the reference voltage VREF. The output of the comparator 604 then returns to a logic low level. At this point, the resistor 606 begins to recharge the capacitor 608, and the process is repeated. The result is a "sawtooth"-like signal at the node 611. This signal is provided to one input of the comparator 612. The voltage at node 61 1 may be configured to have an extremely low duty cycle, with the frequency tolerance determined by the resistor 606 and capacitor 608, the equivalent resistance of the transistor 610, and the hysterisis of the comparator 604. An additional resistor (not shown) may be provided to permit adjustments to the hysterisis of the comparator 604.

A programmable voltage level is provided to the other input of the comparator 612. The programmable voltage reference 614 is controlled by a 5 bit duty cycle register 618 with an associated logic decoder 616. The outputs DC0-DC31 of the logic decoder 616 control a bank of switches 620 used to selectively couple various points of the programmable reference 614 to an input of the comparator 612. In this embodiment of the invention, the programmable reference 614 is configured as a resistor divider having various tap points. The sawtooth-like waveform at node 610 is compared to the voltage at a selected tap point, resulting in a signal at the output of comparator 612 having a variable dut> cycle based upon the voltage reference selected by the duty cycle register 618. The duty cycle register 618 may be programmed to accommodate various power states, including an ultra-lower power mode, a low power mode, and a normal operating power mode. Alternatively, a programmable duty cycle circuit such as that described above could be used as a control signal to the gate of the transistor 600.

The high voltage isolation barrier 102 of Figure 6 may include a capacitor 630 for communicating a clock signal from the system side circuitry 102 to the line side circuitry 100. This configuration permits the power clock to be independent of the system digital clock, which may beneficially decrease EMI emissions. One or more data path capacitors 632 are also included in the high voltage isolation barrier 102. A capacitor 634 is also provided as discussed above to provide a common ground reference between the system side circuitry 102 and the line side circuitry 100.

Figures 7A, 7B and 7C are flow charts depicting exemplary ring signal validation steps performed by the data access arrangement of Figure 1 in accordance with the present invention. In step 700, the circuitry of the data access arrangement is placed into a wake-on- ring mode in which power consumption is reduced until a valid incoming ring signal is detected.

In step 702, first threshold detection circuitry (e.g., the low power threshold reference 108 of Figure 1) is activated to provide a voltage reference to comparator circuitry 112. This permits the line side circuitry 100 to detect probable valid ring signals. In addition, in step 702, the second (programmable) threshold reference 110 is disabled or placed in a low power state.

In order to reduce power consumption during the wake-on-ring mode, the programmable power supply 118 is set to an ultra-low power mode in step 704. Next, in step 706, a state machine in the system side circuitry 104 is programmed to a wake-on-ring/ultra- low power mode. The state machine may be executed by controller circuitry 120, or by processing circuitry of a host system. The data access arrangement remains in this state until a probable valid ring signal is detected in step 708. Following detection of such a signal, a signal is provided from the line side circuitry 100 to the system side circuitry 104 in step 710 to indicate that a probable valid ring signal has been received and should be further validated.

The process then continues in step 712 (Figure 7B) where the programmable power supply 118 is programmed to a low power mode. Next, in step 714, the second threshold reference 110 is activated while the first threshold reference 108 is disabled. Disabling of the second threshold reference 110 may include merely switching the input to the comparator circuitry 112 between the two references, or disabling power to the second threshold reference 110 itself. A country-specific value may be programmed into the second threshold reference 110 in optional step 716. The country-specific value may be imposed by a value previously stored in software, or via a register located on either the line side or the system side.

The process then continues in step 718 and the system side state machine is set to a ring amplitude validation mode to direct further validation operations on the probable valid incoming ring signal. These operations include determining if the represented amplitude value of the probable valid ring signal is greater than the voltage threshold value established by the second threshold reference 110 (step 720). If not, the process returns to step 702 to return to an ultra-low power mode and await further probable valid incoming ring signals.

If the probable valid incoming ring signal is greater than the second threshold value, a corresponding signal is communicated from the line side circuitry 100 to the system side circuitry 104. This signal may comprise the output of the comparator circuitry 112. Next, in step 724, further validation, such as cadence and frequency validation, is performed on the probable valid ring signal.

If the probable valid ring signal is not validated as determined in step 726, the process again returns to step 702 to return to an ultra-low power mode/wake-on-ring mode and await further probable valid incoming ring signals. Alternatively, if the probable valid ring signal is validated, the host system is placed in an awake state in step 728 and the programmable power supply 118 is programmed to provide a normal level of operating power. Normal communications operations are then carried out between the telephone network 1 16 and the data access arrangement of the disclosed embodiment of the invention. It should be noted that the ordering of many of the aforementioned steps is not considered critical to the invention. For example, step 724 could be performed prior to or in parallel with amplitude validation. Likewise, the programmable power supply 1 18 could be placed in a normal operating mode following detection of probable valid ring signal but prior to complete validation the probable valid ring signal. Figure 8 is a schematic diagram of an exemplary digital circuit for implementing independent duty cycle control for signal outputs DIB_P and DIB_N in accordance with the present invention. A synchronous counter 800 is provided for dividing the frequency of a master clock signal provided to a clock input CLK. More specifically, the synchronous counter 800 provides outputs Ql, Q2, Q3 and Q4 that divide the master clock signal by two, four, eight and sixteen, respectively.

The outputs Ql, Q2, Q3 and Q4 are individually provided to the inputs of a four-input NOR gate 802 to generate an output signal (shown as wavefomr 810) with a base duty cycle equal to 1/16^th (6.25%) of the master clock period. The output signal 810 is provided to the input of a shift register 830 having outputs SI through S8. The shift register 830 shifts the input signal 810 by one through eight master clock cycles, which are provided by the outputs

S1-S8.

The outputs S1-S8 are individually provided to one input of one the AND gates in an array 812 of eight AND gates. The second input of each AND gate in the aπay 812 is coupled to one of the control signal P1-P8 provided by a duty-cycle control register 840. The output of each AND gate in the array 812 is provided to an input of the eight-input OR gate 816. The output of the OR gate 816 is designated as the duty-cycle controlled transformer driver signal DIB_P. Similarly, the outputs S1-S8 are also individually provided to one input of one the

AND gates in an array 814 of eight AND gates. The second input of each AND gate in the aπay 814 is coupled to one of the control signal N1-N8 provided by a duty-cycle control register 860. The output of each AND gate in the aπay 814 is provided to an input of the eight-input OR gate 818. The output of the OR gate 818 is designated as the duty-cycle controlled transformer driver signal DIB_N.

Setting one or more of the outputs P1-P8 of the duty-cycle control register 840 to a logic high level results in a digital wave form for the transformer driver signal DIB P which reflects the selected pattern of control signals P1-P8. For example, wave form 840a reflects a pattern combination wherein P1=HIGH, while P2-P8=LOW. Wave forms 840b, 840c and 840d similarly result from other combinations of control signals P1-P8.

Likewise, setting one or more of the outputs N1-N8 of the duty-cycle control register 860 to a logic high level results in a digital wave form for the transformer driver signal DIB_N which reflects the selected pattern of control signals N1-N8. For example, wave form 860c reflects a pattern combination wherein Nl=N2=N3=LOW, N4=N5=N6=HIGH, while N7=N8=LOW. Wave forms 860a, 860b and 860d similarly result from other combinations of control signals P1-P8.

The circuitry of Figure 8 has substantial flexibility in that the transformer driver signals DIB_P and DIB_N can be shifted with respect to each other via appropriate settings in the duty-cycle control registers 840 and 860. For example, the transformer driver signal DIB_P can be selected to lead, lag, or overlap the transformer driver signal DIB_N, and vice- versa. Furthermore, the duty cycle of each transformer driver signal DIB_N and DIB P can be selected independently, permitting optimization of efficiency in the transformer driver. If the base duty cycle of the waveform 810 is to be decreased from 6.25% for higher resolution, the circuit design may remain essentially the same except that the synchronous counter 800 and NOR gate 802 may be increased in size to generate a lower base duty cycle. For example, to obtain a base duty cycle of 1/128th, equivalent to approximately 0.78%o duty cycle steps, counter 800 would be increased to eight bits and NOR gate 802 to eight inputs. It is further contemplated that counter 800 can be asynchronous, provided that a D-type flip- flop is added at the output of NOR gate 802, with a clock signal shifted by one-half clock cycle (inverted) with respect to the master clock. As will be recognized by those skilled in the art, numerous other circuit topologies could be utilized to implement independent duty cycle control for transformer driver signals DIB_P and DIB_N. Thus, an efficient method and circuitry have been described for transferring various levels of power across a high-voltage isolation barrier. The use of offset pulses to drive the primary side of an isolation transformer or a single duty cycle pulse results in improved transformer efficiency and reduces overall power consumption in the system.

In view of the above detailed description of the present invention and associated drawings, other modifications and variations will now become apparent to those skilled in the art. It should also be apparent that such other modifications and variations may be effected without departing from the spirit and scope of the present invention.

Claims

CLAIMS We claim: L A method for transferring power to the secondary side of an isolation transformer having a primary side with first and second input nodes, comprising: providing a first pulse signal to the first input node; providing a second pulse signal to the second input node; and the second pulse signal being delayed with respect to the first pulse signal.

2. The method of claim 1, the first and second pulse signals each having a beginning edge and an ending edge, wherein there is substantially no delay between the ending edge of the first pulse and the beginning edge of the second pulse.

3. The method of claim 1 , wherein the first input node is configured as the negative node of the primary side, and the second input node is configured as the positive node of primary side.

4. The method of claim 3, wherein the first pulse signal and the second pulse signal are repeated at a predeteπnined frequency, the duty cycle of the repeated first pulse signals being greater than the duty cycle of the repeated second pulse signals.

5. The method of claim 4, wherein the duty cycle of the repeated second pulse signals is in the range of approximately 5-10 %.

6. The method of claim 1 wherein the first pulse signal and the second pulse signal are repeated at a predetermined frequency.

7. The method of claim 6, further comprising: varying the amount of power transfeπed to the secondary side of the isolation transformer by varying the predetermined frequency.

8. The method of claim 1, further comprising: repeating the first pulse signal and the second pulse signal at a predetermined frequency; and selectively varying the duty cycles of the repeated first and second pulse signals to vary the amount of power transfeπed to the secondary side of the isolation transformer.

9. The method of claim 8, wherein the duty cycles of the repeated first and second pulse signals are selectively varied with respect to one another.

10. A data access aπangement, comprising: an isolation transformer having a primary side with first and second input nodes and a secondary side; transformer driver circuitry coupled to the first and second nodes of the primary side of the isolation transformer, the transformer driver circuitry configurable to provide a first pulse signal to the first node and a second pulse signal to the second node, the second pulse signal being delayed with respect to the first pulse signal.

11. The data access aπangement of claim 10, wherein there is substantially no delay between the end of the first pulse signal and the beginning of the second pulse signal.

12. The data access aπangement of claim 10, wherein the first and second pulse signals are repeated at a predetermined frequency.

13. The data access aπangement of claim 12, wherein the duty cycle of the repeated first pulse signals is greater than the duty cycle of the repeated second pulse signals.

14. The data access aπangement of claim 13, wherein the duty cycle of the repeated second pulse signals is in the range of approximately 5-10%.

15. The data access aπangement of claim 12, wherein the transformer driver circuitry is further configurable to vary the amount of power transfeπed to the secondary side of the isolation transformer by varying the predetermined frequency.

16. The data access aπangement of claim 12, wherein the transformer driver circuitry is further configurable to vary the duty cycles of the repeated first and second pulse signals to vary the amount of power transfeπed to the secondary side of the isolation transformer

17. The data access aπangement of claim 16, wherein the duty cycles of the repeated first and second pulse signals are selectively varied with respect to one another.